Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_mubi4_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_io_step_down_req_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_io_div2_div_scanmode_sync 100.00 100.00 100.00
tb.dut.u_io_div4_div_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_main_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_io_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_usb_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_io_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_io_div2_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_io_div4_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_main_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_usb_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_clk_io_div4_peri_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_io_div2_peri_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_io_peri_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_usb_peri_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clk_main_aes_trans.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync 100.00 100.00 100.00


Module Instance : tb.dut.u_io_step_down_req_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_io_div2_div_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_io_div4_div_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_main_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_div2_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_div4_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_usb_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_io_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_div2_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_div4_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_main_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_main_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_usb_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_io_peri_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_usb_peri_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_aes_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_aes_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_hmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_hmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_kmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_kmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_otbn_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_otbn_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_io_step_down_req_sync

SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync

SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync

Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_io_div2_div_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div4_div_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_main_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_io_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_usb_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_io_div4_peri_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_io_div2_peri_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_io_peri_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_usb_peri_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_aes_trans.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_calib_rdy_sync

Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 6 6

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_io_meas.u_calib_rdy_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div2_meas.u_calib_rdy_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div4_meas.u_calib_rdy_sync

SCORELINE
100.00 100.00
tb.dut.u_main_meas.u_calib_rdy_sync

SCORELINE
100.00 100.00
tb.dut.u_usb_meas.u_calib_rdy_sync

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1

Cond Coverage for Module : prim_mubi4_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6
Branch Coverage for Module : prim_mubi4_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 22512 22512 0 0
OutputsKnown_A 2147483647 2147483647 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 1082316990 1065969936 0 14472
gen_flops.gen_stable_chks.OutputDelay_A 2147483647 2147483647 0 16884
gen_flops.gen_stable_chks.OutputIfUnstable_A 2147483647 211388 0 0
gen_no_flops.OutputDelay_A 2147483647 2147483647 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22512 22512 0 0
T1 28 28 0 0
T4 28 28 0 0
T5 28 28 0 0
T6 28 28 0 0
T17 28 28 0 0
T24 28 28 0 0
T25 28 28 0 0
T26 28 28 0 0
T27 28 28 0 0
T28 28 28 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 8895122 8881676 0 0
T4 2903519 2899734 0 0
T5 31751 29712 0 0
T6 137958 124567 0 0
T17 38780 37110 0 0
T24 57556 53187 0 0
T25 36793 31962 0 0
T26 75534 73119 0 0
T27 66830 64553 0 0
T28 159539 157024 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1082316990 1065969936 0 14472
T1 1190364 1188300 0 18
T4 671136 670188 0 18
T5 7302 6786 0 18
T6 31380 27978 0 18
T17 8832 8406 0 18
T24 12972 11904 0 18
T25 8472 7272 0 18
T26 6966 6708 0 18
T27 6210 5952 0 18
T28 7626 7476 0 18

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 16884
T1 2901022 2895980 0 21
T4 773987 772817 0 21
T5 8471 7872 0 21
T6 36926 32925 0 21
T17 10393 9893 0 21
T24 15498 14216 0 21
T25 9828 8436 0 21
T26 26343 25404 0 21
T27 23477 22538 0 21
T28 59869 58752 0 21

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 211388 0 0
T1 2901022 1345 0 0
T2 362004 0 0 0
T3 0 312 0 0
T4 462352 4 0 0
T5 4868 12 0 0
T6 36926 267 0 0
T17 10393 16 0 0
T18 9754 88 0 0
T20 0 20 0 0
T21 0 6 0 0
T24 15498 123 0 0
T25 9828 8 0 0
T26 26343 119 0 0
T27 23477 32 0 0
T28 59869 166 0 0
T103 0 9 0 0
T104 0 46 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4803736 4797370 0 0
T4 1458396 1456690 0 0
T5 15978 15015 0 0
T6 69652 63547 0 0
T17 19555 18772 0 0
T24 29086 27028 0 0
T25 18493 16215 0 0
T26 42225 40968 0 0
T27 37143 36024 0 0
T28 92044 90757 0 0

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T24,T26 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T24,T26 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T24,T26 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T24,T26
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T6,T24,T26
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T6,T24,T26
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T6,T24,T26
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T6,T24,T26
0 Covered T4,T5,T6

Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 459400022 454846185 0 0
gen_flops.gen_stable_chks.OutputDelay_A 459400022 454839081 0 2412
gen_flops.gen_stable_chks.OutputIfUnstable_A 459400022 30214 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459400022 454846185 0 0
T1 481426 480586 0 0
T4 87923 87760 0 0
T5 1169 1089 0 0
T6 5122 4576 0 0
T17 1441 1374 0 0
T24 2162 1987 0 0
T25 1356 1167 0 0
T26 4649 4487 0 0
T27 4143 3981 0 0
T28 11095 10891 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459400022 454839081 0 2412
T1 481426 480584 0 3
T4 87923 87757 0 3
T5 1169 1086 0 3
T6 5122 4567 0 3
T17 1441 1371 0 3
T24 2162 1984 0 3
T25 1356 1164 0 3
T26 4649 4484 0 3
T27 4143 3978 0 3
T28 11095 10888 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459400022 30214 0 0
T1 481426 249 0 0
T2 180998 0 0 0
T3 0 123 0 0
T6 5122 55 0 0
T17 1441 0 0 0
T18 6242 37 0 0
T20 0 9 0 0
T21 0 3 0 0
T24 2162 39 0 0
T25 1356 0 0 0
T26 4649 29 0 0
T27 4143 10 0 0
T28 11095 33 0 0

Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 180386165 177668965 0 0
gen_no_flops.OutputDelay_A 180386165 177668965 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177668965 0 0
T1 198394 198052 0 0
T4 111856 111701 0 0
T5 1217 1134 0 0
T6 5230 4672 0 0
T17 1472 1404 0 0
T24 2162 1987 0 0
T25 1412 1215 0 0
T26 1161 1121 0 0
T27 1035 995 0 0
T28 1271 1249 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177668965 0 0
T1 198394 198052 0 0
T4 111856 111701 0 0
T5 1217 1134 0 0
T6 5230 4672 0 0
T17 1472 1404 0 0
T24 2162 1987 0 0
T25 1412 1215 0 0
T26 1161 1121 0 0
T27 1035 995 0 0
T28 1271 1249 0 0

Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 180386165 177668965 0 0
gen_no_flops.OutputDelay_A 180386165 177668965 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177668965 0 0
T1 198394 198052 0 0
T4 111856 111701 0 0
T5 1217 1134 0 0
T6 5230 4672 0 0
T17 1472 1404 0 0
T24 2162 1987 0 0
T25 1412 1215 0 0
T26 1161 1121 0 0
T27 1035 995 0 0
T28 1271 1249 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177668965 0 0
T1 198394 198052 0 0
T4 111856 111701 0 0
T5 1217 1134 0 0
T6 5230 4672 0 0
T17 1472 1404 0 0
T24 2162 1987 0 0
T25 1412 1215 0 0
T26 1161 1121 0 0
T27 1035 995 0 0
T28 1271 1249 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T26,T27 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T26,T27 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T26,T27 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T26,T27
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T6,T26,T27
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T6,T26,T27
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T6,T26,T27
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T6,T26,T27
0 Covered T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 180386165 177668965 0 0
gen_flops.gen_stable_chks.OutputDelay_A 180386165 177661656 0 2412
gen_flops.gen_stable_chks.OutputIfUnstable_A 180386165 18951 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177668965 0 0
T1 198394 198052 0 0
T4 111856 111701 0 0
T5 1217 1134 0 0
T6 5230 4672 0 0
T17 1472 1404 0 0
T24 2162 1987 0 0
T25 1412 1215 0 0
T26 1161 1121 0 0
T27 1035 995 0 0
T28 1271 1249 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177661656 0 2412
T1 198394 198050 0 3
T4 111856 111698 0 3
T5 1217 1131 0 3
T6 5230 4663 0 3
T17 1472 1401 0 3
T24 2162 1984 0 3
T25 1412 1212 0 3
T26 1161 1118 0 3
T27 1035 992 0 3
T28 1271 1246 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 18951 0 0
T1 198394 173 0 0
T2 90503 0 0 0
T3 0 96 0 0
T6 5230 37 0 0
T17 1472 0 0 0
T18 1756 23 0 0
T20 0 6 0 0
T24 2162 0 0 0
T25 1412 0 0 0
T26 1161 30 0 0
T27 1035 7 0 0
T28 1271 33 0 0
T103 0 9 0 0
T104 0 46 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T24,T26 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T24,T26 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T24,T26 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T24,T26
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T6,T24,T26
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T6,T24,T26
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T6,T24,T26
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T6,T24,T26
0 Covered T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 180386165 177668965 0 0
gen_flops.gen_stable_chks.OutputDelay_A 180386165 177661656 0 2412
gen_flops.gen_stable_chks.OutputIfUnstable_A 180386165 21480 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177668965 0 0
T1 198394 198052 0 0
T4 111856 111701 0 0
T5 1217 1134 0 0
T6 5230 4672 0 0
T17 1472 1404 0 0
T24 2162 1987 0 0
T25 1412 1215 0 0
T26 1161 1121 0 0
T27 1035 995 0 0
T28 1271 1249 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177661656 0 2412
T1 198394 198050 0 3
T4 111856 111698 0 3
T5 1217 1131 0 3
T6 5230 4663 0 3
T17 1472 1401 0 3
T24 2162 1984 0 3
T25 1412 1212 0 3
T26 1161 1118 0 3
T27 1035 992 0 3
T28 1271 1246 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 21480 0 0
T1 198394 171 0 0
T2 90503 0 0 0
T3 0 93 0 0
T6 5230 32 0 0
T17 1472 0 0 0
T18 1756 28 0 0
T20 0 5 0 0
T21 0 3 0 0
T24 2162 33 0 0
T25 1412 0 0 0
T26 1161 29 0 0
T27 1035 8 0 0
T28 1271 42 0 0

Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 491126341 488717753 0 0
gen_no_flops.OutputDelay_A 491126341 488717753 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 488717753 0 0
T1 505702 505370 0 0
T4 115588 115547 0 0
T5 1217 1162 0 0
T6 5336 5139 0 0
T17 1502 1461 0 0
T24 2253 2141 0 0
T25 1412 1286 0 0
T26 4843 4703 0 0
T27 4316 4232 0 0
T28 11558 11432 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 488717753 0 0
T1 505702 505370 0 0
T4 115588 115547 0 0
T5 1217 1162 0 0
T6 5336 5139 0 0
T17 1502 1461 0 0
T24 2253 2141 0 0
T25 1412 1286 0 0
T26 4843 4703 0 0
T27 4316 4232 0 0
T28 11558 11432 0 0

Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 459400022 457106580 0 0
gen_no_flops.OutputDelay_A 459400022 457106580 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459400022 457106580 0 0
T1 481426 481108 0 0
T4 87923 87884 0 0
T5 1169 1117 0 0
T6 5122 4933 0 0
T17 1441 1402 0 0
T24 2162 2055 0 0
T25 1356 1235 0 0
T26 4649 4515 0 0
T27 4143 4063 0 0
T28 11095 10974 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459400022 457106580 0 0
T1 481426 481108 0 0
T4 87923 87884 0 0
T5 1169 1117 0 0
T6 5122 4933 0 0
T17 1441 1402 0 0
T24 2162 2055 0 0
T25 1356 1235 0 0
T26 4649 4515 0 0
T27 4143 4063 0 0
T28 11095 10974 0 0

Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 228849094 228849094 0 0
gen_no_flops.OutputDelay_A 228849094 228849094 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 228849094 228849094 0 0
T1 240848 240848 0 0
T4 43942 43942 0 0
T5 559 559 0 0
T6 2606 2606 0 0
T17 701 701 0 0
T24 1071 1071 0 0
T25 618 618 0 0
T26 2715 2715 0 0
T27 2093 2093 0 0
T28 6658 6658 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 228849094 228849094 0 0
T1 240848 240848 0 0
T4 43942 43942 0 0
T5 559 559 0 0
T6 2606 2606 0 0
T17 701 701 0 0
T24 1071 1071 0 0
T25 618 618 0 0
T26 2715 2715 0 0
T27 2093 2093 0 0
T28 6658 6658 0 0

Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 114423868 114423868 0 0
gen_no_flops.OutputDelay_A 114423868 114423868 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 114423868 114423868 0 0
T1 120423 120423 0 0
T4 21971 21971 0 0
T5 279 279 0 0
T6 1303 1303 0 0
T17 351 351 0 0
T24 535 535 0 0
T25 309 309 0 0
T26 1356 1356 0 0
T27 1046 1046 0 0
T28 3328 3328 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 114423868 114423868 0 0
T1 120423 120423 0 0
T4 21971 21971 0 0
T5 279 279 0 0
T6 1303 1303 0 0
T17 351 351 0 0
T24 535 535 0 0
T25 309 309 0 0
T26 1356 1356 0 0
T27 1046 1046 0 0
T28 3328 3328 0 0

Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 235890820 234736998 0 0
gen_no_flops.OutputDelay_A 235890820 234736998 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 235890820 234736998 0 0
T1 242165 242005 0 0
T4 55484 55464 0 0
T5 584 558 0 0
T6 2561 2466 0 0
T17 720 701 0 0
T24 1081 1028 0 0
T25 678 617 0 0
T26 2324 2257 0 0
T27 2071 2032 0 0
T28 5547 5487 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 235890820 234736998 0 0
T1 242165 242005 0 0
T4 55484 55464 0 0
T5 584 558 0 0
T6 2561 2466 0 0
T17 720 701 0 0
T24 1081 1028 0 0
T25 678 617 0 0
T26 2324 2257 0 0
T27 2071 2032 0 0
T28 5547 5487 0 0

Line Coverage for Instance : tb.dut.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 6 6

Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 180386165 177668965 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 180386165 177661656 0 2412


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177668965 0 0
T1 198394 198052 0 0
T4 111856 111701 0 0
T5 1217 1134 0 0
T6 5230 4672 0 0
T17 1472 1404 0 0
T24 2162 1987 0 0
T25 1412 1215 0 0
T26 1161 1121 0 0
T27 1035 995 0 0
T28 1271 1249 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177661656 0 2412
T1 198394 198050 0 3
T4 111856 111698 0 3
T5 1217 1131 0 3
T6 5230 4663 0 3
T17 1472 1401 0 3
T24 2162 1984 0 3
T25 1412 1212 0 3
T26 1161 1118 0 3
T27 1035 992 0 3
T28 1271 1246 0 3

Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 180386165 177668965 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 180386165 177661656 0 2412


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177668965 0 0
T1 198394 198052 0 0
T4 111856 111701 0 0
T5 1217 1134 0 0
T6 5230 4672 0 0
T17 1472 1404 0 0
T24 2162 1987 0 0
T25 1412 1215 0 0
T26 1161 1121 0 0
T27 1035 995 0 0
T28 1271 1249 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177661656 0 2412
T1 198394 198050 0 3
T4 111856 111698 0 3
T5 1217 1131 0 3
T6 5230 4663 0 3
T17 1472 1401 0 3
T24 2162 1984 0 3
T25 1412 1212 0 3
T26 1161 1118 0 3
T27 1035 992 0 3
T28 1271 1246 0 3

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 180386165 177668965 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 180386165 177661656 0 2412


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177668965 0 0
T1 198394 198052 0 0
T4 111856 111701 0 0
T5 1217 1134 0 0
T6 5230 4672 0 0
T17 1472 1404 0 0
T24 2162 1987 0 0
T25 1412 1215 0 0
T26 1161 1121 0 0
T27 1035 995 0 0
T28 1271 1249 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177661656 0 2412
T1 198394 198050 0 3
T4 111856 111698 0 3
T5 1217 1131 0 3
T6 5230 4663 0 3
T17 1472 1401 0 3
T24 2162 1984 0 3
T25 1412 1212 0 3
T26 1161 1118 0 3
T27 1035 992 0 3
T28 1271 1246 0 3

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 180386165 177668965 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 180386165 177661656 0 2412


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177668965 0 0
T1 198394 198052 0 0
T4 111856 111701 0 0
T5 1217 1134 0 0
T6 5230 4672 0 0
T17 1472 1404 0 0
T24 2162 1987 0 0
T25 1412 1215 0 0
T26 1161 1121 0 0
T27 1035 995 0 0
T28 1271 1249 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177661656 0 2412
T1 198394 198050 0 3
T4 111856 111698 0 3
T5 1217 1131 0 3
T6 5230 4663 0 3
T17 1472 1401 0 3
T24 2162 1984 0 3
T25 1412 1212 0 3
T26 1161 1118 0 3
T27 1035 992 0 3
T28 1271 1246 0 3

Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 180386165 177668965 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 180386165 177661656 0 2412


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177668965 0 0
T1 198394 198052 0 0
T4 111856 111701 0 0
T5 1217 1134 0 0
T6 5230 4672 0 0
T17 1472 1404 0 0
T24 2162 1987 0 0
T25 1412 1215 0 0
T26 1161 1121 0 0
T27 1035 995 0 0
T28 1271 1249 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177661656 0 2412
T1 198394 198050 0 3
T4 111856 111698 0 3
T5 1217 1131 0 3
T6 5230 4663 0 3
T17 1472 1401 0 3
T24 2162 1984 0 3
T25 1412 1212 0 3
T26 1161 1118 0 3
T27 1035 992 0 3
T28 1271 1246 0 3

Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 180386165 177668965 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 180386165 177661656 0 2412


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177668965 0 0
T1 198394 198052 0 0
T4 111856 111701 0 0
T5 1217 1134 0 0
T6 5230 4672 0 0
T17 1472 1404 0 0
T24 2162 1987 0 0
T25 1412 1215 0 0
T26 1161 1121 0 0
T27 1035 995 0 0
T28 1271 1249 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177661656 0 2412
T1 198394 198050 0 3
T4 111856 111698 0 3
T5 1217 1131 0 3
T6 5230 4663 0 3
T17 1472 1401 0 3
T24 2162 1984 0 3
T25 1412 1212 0 3
T26 1161 1118 0 3
T27 1035 992 0 3
T28 1271 1246 0 3

Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 180386165 177668965 0 0
gen_no_flops.OutputDelay_A 180386165 177668965 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177668965 0 0
T1 198394 198052 0 0
T4 111856 111701 0 0
T5 1217 1134 0 0
T6 5230 4672 0 0
T17 1472 1404 0 0
T24 2162 1987 0 0
T25 1412 1215 0 0
T26 1161 1121 0 0
T27 1035 995 0 0
T28 1271 1249 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177668965 0 0
T1 198394 198052 0 0
T4 111856 111701 0 0
T5 1217 1134 0 0
T6 5230 4672 0 0
T17 1472 1404 0 0
T24 2162 1987 0 0
T25 1412 1215 0 0
T26 1161 1121 0 0
T27 1035 995 0 0
T28 1271 1249 0 0

Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 180386165 177668965 0 0
gen_no_flops.OutputDelay_A 180386165 177668965 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177668965 0 0
T1 198394 198052 0 0
T4 111856 111701 0 0
T5 1217 1134 0 0
T6 5230 4672 0 0
T17 1472 1404 0 0
T24 2162 1987 0 0
T25 1412 1215 0 0
T26 1161 1121 0 0
T27 1035 995 0 0
T28 1271 1249 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177668965 0 0
T1 198394 198052 0 0
T4 111856 111701 0 0
T5 1217 1134 0 0
T6 5230 4672 0 0
T17 1472 1404 0 0
T24 2162 1987 0 0
T25 1412 1215 0 0
T26 1161 1121 0 0
T27 1035 995 0 0
T28 1271 1249 0 0

Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 180386165 177668965 0 0
gen_no_flops.OutputDelay_A 180386165 177668965 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177668965 0 0
T1 198394 198052 0 0
T4 111856 111701 0 0
T5 1217 1134 0 0
T6 5230 4672 0 0
T17 1472 1404 0 0
T24 2162 1987 0 0
T25 1412 1215 0 0
T26 1161 1121 0 0
T27 1035 995 0 0
T28 1271 1249 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177668965 0 0
T1 198394 198052 0 0
T4 111856 111701 0 0
T5 1217 1134 0 0
T6 5230 4672 0 0
T17 1472 1404 0 0
T24 2162 1987 0 0
T25 1412 1215 0 0
T26 1161 1121 0 0
T27 1035 995 0 0
T28 1271 1249 0 0

Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 180386165 177668965 0 0
gen_no_flops.OutputDelay_A 180386165 177668965 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177668965 0 0
T1 198394 198052 0 0
T4 111856 111701 0 0
T5 1217 1134 0 0
T6 5230 4672 0 0
T17 1472 1404 0 0
T24 2162 1987 0 0
T25 1412 1215 0 0
T26 1161 1121 0 0
T27 1035 995 0 0
T28 1271 1249 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 180386165 177668965 0 0
T1 198394 198052 0 0
T4 111856 111701 0 0
T5 1217 1134 0 0
T6 5230 4672 0 0
T17 1472 1404 0 0
T24 2162 1987 0 0
T25 1412 1215 0 0
T26 1161 1121 0 0
T27 1035 995 0 0
T28 1271 1249 0 0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 491126341 486334510 0 0
gen_flops.gen_stable_chks.OutputDelay_A 491126341 486327324 0 2412
gen_flops.gen_stable_chks.OutputIfUnstable_A 491126341 35496 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 486334510 0 0
T1 505702 504826 0 0
T4 115588 115419 0 0
T5 1217 1134 0 0
T6 5336 4767 0 0
T17 1502 1433 0 0
T24 2253 2069 0 0
T25 1412 1215 0 0
T26 4843 4674 0 0
T27 4316 4147 0 0
T28 11558 11346 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 486327324 0 2412
T1 505702 504824 0 3
T4 115588 115416 0 3
T5 1217 1131 0 3
T6 5336 4758 0 3
T17 1502 1430 0 3
T24 2253 2066 0 3
T25 1412 1212 0 3
T26 4843 4671 0 3
T27 4316 4144 0 3
T28 11558 11343 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 35496 0 0
T1 505702 187 0 0
T4 115588 1 0 0
T5 1217 3 0 0
T6 5336 32 0 0
T17 1502 1 0 0
T24 2253 7 0 0
T25 1412 1 0 0
T26 4843 9 0 0
T27 4316 1 0 0
T28 11558 14 0 0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 491126341 486334510 0 0
gen_no_flops.OutputDelay_A 491126341 486334510 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 486334510 0 0
T1 505702 504826 0 0
T4 115588 115419 0 0
T5 1217 1134 0 0
T6 5336 4767 0 0
T17 1502 1433 0 0
T24 2253 2069 0 0
T25 1412 1215 0 0
T26 4843 4674 0 0
T27 4316 4147 0 0
T28 11558 11346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 486334510 0 0
T1 505702 504826 0 0
T4 115588 115419 0 0
T5 1217 1134 0 0
T6 5336 4767 0 0
T17 1502 1433 0 0
T24 2253 2069 0 0
T25 1412 1215 0 0
T26 4843 4674 0 0
T27 4316 4147 0 0
T28 11558 11346 0 0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 491126341 486334510 0 0
gen_flops.gen_stable_chks.OutputDelay_A 491126341 486327324 0 2412
gen_flops.gen_stable_chks.OutputIfUnstable_A 491126341 35101 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 486334510 0 0
T1 505702 504826 0 0
T4 115588 115419 0 0
T5 1217 1134 0 0
T6 5336 4767 0 0
T17 1502 1433 0 0
T24 2253 2069 0 0
T25 1412 1215 0 0
T26 4843 4674 0 0
T27 4316 4147 0 0
T28 11558 11346 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 486327324 0 2412
T1 505702 504824 0 3
T4 115588 115416 0 3
T5 1217 1131 0 3
T6 5336 4758 0 3
T17 1502 1430 0 3
T24 2253 2066 0 3
T25 1412 1212 0 3
T26 4843 4671 0 3
T27 4316 4144 0 3
T28 11558 11343 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 35101 0 0
T1 505702 177 0 0
T4 115588 1 0 0
T5 1217 3 0 0
T6 5336 35 0 0
T17 1502 5 0 0
T24 2253 21 0 0
T25 1412 1 0 0
T26 4843 4 0 0
T27 4316 2 0 0
T28 11558 14 0 0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 491126341 486334510 0 0
gen_no_flops.OutputDelay_A 491126341 486334510 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 486334510 0 0
T1 505702 504826 0 0
T4 115588 115419 0 0
T5 1217 1134 0 0
T6 5336 4767 0 0
T17 1502 1433 0 0
T24 2253 2069 0 0
T25 1412 1215 0 0
T26 4843 4674 0 0
T27 4316 4147 0 0
T28 11558 11346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 486334510 0 0
T1 505702 504826 0 0
T4 115588 115419 0 0
T5 1217 1134 0 0
T6 5336 4767 0 0
T17 1502 1433 0 0
T24 2253 2069 0 0
T25 1412 1215 0 0
T26 4843 4674 0 0
T27 4316 4147 0 0
T28 11558 11346 0 0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 491126341 486334510 0 0
gen_flops.gen_stable_chks.OutputDelay_A 491126341 486327324 0 2412
gen_flops.gen_stable_chks.OutputIfUnstable_A 491126341 35157 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 486334510 0 0
T1 505702 504826 0 0
T4 115588 115419 0 0
T5 1217 1134 0 0
T6 5336 4767 0 0
T17 1502 1433 0 0
T24 2253 2069 0 0
T25 1412 1215 0 0
T26 4843 4674 0 0
T27 4316 4147 0 0
T28 11558 11346 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 486327324 0 2412
T1 505702 504824 0 3
T4 115588 115416 0 3
T5 1217 1131 0 3
T6 5336 4758 0 3
T17 1502 1430 0 3
T24 2253 2066 0 3
T25 1412 1212 0 3
T26 4843 4671 0 3
T27 4316 4144 0 3
T28 11558 11343 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 35157 0 0
T1 505702 191 0 0
T4 115588 1 0 0
T5 1217 3 0 0
T6 5336 35 0 0
T17 1502 5 0 0
T24 2253 9 0 0
T25 1412 3 0 0
T26 4843 9 0 0
T27 4316 2 0 0
T28 11558 14 0 0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 491126341 486334510 0 0
gen_no_flops.OutputDelay_A 491126341 486334510 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 486334510 0 0
T1 505702 504826 0 0
T4 115588 115419 0 0
T5 1217 1134 0 0
T6 5336 4767 0 0
T17 1502 1433 0 0
T24 2253 2069 0 0
T25 1412 1215 0 0
T26 4843 4674 0 0
T27 4316 4147 0 0
T28 11558 11346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 486334510 0 0
T1 505702 504826 0 0
T4 115588 115419 0 0
T5 1217 1134 0 0
T6 5336 4767 0 0
T17 1502 1433 0 0
T24 2253 2069 0 0
T25 1412 1215 0 0
T26 4843 4674 0 0
T27 4316 4147 0 0
T28 11558 11346 0 0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 491126341 486334510 0 0
gen_flops.gen_stable_chks.OutputDelay_A 491126341 486327324 0 2412
gen_flops.gen_stable_chks.OutputIfUnstable_A 491126341 34989 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 486334510 0 0
T1 505702 504826 0 0
T4 115588 115419 0 0
T5 1217 1134 0 0
T6 5336 4767 0 0
T17 1502 1433 0 0
T24 2253 2069 0 0
T25 1412 1215 0 0
T26 4843 4674 0 0
T27 4316 4147 0 0
T28 11558 11346 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 486327324 0 2412
T1 505702 504824 0 3
T4 115588 115416 0 3
T5 1217 1131 0 3
T6 5336 4758 0 3
T17 1502 1430 0 3
T24 2253 2066 0 3
T25 1412 1212 0 3
T26 4843 4671 0 3
T27 4316 4144 0 3
T28 11558 11343 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 34989 0 0
T1 505702 197 0 0
T4 115588 1 0 0
T5 1217 3 0 0
T6 5336 41 0 0
T17 1502 5 0 0
T24 2253 14 0 0
T25 1412 3 0 0
T26 4843 9 0 0
T27 4316 2 0 0
T28 11558 16 0 0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 491126341 486334510 0 0
gen_no_flops.OutputDelay_A 491126341 486334510 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 486334510 0 0
T1 505702 504826 0 0
T4 115588 115419 0 0
T5 1217 1134 0 0
T6 5336 4767 0 0
T17 1502 1433 0 0
T24 2253 2069 0 0
T25 1412 1215 0 0
T26 4843 4674 0 0
T27 4316 4147 0 0
T28 11558 11346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491126341 486334510 0 0
T1 505702 504826 0 0
T4 115588 115419 0 0
T5 1217 1134 0 0
T6 5336 4767 0 0
T17 1502 1433 0 0
T24 2253 2069 0 0
T25 1412 1215 0 0
T26 4843 4674 0 0
T27 4316 4147 0 0
T28 11558 11346 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%