Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T3

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	180386165	177511020	0	0
AllClkBypReqTrue_A	180386165	155577	0	0
IoClkBypReqFalse_A	180386165	177416250	0	2412
IoClkBypReqTrue_A	180386165	245611	0	0
LcClkBypAckFalse_A	180386165	177521923	0	0
LcClkBypAckTrue_A	180386165	144674	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180386165	177511020	0	0
T1	198394	197842	0	0
T4	111856	111700	0	0
T5	1217	1133	0	0
T6	5230	4507	0	0
T17	1472	1403	0	0
T24	2162	1857	0	0
T25	1412	1214	0	0
T26	1161	971	0	0
T27	1035	971	0	0
T28	1271	1082	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180386165	155577	0	0
T1	198394	2097	0	0
T2	90503	0	0	0
T3	0	477	0	0
T6	5230	162	0	0
T17	1472	0	0	0
T18	1756	157	0	0
T20	0	54	0	0
T21	0	4	0	0
T24	2162	129	0	0
T25	1412	0	0	0
T26	1161	149	0	0
T27	1035	23	0	0
T28	1271	166	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180386165	177416250	0	2412
T1	198394	197721	0	3
T4	111856	111698	0	3
T5	1217	1131	0	3
T6	5230	4259	0	3
T17	1472	1401	0	3
T24	2162	1984	0	3
T25	1412	1212	0	3
T26	1161	924	0	3
T27	1035	929	0	3
T28	1271	1034	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180386165	245611	0	0
T1	198394	3290	0	0
T2	90503	0	0	0
T3	0	770	0	0
T6	5230	404	0	0
T17	1472	0	0	0
T18	1756	371	0	0
T20	0	104	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	194	0	0
T27	1035	63	0	0
T28	1271	212	0	0
T103	0	114	0	0
T104	0	253	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180386165	177521923	0	0
T1	198394	197840	0	0
T4	111856	111700	0	0
T5	1217	1133	0	0
T6	5230	4430	0	0
T17	1472	1403	0	0
T24	2162	1986	0	0
T25	1412	1214	0	0
T26	1161	992	0	0
T27	1035	973	0	0
T28	1271	1130	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180386165	144674	0	0
T1	198394	2114	0	0
T2	90503	0	0	0
T3	0	452	0	0
T6	5230	239	0	0
T17	1472	0	0	0
T18	1756	203	0	0
T20	0	36	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	128	0	0
T27	1035	21	0	0
T28	1271	118	0	0
T103	0	82	0	0
T104	0	83	0	0