Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1964507120	16396	0	0
TransStop_A	1964507120	8468	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1964507120	16396	0	0
T1	2022808	79	0	0
T2	754184	0	0	0
T3	0	184	0	0
T6	21344	14	0	0
T11	0	301	0	0
T12	0	48	0	0
T17	6008	0	0	0
T18	26012	0	0	0
T24	9016	0	0	0
T25	5652	0	0	0
T26	19372	0	0	0
T27	17268	0	0	0
T28	46232	0	0	0
T35	0	1	0	0
T44	0	4	0	0
T105	0	10	0	0
T106	0	4	0	0
T107	0	4	0	0
T108	0	4	0	0
T109	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1964507120	8468	0	0
T1	2022808	28	0	0
T2	754184	0	0	0
T3	222609	86	0	0
T6	16008	3	0	0
T11	0	160	0	0
T12	0	38	0	0
T17	6008	0	0	0
T18	26012	0	0	0
T19	20113	0	0	0
T20	2121	0	0	0
T21	3797	0	0	0
T22	1894	0	0	0
T23	2382	0	0	0
T24	6762	0	0	0
T25	4239	0	0	0
T26	14529	0	0	0
T27	12951	0	0	0
T28	34674	0	0	0
T44	0	4	0	0
T105	0	4	0	0
T106	0	4	0	0
T107	0	4	0	0
T108	0	4	0	0
T109	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	491126780	4090	0	0
TransStop_A	491126780	2096	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491126780	4090	0	0
T1	505702	22	0	0
T2	188546	0	0	0
T3	0	52	0	0
T6	5336	2	0	0
T11	0	71	0	0
T12	0	15	0	0
T17	1502	0	0	0
T18	6503	0	0	0
T24	2254	0	0	0
T25	1413	0	0	0
T26	4843	0	0	0
T27	4317	0	0	0
T28	11558	0	0	0
T44	0	1	0	0
T105	0	3	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491126780	2096	0	0
T1	505702	7	0	0
T2	188546	0	0	0
T3	222609	25	0	0
T11	0	36	0	0
T12	0	8	0	0
T17	1502	0	0	0
T18	6503	0	0	0
T19	20113	0	0	0
T20	2121	0	0	0
T21	3797	0	0	0
T22	1894	0	0	0
T23	2382	0	0	0
T44	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	491126780	4116	0	0
TransStop_A	491126780	2119	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491126780	4116	0	0
T1	505702	17	0	0
T2	188546	0	0	0
T3	0	37	0	0
T6	5336	3	0	0
T11	0	80	0	0
T17	1502	0	0	0
T18	6503	0	0	0
T24	2254	0	0	0
T25	1413	0	0	0
T26	4843	0	0	0
T27	4317	0	0	0
T28	11558	0	0	0
T35	0	1	0	0
T44	0	1	0	0
T105	0	4	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491126780	2119	0	0
T1	505702	6	0	0
T2	188546	0	0	0
T3	0	16	0	0
T6	5336	1	0	0
T11	0	42	0	0
T12	0	9	0	0
T17	1502	0	0	0
T18	6503	0	0	0
T24	2254	0	0	0
T25	1413	0	0	0
T26	4843	0	0	0
T27	4317	0	0	0
T28	11558	0	0	0
T44	0	1	0	0
T105	0	2	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	491126780	4081	0	0
TransStop_A	491126780	2095	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491126780	4081	0	0
T1	505702	19	0	0
T2	188546	0	0	0
T3	0	59	0	0
T6	5336	5	0	0
T11	0	73	0	0
T12	0	18	0	0
T17	1502	0	0	0
T18	6503	0	0	0
T24	2254	0	0	0
T25	1413	0	0	0
T26	4843	0	0	0
T27	4317	0	0	0
T28	11558	0	0	0
T44	0	1	0	0
T105	0	3	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491126780	2095	0	0
T1	505702	7	0	0
T2	188546	0	0	0
T3	0	27	0	0
T6	5336	1	0	0
T11	0	39	0	0
T12	0	11	0	0
T17	1502	0	0	0
T18	6503	0	0	0
T24	2254	0	0	0
T25	1413	0	0	0
T26	4843	0	0	0
T27	4317	0	0	0
T28	11558	0	0	0
T44	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	491126780	4109	0	0
TransStop_A	491126780	2158	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491126780	4109	0	0
T1	505702	21	0	0
T2	188546	0	0	0
T3	0	36	0	0
T6	5336	4	0	0
T11	0	77	0	0
T12	0	15	0	0
T17	1502	0	0	0
T18	6503	0	0	0
T24	2254	0	0	0
T25	1413	0	0	0
T26	4843	0	0	0
T27	4317	0	0	0
T28	11558	0	0	0
T44	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491126780	2158	0	0
T1	505702	8	0	0
T2	188546	0	0	0
T3	0	18	0	0
T6	5336	1	0	0
T11	0	43	0	0
T12	0	10	0	0
T17	1502	0	0	0
T18	6503	0	0	0
T24	2254	0	0	0
T25	1413	0	0	0
T26	4843	0	0	0
T27	4317	0	0	0
T28	11558	0	0	0
T44	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0