Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	181244005	5720596	0	0
clk_enables_rd_A	181244005	78582	0	0
clk_hints_rd_A	181244005	70834	0	0
extclk_ctrl_rd_A	181244005	88961	0	0
extclk_ctrl_regwen_rd_A	181244005	68217	0	0
jitter_enable_rd_A	181244005	99067	0	0
jitter_regwen_rd_A	181244005	77005	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	5720596	0	0
T1	198394	61897	0	0
T2	90503	0	0	0
T3	222862	102703	0	0
T11	0	108430	0	0
T16	0	179112	0	0
T17	1472	0	0	0
T18	1756	0	0	0
T19	19307	0	0	0
T20	1018	0	0	0
T21	986	0	0	0
T22	1799	0	0	0
T23	1143	0	0	0
T36	0	132674	0	0
T38	0	125635	0	0
T69	0	69639	0	0
T70	0	160127	0	0
T71	0	109883	0	0
T72	0	85419	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	78582	0	0
T1	198394	1278	0	0
T2	90503	0	0	0
T3	222862	0	0	0
T11	0	4262	0	0
T17	1472	0	0	0
T18	1756	0	0	0
T19	19307	0	0	0
T20	1018	0	0	0
T21	986	0	0	0
T22	1799	0	0	0
T23	1143	0	0	0
T72	0	3497	0	0
T109	0	10	0	0
T126	0	6	0	0
T127	0	6009	0	0
T128	0	4645	0	0
T129	0	8	0	0
T130	0	6	0	0
T131	0	4196	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	70834	0	0
T1	198394	1247	0	0
T2	90503	0	0	0
T3	222862	0	0	0
T11	0	3621	0	0
T17	1472	0	0	0
T18	1756	0	0	0
T19	19307	0	0	0
T20	1018	0	0	0
T21	986	0	0	0
T22	1799	0	0	0
T23	1143	0	0	0
T72	0	2898	0	0
T106	0	2	0	0
T109	0	1	0	0
T126	0	6	0	0
T127	0	5723	0	0
T128	0	3898	0	0
T129	0	16	0	0
T132	0	4	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	88961	0	0
T1	198394	1469	0	0
T2	90503	0	0	0
T3	222862	0	0	0
T11	0	4810	0	0
T17	1472	0	0	0
T18	1756	43	0	0
T19	19307	0	0	0
T20	1018	10	0	0
T21	986	0	0	0
T22	1799	0	0	0
T23	1143	0	0	0
T73	0	43	0	0
T133	0	42	0	0
T134	0	66	0	0
T135	0	69	0	0
T136	0	43	0	0
T137	0	71	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	68217	0	0
T1	198394	1155	0	0
T2	90503	0	0	0
T3	222862	0	0	0
T11	0	3627	0	0
T17	1472	0	0	0
T18	1756	0	0	0
T19	19307	0	0	0
T20	1018	0	0	0
T21	986	0	0	0
T22	1799	0	0	0
T23	1143	0	0	0
T72	0	2906	0	0
T102	0	18	0	0
T127	0	5771	0	0
T128	0	4036	0	0
T131	0	3746	0	0
T138	0	3	0	0
T139	0	71	0	0
T140	0	42	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	99067	0	0
T1	198394	1748	0	0
T2	90503	0	0	0
T3	222862	0	0	0
T11	0	5983	0	0
T17	1472	0	0	0
T18	1756	0	0	0
T19	19307	0	0	0
T20	1018	0	0	0
T21	986	0	0	0
T22	1799	0	0	0
T23	1143	0	0	0
T72	0	4243	0	0
T106	0	108	0	0
T109	0	60	0	0
T126	0	117	0	0
T127	0	7434	0	0
T128	0	7454	0	0
T129	0	490	0	0
T132	0	119	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	77005	0	0
T1	198394	1292	0	0
T2	90503	0	0	0
T3	222862	0	0	0
T11	0	4078	0	0
T17	1472	0	0	0
T18	1756	0	0	0
T19	19307	0	0	0
T20	1018	0	0	0
T21	986	0	0	0
T22	1799	0	0	0
T23	1143	0	0	0
T39	0	1435	0	0
T72	0	3427	0	0
T127	0	6473	0	0
T128	0	4570	0	0
T131	0	4247	0	0
T141	0	4719	0	0
T142	0	1656	0	0
T143	0	829	0	0