Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	51074	0	0
CgEnOn_A	2147483647	41603	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	51074	0	0
T1	1348399	147	0	0
T3	2691958	57	0	0
T4	153836	3	0	0
T5	2007	3	0	0
T6	14367	11	0	0
T7	170165	0	0	0
T16	0	5	0	0
T17	3995	3	0	0
T18	6502	0	0	0
T24	6021	3	0	0
T25	3695	6	0	0
T26	13563	3	0	0
T27	11598	3	0	0
T28	32639	3	0	0
T32	29613	0	0	0
T41	2935	12	0	0
T42	5052	14	0	0
T43	0	10	0	0
T103	3900	0	0	0
T104	17011	0	0	0
T105	7133	3	0	0
T128	0	5	0	0
T133	16910	0	0	0
T144	0	20	0	0
T145	0	10	0	0
T146	0	10	0	0
T147	0	30	0	0
T153	7048	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41603	0	0
T1	361271	107	0	0
T2	135730	0	0	0
T3	2490518	127	0	0
T7	68603	0	0	0
T11	0	240	0	0
T16	0	4	0	0
T17	1052	0	0	0
T18	5238	0	0	0
T19	14431	0	0	0
T20	1538	0	0	0
T25	927	3	0	0
T26	4071	0	0	0
T27	3139	0	0	0
T28	9986	0	0	0
T32	29613	0	0	0
T35	0	83	0	0
T41	2935	16	0	0
T42	5052	16	0	0
T43	0	10	0	0
T44	0	3	0	0
T103	2162	0	0	0
T104	9778	0	0	0
T105	3941	0	0	0
T106	0	3	0	0
T107	0	1	0	0
T108	0	2	0	0
T128	0	4	0	0
T133	9936	0	0	0
T144	0	20	0	0
T145	0	10	0	0
T146	0	10	0	0
T147	0	30	0	0
T148	0	4	0	0
T149	0	1	0	0
T150	0	3	0	0
T151	7996	0	0	0
T153	3896	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T3
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	228849094	146	0	0
CgEnOn_A	228849094	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228849094	146	0	0
T3	996212	1	0	0
T7	27440	0	0	0
T16	0	1	0	0
T32	6554	0	0	0
T41	629	2	0	0
T42	1108	2	0	0
T43	0	2	0	0
T103	866	0	0	0
T104	3913	0	0	0
T105	1577	0	0	0
T128	0	1	0	0
T133	3975	0	0	0
T144	0	4	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	6	0	0
T153	1559	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228849094	146	0	0
T3	996212	1	0	0
T7	27440	0	0	0
T16	0	1	0	0
T32	6554	0	0	0
T41	629	2	0	0
T42	1108	2	0	0
T43	0	2	0	0
T103	866	0	0	0
T104	3913	0	0	0
T105	1577	0	0	0
T128	0	1	0	0
T133	3975	0	0	0
T144	0	4	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	6	0	0
T153	1559	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T3
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	114423868	146	0	0
CgEnOn_A	114423868	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114423868	146	0	0
T3	498102	1	0	0
T7	13721	0	0	0
T16	0	1	0	0
T32	3277	0	0	0
T41	314	2	0	0
T42	554	2	0	0
T43	0	2	0	0
T103	432	0	0	0
T104	1955	0	0	0
T105	788	0	0	0
T128	0	1	0	0
T133	1987	0	0	0
T144	0	4	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	6	0	0
T153	779	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114423868	146	0	0
T3	498102	1	0	0
T7	13721	0	0	0
T16	0	1	0	0
T32	3277	0	0	0
T41	314	2	0	0
T42	554	2	0	0
T43	0	2	0	0
T103	432	0	0	0
T104	1955	0	0	0
T105	788	0	0	0
T128	0	1	0	0
T133	1987	0	0	0
T144	0	4	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	6	0	0
T153	779	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T3
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	459400022	146	0	0
CgEnOn_A	459400022	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459400022	146	0	0
T3	201440	1	0	0
T7	101562	0	0	0
T16	0	1	0	0
T32	13228	0	0	0
T41	1364	2	0	0
T42	2282	2	0	0
T43	0	2	0	0
T103	1738	0	0	0
T104	7233	0	0	0
T105	3192	0	0	0
T128	0	1	0	0
T133	6974	0	0	0
T144	0	4	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	6	0	0
T153	3152	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459400022	142	0	0
T29	58171	0	0	0
T32	13228	0	0	0
T33	91953	0	0	0
T34	153955	0	0	0
T35	813413	0	0	0
T41	1364	2	0	0
T42	2282	2	0	0
T43	0	2	0	0
T44	2672	0	0	0
T73	2493	0	0	0
T144	0	4	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	6	0	0
T148	0	4	0	0
T149	0	1	0	0
T150	0	3	0	0
T151	7996	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T3
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	491126341	152	0	0
CgEnOn_A	491126341	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491126341	152	0	0
T29	60597	0	0	0
T32	7780	0	0	0
T33	113787	0	0	0
T34	184375	0	0	0
T35	102733	0	0	0
T41	1370	2	0	0
T42	2320	4	0	0
T43	0	2	0	0
T44	2784	0	0	0
T73	2596	0	0	0
T144	0	7	0	0
T145	0	4	0	0
T146	0	2	0	0
T147	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	5	0	0
T151	8329	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491126341	151	0	0
T29	60597	0	0	0
T32	7780	0	0	0
T33	113787	0	0	0
T34	184375	0	0	0
T35	102733	0	0	0
T41	1370	2	0	0
T42	2320	4	0	0
T43	0	2	0	0
T44	2784	0	0	0
T73	2596	0	0	0
T144	0	7	0	0
T145	0	4	0	0
T146	0	2	0	0
T147	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	5	0	0
T151	8329	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T3
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	114423868	146	0	0
CgEnOn_A	114423868	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114423868	146	0	0
T3	498102	1	0	0
T7	13721	0	0	0
T16	0	1	0	0
T32	3277	0	0	0
T41	314	2	0	0
T42	554	2	0	0
T43	0	2	0	0
T103	432	0	0	0
T104	1955	0	0	0
T105	788	0	0	0
T128	0	1	0	0
T133	1987	0	0	0
T144	0	4	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	6	0	0
T153	779	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114423868	146	0	0
T3	498102	1	0	0
T7	13721	0	0	0
T16	0	1	0	0
T32	3277	0	0	0
T41	314	2	0	0
T42	554	2	0	0
T43	0	2	0	0
T103	432	0	0	0
T104	1955	0	0	0
T105	788	0	0	0
T128	0	1	0	0
T133	1987	0	0	0
T144	0	4	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	6	0	0
T153	779	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T3
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	491126341	152	0	0
CgEnOn_A	491126341	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491126341	152	0	0
T29	60597	0	0	0
T32	7780	0	0	0
T33	113787	0	0	0
T34	184375	0	0	0
T35	102733	0	0	0
T41	1370	2	0	0
T42	2320	4	0	0
T43	0	2	0	0
T44	2784	0	0	0
T73	2596	0	0	0
T144	0	7	0	0
T145	0	4	0	0
T146	0	2	0	0
T147	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	5	0	0
T151	8329	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491126341	151	0	0
T29	60597	0	0	0
T32	7780	0	0	0
T33	113787	0	0	0
T34	184375	0	0	0
T35	102733	0	0	0
T41	1370	2	0	0
T42	2320	4	0	0
T43	0	2	0	0
T44	2784	0	0	0
T73	2596	0	0	0
T144	0	7	0	0
T145	0	4	0	0
T146	0	2	0	0
T147	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	5	0	0
T151	8329	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T3
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	114423868	146	0	0
CgEnOn_A	114423868	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114423868	146	0	0
T3	498102	1	0	0
T7	13721	0	0	0
T16	0	1	0	0
T32	3277	0	0	0
T41	314	2	0	0
T42	554	2	0	0
T43	0	2	0	0
T103	432	0	0	0
T104	1955	0	0	0
T105	788	0	0	0
T128	0	1	0	0
T133	1987	0	0	0
T144	0	4	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	6	0	0
T153	779	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114423868	146	0	0
T3	498102	1	0	0
T7	13721	0	0	0
T16	0	1	0	0
T32	3277	0	0	0
T41	314	2	0	0
T42	554	2	0	0
T43	0	2	0	0
T103	432	0	0	0
T104	1955	0	0	0
T105	788	0	0	0
T128	0	1	0	0
T133	1987	0	0	0
T144	0	4	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	6	0	0
T153	779	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	228849094	8271	0	0
CgEnOn_A	228849094	5908	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228849094	8271	0	0
T1	240848	41	0	0
T4	43942	1	0	0
T5	559	1	0	0
T6	2606	3	0	0
T17	701	1	0	0
T24	1071	1	0	0
T25	618	2	0	0
T26	2715	1	0	0
T27	2093	1	0	0
T28	6658	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228849094	5908	0	0
T1	240848	35	0	0
T2	90487	0	0	0
T3	0	41	0	0
T11	0	83	0	0
T17	701	0	0	0
T18	3492	0	0	0
T19	9621	0	0	0
T20	1025	0	0	0
T25	618	1	0	0
T26	2715	0	0	0
T27	2093	0	0	0
T28	6658	0	0	0
T35	0	28	0	0
T41	0	2	0	0
T42	0	2	0	0
T44	0	1	0	0
T106	0	1	0	0
T108	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	114423868	8214	0	0
CgEnOn_A	114423868	5851	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114423868	8214	0	0
T1	120423	42	0	0
T4	21971	1	0	0
T5	279	1	0	0
T6	1303	3	0	0
T17	351	1	0	0
T24	535	1	0	0
T25	309	2	0	0
T26	1356	1	0	0
T27	1046	1	0	0
T28	3328	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114423868	5851	0	0
T1	120423	36	0	0
T2	45243	0	0	0
T3	0	37	0	0
T11	0	78	0	0
T17	351	0	0	0
T18	1746	0	0	0
T19	4810	0	0	0
T20	513	0	0	0
T25	309	1	0	0
T26	1356	0	0	0
T27	1046	0	0	0
T28	3328	0	0	0
T35	0	30	0	0
T41	0	2	0	0
T42	0	2	0	0
T44	0	1	0	0
T106	0	1	0	0
T108	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	459400022	8283	0	0
CgEnOn_A	459400022	5916	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459400022	8283	0	0
T1	481426	42	0	0
T4	87923	1	0	0
T5	1169	1	0	0
T6	5122	3	0	0
T17	1441	1	0	0
T24	2162	1	0	0
T25	1356	2	0	0
T26	4649	1	0	0
T27	4143	1	0	0
T28	11095	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459400022	5916	0	0
T1	481426	36	0	0
T2	180998	0	0	0
T3	0	45	0	0
T11	0	79	0	0
T17	1441	0	0	0
T18	6242	0	0	0
T19	19307	0	0	0
T20	2036	0	0	0
T25	1356	1	0	0
T26	4649	0	0	0
T27	4143	0	0	0
T28	11095	0	0	0
T35	0	25	0	0
T41	0	2	0	0
T42	0	2	0	0
T44	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	235890820	8268	0	0
CgEnOn_A	235890820	5900	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235890820	8268	0	0
T1	242165	40	0	0
T4	55484	1	0	0
T5	584	1	0	0
T6	2561	3	0	0
T17	720	1	0	0
T24	1081	1	0	0
T25	678	2	0	0
T26	2324	1	0	0
T27	2071	1	0	0
T28	5547	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235890820	5900	0	0
T1	242165	34	0	0
T2	90503	0	0	0
T3	0	40	0	0
T11	0	88	0	0
T17	720	0	0	0
T18	3121	0	0	0
T19	9654	0	0	0
T20	1018	0	0	0
T25	678	1	0	0
T26	2324	0	0	0
T27	2071	0	0	0
T28	5547	0	0	0
T35	0	27	0	0
T41	0	3	0	0
T42	0	3	0	0
T44	0	1	0	0
T106	0	1	0	0
T108	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T3
1	0	Covered	T6,T1,T3
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	491126341	4242	0	0
CgEnOn_A	491126341	4241	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491126341	4242	0	0
T1	505702	22	0	0
T2	188545	0	0	0
T3	0	52	0	0
T6	5336	2	0	0
T11	0	71	0	0
T17	1502	0	0	0
T18	6502	0	0	0
T24	2253	0	0	0
T25	1412	0	0	0
T26	4843	0	0	0
T27	4316	0	0	0
T28	11558	0	0	0
T41	0	2	0	0
T42	0	4	0	0
T44	0	1	0	0
T105	0	3	0	0
T106	0	1	0	0
T107	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491126341	4241	0	0
T1	505702	22	0	0
T2	188545	0	0	0
T3	0	52	0	0
T6	5336	2	0	0
T11	0	71	0	0
T17	1502	0	0	0
T18	6502	0	0	0
T24	2253	0	0	0
T25	1412	0	0	0
T26	4843	0	0	0
T27	4316	0	0	0
T28	11558	0	0	0
T41	0	2	0	0
T42	0	4	0	0
T44	0	1	0	0
T105	0	3	0	0
T106	0	1	0	0
T107	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T3
1	0	Covered	T6,T1,T3
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	491126341	4268	0	0
CgEnOn_A	491126341	4267	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491126341	4268	0	0
T1	505702	17	0	0
T2	188545	0	0	0
T3	0	37	0	0
T6	5336	3	0	0
T17	1502	0	0	0
T18	6502	0	0	0
T24	2253	0	0	0
T25	1412	0	0	0
T26	4843	0	0	0
T27	4316	0	0	0
T28	11558	0	0	0
T35	0	1	0	0
T41	0	2	0	0
T42	0	4	0	0
T44	0	1	0	0
T105	0	4	0	0
T106	0	1	0	0
T107	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491126341	4267	0	0
T1	505702	17	0	0
T2	188545	0	0	0
T3	0	37	0	0
T6	5336	3	0	0
T17	1502	0	0	0
T18	6502	0	0	0
T24	2253	0	0	0
T25	1412	0	0	0
T26	4843	0	0	0
T27	4316	0	0	0
T28	11558	0	0	0
T35	0	1	0	0
T41	0	2	0	0
T42	0	4	0	0
T44	0	1	0	0
T105	0	4	0	0
T106	0	1	0	0
T107	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T3
1	0	Covered	T6,T1,T3
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	491126341	4233	0	0
CgEnOn_A	491126341	4232	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491126341	4233	0	0
T1	505702	19	0	0
T2	188545	0	0	0
T3	0	59	0	0
T6	5336	5	0	0
T11	0	73	0	0
T17	1502	0	0	0
T18	6502	0	0	0
T24	2253	0	0	0
T25	1412	0	0	0
T26	4843	0	0	0
T27	4316	0	0	0
T28	11558	0	0	0
T41	0	2	0	0
T42	0	4	0	0
T44	0	1	0	0
T105	0	3	0	0
T106	0	1	0	0
T107	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491126341	4232	0	0
T1	505702	19	0	0
T2	188545	0	0	0
T3	0	59	0	0
T6	5336	5	0	0
T11	0	73	0	0
T17	1502	0	0	0
T18	6502	0	0	0
T24	2253	0	0	0
T25	1412	0	0	0
T26	4843	0	0	0
T27	4316	0	0	0
T28	11558	0	0	0
T41	0	2	0	0
T42	0	4	0	0
T44	0	1	0	0
T105	0	3	0	0
T106	0	1	0	0
T107	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T3
1	0	Covered	T6,T1,T3
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	491126341	4261	0	0
CgEnOn_A	491126341	4260	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491126341	4261	0	0
T1	505702	21	0	0
T2	188545	0	0	0
T3	0	36	0	0
T6	5336	4	0	0
T11	0	77	0	0
T17	1502	0	0	0
T18	6502	0	0	0
T24	2253	0	0	0
T25	1412	0	0	0
T26	4843	0	0	0
T27	4316	0	0	0
T28	11558	0	0	0
T41	0	2	0	0
T42	0	4	0	0
T44	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491126341	4260	0	0
T1	505702	21	0	0
T2	188545	0	0	0
T3	0	36	0	0
T6	5336	4	0	0
T11	0	77	0	0
T17	1502	0	0	0
T18	6502	0	0	0
T24	2253	0	0	0
T25	1412	0	0	0
T26	4843	0	0	0
T27	4316	0	0	0
T28	11558	0	0	0
T41	0	2	0	0
T42	0	4	0	0
T44	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0