Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T1,T3
0	1	Covered	T1,T3,T35
1	0	Covered	T5,T6,T24

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T1,T3
1	0	Covered	T41,T42,T43
1	1	Covered	T5,T6,T24

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1038565473	15236	0	0
GateOpen_A	1038565473	15236	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1038565473	15236	0	0
T1	1084862	70	0	0
T2	407232	0	0	0
T3	0	102	0	0
T11	0	199	0	0
T17	3216	0	0	0
T18	14603	0	0	0
T19	43394	0	0	0
T20	4593	0	0	0
T25	2962	4	0	0
T26	11046	0	0	0
T27	9356	0	0	0
T28	26632	0	0	0
T35	0	77	0	0
T41	0	9	0	0
T42	0	9	0	0
T44	0	4	0	0
T106	0	4	0	0
T107	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1038565473	15236	0	0
T1	1084862	70	0	0
T2	407232	0	0	0
T3	0	102	0	0
T11	0	199	0	0
T17	3216	0	0	0
T18	14603	0	0	0
T19	43394	0	0	0
T20	4593	0	0	0
T25	2962	4	0	0
T26	11046	0	0	0
T27	9356	0	0	0
T28	26632	0	0	0
T35	0	77	0	0
T41	0	9	0	0
T42	0	9	0	0
T44	0	4	0	0
T106	0	4	0	0
T107	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T1,T3
0	1	Covered	T1,T3,T35
1	0	Covered	T5,T6,T24

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T1,T3
1	0	Covered	T41,T42,T43
1	1	Covered	T5,T6,T24

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	114424259	3756	0	0
GateOpen_A	114424259	3756	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114424259	3756	0	0
T1	120423	17	0	0
T2	45244	0	0	0
T3	0	24	0	0
T11	0	48	0	0
T17	351	0	0	0
T18	1746	0	0	0
T19	4811	0	0	0
T20	513	0	0	0
T25	309	1	0	0
T26	1357	0	0	0
T27	1047	0	0	0
T28	3329	0	0	0
T35	0	20	0	0
T41	0	2	0	0
T42	0	2	0	0
T44	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114424259	3756	0	0
T1	120423	17	0	0
T2	45244	0	0	0
T3	0	24	0	0
T11	0	48	0	0
T17	351	0	0	0
T18	1746	0	0	0
T19	4811	0	0	0
T20	513	0	0	0
T25	309	1	0	0
T26	1357	0	0	0
T27	1047	0	0	0
T28	3329	0	0	0
T35	0	20	0	0
T41	0	2	0	0
T42	0	2	0	0
T44	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T1,T3
0	1	Covered	T1,T3,T35
1	0	Covered	T5,T6,T24

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T1,T3
1	0	Covered	T41,T42,T43
1	1	Covered	T5,T6,T24

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	228849509	3801	0	0
GateOpen_A	228849509	3801	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228849509	3801	0	0
T1	240848	18	0	0
T2	90487	0	0	0
T3	0	26	0	0
T11	0	49	0	0
T17	702	0	0	0
T18	3493	0	0	0
T19	9621	0	0	0
T20	1026	0	0	0
T25	618	1	0	0
T26	2715	0	0	0
T27	2093	0	0	0
T28	6659	0	0	0
T35	0	20	0	0
T41	0	2	0	0
T42	0	2	0	0
T44	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228849509	3801	0	0
T1	240848	18	0	0
T2	90487	0	0	0
T3	0	26	0	0
T11	0	49	0	0
T17	702	0	0	0
T18	3493	0	0	0
T19	9621	0	0	0
T20	1026	0	0	0
T25	618	1	0	0
T26	2715	0	0	0
T27	2093	0	0	0
T28	6659	0	0	0
T35	0	20	0	0
T41	0	2	0	0
T42	0	2	0	0
T44	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T1,T3
0	1	Covered	T1,T3,T35
1	0	Covered	T5,T6,T24

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T1,T3
1	0	Covered	T41,T42,T43
1	1	Covered	T5,T6,T24

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	459400469	3856	0	0
GateOpen_A	459400469	3856	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459400469	3856	0	0
T1	481426	18	0	0
T2	180998	0	0	0
T3	0	26	0	0
T11	0	48	0	0
T17	1442	0	0	0
T18	6243	0	0	0
T19	19308	0	0	0
T20	2036	0	0	0
T25	1356	1	0	0
T26	4649	0	0	0
T27	4144	0	0	0
T28	11096	0	0	0
T35	0	19	0	0
T41	0	2	0	0
T42	0	2	0	0
T44	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459400469	3856	0	0
T1	481426	18	0	0
T2	180998	0	0	0
T3	0	26	0	0
T11	0	48	0	0
T17	1442	0	0	0
T18	6243	0	0	0
T19	19308	0	0	0
T20	2036	0	0	0
T25	1356	1	0	0
T26	4649	0	0	0
T27	4144	0	0	0
T28	11096	0	0	0
T35	0	19	0	0
T41	0	2	0	0
T42	0	2	0	0
T44	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T1,T3
0	1	Covered	T1,T3,T35
1	0	Covered	T5,T6,T24

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T1,T3
1	0	Covered	T41,T42,T43
1	1	Covered	T5,T6,T24

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	235891236	3823	0	0
GateOpen_A	235891236	3823	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235891236	3823	0	0
T1	242165	17	0	0
T2	90503	0	0	0
T3	0	26	0	0
T11	0	54	0	0
T17	721	0	0	0
T18	3121	0	0	0
T19	9654	0	0	0
T20	1018	0	0	0
T25	679	1	0	0
T26	2325	0	0	0
T27	2072	0	0	0
T28	5548	0	0	0
T35	0	18	0	0
T41	0	3	0	0
T42	0	3	0	0
T44	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235891236	3823	0	0
T1	242165	17	0	0
T2	90503	0	0	0
T3	0	26	0	0
T11	0	54	0	0
T17	721	0	0	0
T18	3121	0	0	0
T19	9654	0	0	0
T20	1018	0	0	0
T25	679	1	0	0
T26	2325	0	0	0
T27	2072	0	0	0
T28	5548	0	0	0
T35	0	18	0	0
T41	0	3	0	0
T42	0	3	0	0
T44	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0