Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	588596	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3324401

1

T1

679

T6

7

T15

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	963327	1			T5	50		T1	322		T15	18
values[0x0]	1358045	1			T1	608		T6	12		T15	19
values[0x1]	1591625	1			T1	586		T6	13		T15	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	328360	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3584637

1

T5

20

T1

892

T6

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14773	1			T5	2		T1	4		T4	6
valid_sources[0x01]	14911	1			T1	3		T4	5		T2	7
valid_sources[0x02]	16472	1			T1	8		T4	5		T2	5
valid_sources[0x03]	16834	1			T1	12		T4	8		T2	5
valid_sources[0x04]	14611	1			T1	6		T4	6		T2	3
valid_sources[0x05]	15749	1			T1	7		T4	5		T2	6
valid_sources[0x06]	14937	1			T1	2		T4	5		T2	5
valid_sources[0x07]	14411	1			T1	5		T4	3		T2	12
valid_sources[0x08]	16278	1			T1	3		T4	2		T2	4
valid_sources[0x09]	13485	1			T1	8		T4	4		T2	3
valid_sources[0x0a]	15011	1			T1	3		T4	6		T2	3
valid_sources[0x0b]	14952	1			T1	6		T4	2		T2	8
valid_sources[0x0c]	14309	1			T1	7		T4	1		T2	12
valid_sources[0x0d]	14731	1			T1	6		T4	4		T2	7
valid_sources[0x0e]	15618	1			T1	5		T4	6		T2	6
valid_sources[0x0f]	15297	1			T1	6		T2	4		T78	1
valid_sources[0x10]	14130	1			T1	5		T4	6		T2	6
valid_sources[0x11]	14645	1			T1	1		T4	4		T2	6
valid_sources[0x12]	15090	1			T1	7		T4	6		T2	6
valid_sources[0x13]	15717	1			T1	1		T4	2		T2	6
valid_sources[0x14]	15799	1			T1	5		T4	4		T2	4
valid_sources[0x15]	15027	1			T1	5		T4	7		T2	3
valid_sources[0x16]	15399	1			T1	9		T4	1		T2	2
valid_sources[0x17]	17209	1			T1	8		T4	2		T2	6
valid_sources[0x18]	15759	1			T1	3		T4	3		T2	4
valid_sources[0x19]	14875	1			T1	5		T4	4		T2	7
valid_sources[0x1a]	15424	1			T1	8		T4	2		T2	5
valid_sources[0x1b]	15192	1			T1	9		T4	7		T2	5
valid_sources[0x1c]	15608	1			T1	9		T4	3		T2	2
valid_sources[0x1d]	16774	1			T1	4		T4	3		T24	2
valid_sources[0x1e]	14468	1			T1	3		T4	2		T2	3
valid_sources[0x1f]	15897	1			T1	4		T4	3		T2	8
valid_sources[0x20]	14869	1			T1	3		T4	4		T2	4
valid_sources[0x21]	15521	1			T1	5		T2	6		T28	2
valid_sources[0x22]	15131	1			T1	6		T4	2		T2	4
valid_sources[0x23]	14099	1			T1	3		T4	7		T2	5
valid_sources[0x24]	15844	1			T5	1		T1	7		T4	5
valid_sources[0x25]	14880	1			T1	4		T4	2		T2	7
valid_sources[0x26]	16037	1			T1	8		T4	3		T2	9
valid_sources[0x27]	14257	1			T1	12		T4	4		T2	5
valid_sources[0x28]	16031	1			T5	1		T1	5		T4	3
valid_sources[0x29]	16394	1			T1	6		T4	2		T2	5
valid_sources[0x2a]	14680	1			T1	4		T4	7		T2	3
valid_sources[0x2b]	14893	1			T1	5		T4	7		T2	2
valid_sources[0x2c]	15841	1			T1	2		T4	4		T2	4
valid_sources[0x2d]	15876	1			T1	4		T4	2		T2	6
valid_sources[0x2e]	14232	1			T1	4		T4	2		T2	8
valid_sources[0x2f]	15306	1			T1	7		T4	5		T2	3
valid_sources[0x30]	14347	1			T1	5		T4	3		T2	11
valid_sources[0x31]	15709	1			T1	9		T4	5		T2	4
valid_sources[0x32]	16113	1			T5	2		T1	4		T4	2
valid_sources[0x33]	15971	1			T1	4		T4	1		T2	2
valid_sources[0x34]	14687	1			T1	8		T4	3		T2	6
valid_sources[0x35]	15118	1			T1	6		T4	2		T2	3
valid_sources[0x36]	15910	1			T1	8		T4	6		T2	14
valid_sources[0x37]	15349	1			T1	1		T15	1		T4	5
valid_sources[0x38]	15538	1			T1	5		T4	2		T2	4
valid_sources[0x39]	15042	1			T1	3		T4	2		T2	7
valid_sources[0x3a]	14115	1			T1	8		T4	5		T2	2
valid_sources[0x3b]	15681	1			T1	4		T4	4		T2	3
valid_sources[0x3c]	14526	1			T1	10		T4	1		T2	4
valid_sources[0x3d]	16781	1			T1	9		T4	3		T2	6
valid_sources[0x3e]	14914	1			T1	5		T4	2		T2	2
valid_sources[0x3f]	15565	1			T1	7		T6	5		T4	4
valid_sources[0x40]	15142	1			T1	5		T4	4		T2	5
valid_sources[0x41]	16172	1			T1	4		T4	3		T2	8
valid_sources[0x42]	16516	1			T1	4		T4	5		T2	5
valid_sources[0x43]	15197	1			T1	4		T4	1		T2	2
valid_sources[0x44]	15382	1			T1	4		T4	2		T2	6
valid_sources[0x45]	14840	1			T1	9		T4	2		T2	1
valid_sources[0x46]	16684	1			T1	5		T2	5		T78	1
valid_sources[0x47]	15030	1			T1	5		T4	2		T2	5
valid_sources[0x48]	14539	1			T1	11		T4	1		T2	4
valid_sources[0x49]	13578	1			T1	8		T4	2		T2	3
valid_sources[0x4a]	14847	1			T5	1		T1	5		T4	2
valid_sources[0x4b]	14500	1			T1	5		T4	2		T2	12
valid_sources[0x4c]	15913	1			T5	3		T1	5		T4	1
valid_sources[0x4d]	15666	1			T5	3		T1	4		T4	3
valid_sources[0x4e]	15875	1			T1	1		T4	1		T2	3
valid_sources[0x4f]	13742	1			T5	3		T1	8		T4	1
valid_sources[0x50]	15153	1			T1	5		T4	1		T2	6
valid_sources[0x51]	15277	1			T5	1		T1	6		T4	3
valid_sources[0x52]	16194	1			T5	2		T1	9		T4	3
valid_sources[0x53]	16005	1			T1	2		T4	5		T2	7
valid_sources[0x54]	15108	1			T1	1		T4	5		T2	4
valid_sources[0x55]	14041	1			T1	8		T4	5		T2	5
valid_sources[0x56]	15225	1			T1	8		T4	2		T2	3
valid_sources[0x57]	14565	1			T1	3		T4	3		T2	2
valid_sources[0x58]	13989	1			T1	3		T4	4		T2	3
valid_sources[0x59]	16238	1			T1	9		T4	2		T2	8
valid_sources[0x5a]	15326	1			T1	8		T4	1		T2	9
valid_sources[0x5b]	16758	1			T1	6		T4	6		T2	2
valid_sources[0x5c]	14961	1			T1	14		T4	6		T2	2
valid_sources[0x5d]	15637	1			T1	5		T4	2		T2	6
valid_sources[0x5e]	17345	1			T1	3		T4	4		T2	6
valid_sources[0x5f]	15602	1			T1	11		T4	1		T2	9
valid_sources[0x60]	15801	1			T1	9		T2	3		T81	4
valid_sources[0x61]	13429	1			T1	8		T4	2		T2	9
valid_sources[0x62]	14896	1			T1	2		T4	4		T2	2
valid_sources[0x63]	15319	1			T1	7		T4	6		T2	10
valid_sources[0x64]	17833	1			T1	3		T6	1		T4	1
valid_sources[0x65]	15511	1			T1	10		T4	5		T2	10
valid_sources[0x66]	15928	1			T1	4		T2	6		T114	1
valid_sources[0x67]	15203	1			T1	3		T4	5		T2	8
valid_sources[0x68]	14189	1			T1	6		T4	2		T2	3
valid_sources[0x69]	14854	1			T1	7		T4	3		T2	5
valid_sources[0x6a]	16136	1			T1	6		T4	2		T2	8
valid_sources[0x6b]	16175	1			T1	4		T4	3		T2	7
valid_sources[0x6c]	14607	1			T1	8		T4	2		T2	5
valid_sources[0x6d]	14624	1			T1	4		T4	3		T2	5
valid_sources[0x6e]	15374	1			T1	9		T4	5		T2	5
valid_sources[0x6f]	14342	1			T1	9		T4	4		T2	4
valid_sources[0x70]	16464	1			T1	5		T4	5		T2	11
valid_sources[0x71]	15164	1			T1	6		T6	4		T4	1
valid_sources[0x72]	15520	1			T1	7		T4	1		T2	6
valid_sources[0x73]	14690	1			T1	5		T4	4		T2	10
valid_sources[0x74]	15012	1			T1	9		T4	2		T2	6
valid_sources[0x75]	15720	1			T1	6		T4	1		T2	15
valid_sources[0x76]	15486	1			T1	11		T2	5		T78	1
valid_sources[0x77]	15732	1			T5	2		T1	2		T4	1
valid_sources[0x78]	15770	1			T1	5		T4	4		T2	7
valid_sources[0x79]	15755	1			T1	4		T4	5		T2	5
valid_sources[0x7a]	15436	1			T1	4		T2	2		T27	2
valid_sources[0x7b]	14744	1			T1	11		T4	1		T2	2
valid_sources[0x7c]	13590	1			T5	1		T1	6		T4	2
valid_sources[0x7d]	16031	1			T1	8		T4	3		T2	9
valid_sources[0x7e]	14243	1			T5	2		T1	5		T15	16
valid_sources[0x7f]	14631	1			T5	1		T1	7		T4	5
valid_sources[0x80]	16743	1			T1	3		T4	5		T2	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

839627

1

T1

152

T15

6

T4

211

values[0x0]

all_enables

biggest_size

1265965

1

T1

348

T6

6

T15

8

values[0x1]

all_enables

biggest_size

1218809

1

T1

179

T6

1

T15

2