Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	777521595	76616	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777521595	76616	0	0
T1	1356335	476	0	0
T2	3299455	204	0	0
T3	0	910	0	0
T4	302265	0	0	0
T6	6535	0	0	0
T7	0	72	0	0
T8	0	785	0	0
T9	0	190	0	0
T10	0	632	0	0
T11	0	110	0	0
T12	0	678	0	0
T13	0	2042	0	0
T14	8660	0	0	0
T15	13180	0	0	0
T16	5250	0	0	0
T17	940235	0	0	0
T18	7750	0	0	0
T19	262860	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	155504319	11116	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155504319	11116	0	0
T1	271267	70	0	0
T2	659891	30	0	0
T3	0	117	0	0
T4	60453	0	0	0
T6	1307	0	0	0
T7	0	10	0	0
T8	0	115	0	0
T9	0	24	0	0
T10	0	100	0	0
T11	0	14	0	0
T12	0	89	0	0
T13	0	273	0	0
T14	1732	0	0	0
T15	2636	0	0	0
T16	1050	0	0	0
T17	188047	0	0	0
T18	1550	0	0	0
T19	52572	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	155504319	15367	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155504319	15367	0	0
T1	271267	95	0	0
T2	659891	42	0	0
T3	0	183	0	0
T4	60453	0	0	0
T6	1307	0	0	0
T7	0	15	0	0
T8	0	155	0	0
T9	0	38	0	0
T10	0	128	0	0
T11	0	22	0	0
T12	0	134	0	0
T13	0	411	0	0
T14	1732	0	0	0
T15	2636	0	0	0
T16	1050	0	0	0
T17	188047	0	0	0
T18	1550	0	0	0
T19	52572	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	155504319	23515	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155504319	23515	0	0
T1	271267	146	0	0
T2	659891	66	0	0
T3	0	297	0	0
T4	60453	0	0	0
T6	1307	0	0	0
T7	0	22	0	0
T8	0	261	0	0
T9	0	62	0	0
T10	0	174	0	0
T11	0	36	0	0
T12	0	232	0	0
T13	0	679	0	0
T14	1732	0	0	0
T15	2636	0	0	0
T16	1050	0	0	0
T17	188047	0	0	0
T18	1550	0	0	0
T19	52572	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	155504319	11128	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155504319	11128	0	0
T1	271267	69	0	0
T2	659891	26	0	0
T3	0	131	0	0
T4	60453	0	0	0
T6	1307	0	0	0
T7	0	10	0	0
T8	0	99	0	0
T9	0	28	0	0
T10	0	101	0	0
T11	0	16	0	0
T12	0	86	0	0
T13	0	267	0	0
T14	1732	0	0	0
T15	2636	0	0	0
T16	1050	0	0	0
T17	188047	0	0	0
T18	1550	0	0	0
T19	52572	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	155504319	15490	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155504319	15490	0	0
T1	271267	96	0	0
T2	659891	40	0	0
T3	0	182	0	0
T4	60453	0	0	0
T6	1307	0	0	0
T7	0	15	0	0
T8	0	155	0	0
T9	0	38	0	0
T10	0	129	0	0
T11	0	22	0	0
T12	0	137	0	0
T13	0	412	0	0
T14	1732	0	0	0
T15	2636	0	0	0
T16	1050	0	0	0
T17	188047	0	0	0
T18	1550	0	0	0
T19	52572	0	0	0