Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T5,T1,T4

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	155504319	152568066	0	0
AllClkBypReqTrue_A	155504319	132519	0	0
IoClkBypReqFalse_A	155504319	152491275	0	2415
IoClkBypReqTrue_A	155504319	204698	0	0
LcClkBypAckFalse_A	155504319	152581808	0	0
LcClkBypAckTrue_A	155504319	118777	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155504319	152568066	0	0
T1	271267	270292	0	0
T2	659891	659070	0	0
T4	60453	9467	0	0
T5	8001	5709	0	0
T6	1307	1275	0	0
T14	1732	1611	0	0
T15	2636	2262	0	0
T16	1050	967	0	0
T17	188047	187938	0	0
T18	1550	1542	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155504319	132519	0	0
T1	271267	339	0	0
T2	659891	80	0	0
T4	60453	0	0	0
T6	1307	0	0	0
T14	1732	0	0	0
T15	2636	247	0	0
T16	1050	0	0	0
T17	188047	0	0	0
T18	1550	0	0	0
T19	52572	78	0	0
T24	0	196	0	0
T25	0	153	0	0
T78	0	182	0	0
T80	0	210	0	0
T111	0	4	0	0
T112	0	148	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155504319	152491275	0	2415
T1	271267	269848	0	3
T2	659891	658818	0	3
T4	60453	9431	0	3
T5	8001	5607	0	3
T6	1307	1273	0	3
T14	1732	1609	0	3
T15	2636	1993	0	3
T16	1050	965	0	3
T17	188047	187936	0	3
T18	1550	1540	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155504319	204698	0	0
T1	271267	767	0	0
T2	659891	324	0	0
T4	60453	0	0	0
T6	1307	0	0	0
T14	1732	0	0	0
T15	2636	514	0	0
T16	1050	0	0	0
T17	188047	0	0	0
T18	1550	0	0	0
T19	52572	130	0	0
T24	0	343	0	0
T78	0	402	0	0
T80	0	294	0	0
T82	0	242	0	0
T83	0	44	0	0
T112	0	49	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155504319	152581808	0	0
T1	271267	270134	0	0
T2	659891	659020	0	0
T4	60453	9467	0	0
T5	8001	5709	0	0
T6	1307	1275	0	0
T14	1732	1611	0	0
T15	2636	2234	0	0
T16	1050	967	0	0
T17	188047	187938	0	0
T18	1550	1542	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155504319	118777	0	0
T1	271267	497	0	0
T2	659891	130	0	0
T4	60453	0	0	0
T6	1307	0	0	0
T14	1732	0	0	0
T15	2636	275	0	0
T16	1050	0	0	0
T17	188047	0	0	0
T18	1550	0	0	0
T19	52572	115	0	0
T24	0	187	0	0
T78	0	172	0	0
T80	0	131	0	0
T82	0	61	0	0
T83	0	42	0	0
T112	0	41	0	0