Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1617000696	15624	0	0
TransStop_A	1617000696	8045	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1617000696	15624	0	0
T1	2166408	29	0	0
T2	2653636	0	0	0
T4	503764	0	0	0
T6	37380	0	0	0
T14	6704	0	0	0
T15	10548	0	0	0
T16	7952	0	0	0
T17	727432	0	0	0
T18	77556	4	0	0
T19	828232	8	0	0
T35	0	4	0	0
T79	0	26	0	0
T81	0	12	0	0
T97	0	14	0	0
T113	0	4	0	0
T114	0	17	0	0
T115	0	25	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1617000696	8045	0	0
T1	2166408	20	0	0
T2	2653636	0	0	0
T3	0	48	0	0
T4	503764	0	0	0
T6	37380	0	0	0
T14	6704	0	0	0
T15	10548	0	0	0
T16	7952	0	0	0
T17	727432	0	0	0
T18	77556	4	0	0
T19	828232	8	0	0
T35	0	4	0	0
T36	0	13	0	0
T64	0	1	0	0
T79	0	11	0	0
T81	0	2	0	0
T97	0	3	0	0
T113	0	4	0	0
T114	0	4	0	0
T115	0	18	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	404250174	3953	0	0
TransStop_A	404250174	2016	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404250174	3953	0	0
T1	541602	8	0	0
T2	663409	0	0	0
T4	125941	0	0	0
T6	9345	0	0	0
T14	1676	0	0	0
T15	2637	0	0	0
T16	1988	0	0	0
T17	181858	0	0	0
T18	19389	1	0	0
T19	207058	2	0	0
T35	0	1	0	0
T79	0	7	0	0
T81	0	2	0	0
T97	0	3	0	0
T113	0	1	0	0
T114	0	2	0	0
T115	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404250174	2016	0	0
T1	541602	5	0	0
T2	663409	0	0	0
T3	0	16	0	0
T4	125941	0	0	0
T6	9345	0	0	0
T14	1676	0	0	0
T15	2637	0	0	0
T16	1988	0	0	0
T17	181858	0	0	0
T18	19389	1	0	0
T19	207058	2	0	0
T35	0	1	0	0
T36	0	13	0	0
T64	0	1	0	0
T79	0	3	0	0
T113	0	1	0	0
T115	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	404250174	3928	0	0
TransStop_A	404250174	2049	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404250174	3928	0	0
T1	541602	7	0	0
T2	663409	0	0	0
T4	125941	0	0	0
T6	9345	0	0	0
T14	1676	0	0	0
T15	2637	0	0	0
T16	1988	0	0	0
T17	181858	0	0	0
T18	19389	1	0	0
T19	207058	2	0	0
T35	0	1	0	0
T79	0	7	0	0
T81	0	3	0	0
T97	0	3	0	0
T113	0	1	0	0
T114	0	6	0	0
T115	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404250174	2049	0	0
T1	541602	5	0	0
T2	663409	0	0	0
T3	0	17	0	0
T4	125941	0	0	0
T6	9345	0	0	0
T14	1676	0	0	0
T15	2637	0	0	0
T16	1988	0	0	0
T17	181858	0	0	0
T18	19389	1	0	0
T19	207058	2	0	0
T35	0	1	0	0
T79	0	1	0	0
T97	0	1	0	0
T113	0	1	0	0
T114	0	2	0	0
T115	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	404250174	3881	0	0
TransStop_A	404250174	1991	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404250174	3881	0	0
T1	541602	7	0	0
T2	663409	0	0	0
T4	125941	0	0	0
T6	9345	0	0	0
T14	1676	0	0	0
T15	2637	0	0	0
T16	1988	0	0	0
T17	181858	0	0	0
T18	19389	1	0	0
T19	207058	2	0	0
T35	0	1	0	0
T79	0	6	0	0
T81	0	3	0	0
T97	0	4	0	0
T113	0	1	0	0
T114	0	6	0	0
T115	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404250174	1991	0	0
T1	541602	4	0	0
T2	663409	0	0	0
T4	125941	0	0	0
T6	9345	0	0	0
T14	1676	0	0	0
T15	2637	0	0	0
T16	1988	0	0	0
T17	181858	0	0	0
T18	19389	1	0	0
T19	207058	2	0	0
T35	0	1	0	0
T79	0	4	0	0
T81	0	1	0	0
T97	0	1	0	0
T113	0	1	0	0
T114	0	2	0	0
T115	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	404250174	3862	0	0
TransStop_A	404250174	1989	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404250174	3862	0	0
T1	541602	7	0	0
T2	663409	0	0	0
T4	125941	0	0	0
T6	9345	0	0	0
T14	1676	0	0	0
T15	2637	0	0	0
T16	1988	0	0	0
T17	181858	0	0	0
T18	19389	1	0	0
T19	207058	2	0	0
T35	0	1	0	0
T79	0	6	0	0
T81	0	4	0	0
T97	0	4	0	0
T113	0	1	0	0
T114	0	3	0	0
T115	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404250174	1989	0	0
T1	541602	6	0	0
T2	663409	0	0	0
T3	0	15	0	0
T4	125941	0	0	0
T6	9345	0	0	0
T14	1676	0	0	0
T15	2637	0	0	0
T16	1988	0	0	0
T17	181858	0	0	0
T18	19389	1	0	0
T19	207058	2	0	0
T35	0	1	0	0
T79	0	3	0	0
T81	0	1	0	0
T97	0	1	0	0
T113	0	1	0	0
T115	0	4	0	0