Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	155504319	17990003	0	63

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155504319	17990003	0	63
T1	271267	42429	0	0
T2	659891	24735	0	0
T3	0	102698	0	0
T4	60453	0	0	0
T6	1307	0	0	0
T7	0	6882	0	1
T8	0	81888	0	1
T9	0	809742	0	0
T10	0	45575	0	0
T11	0	13266	0	1
T14	1732	0	0	0
T15	2636	0	0	0
T16	1050	0	0	0
T17	188047	0	0	0
T18	1550	0	0	0
T19	52572	1341	0	0
T20	0	1080	0	1
T68	0	0	0	1
T69	0	0	0	1
T116	0	0	0	1
T117	0	0	0	1
T118	0	0	0	1
T119	0	0	0	1