Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	156436161	4819753	0	0
clk_enables_rd_A	156436161	50400	0	0
clk_hints_rd_A	156436161	43793	0	0
extclk_ctrl_rd_A	156436161	56368	0	0
extclk_ctrl_regwen_rd_A	156436161	42744	0	0
jitter_enable_rd_A	156436161	66631	0	0
jitter_regwen_rd_A	156436161	48392	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156436161	4819753	0	0
T3	331769	155793	0	0
T7	27922	0	0	0
T8	238333	0	0	0
T9	296023	143000	0	0
T10	0	165610	0	0
T13	0	137572	0	0
T21	0	105332	0	0
T36	797068	33724	0	0
T57	0	160365	0	0
T58	0	105629	0	0
T59	0	32792	0	0
T60	0	89053	0	0
T61	750	0	0	0
T62	27637	0	0	0
T63	1148	0	0	0
T64	1331	0	0	0
T65	13124	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156436161	50400	0	0
T1	271267	9	0	0
T2	659891	0	0	0
T4	60453	0	0	0
T6	1307	0	0	0
T13	0	2892	0	0
T14	1732	0	0	0
T15	2636	0	0	0
T16	1050	0	0	0
T17	188047	0	0	0
T18	1550	3	0	0
T19	52572	0	0	0
T57	0	6305	0	0
T67	0	6	0	0
T108	0	3	0	0
T132	0	2	0	0
T133	0	7	0	0
T134	0	2	0	0
T135	0	7	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156436161	43793	0	0
T1	271267	5	0	0
T2	659891	0	0	0
T4	60453	0	0	0
T6	1307	0	0	0
T13	0	2809	0	0
T14	1732	0	0	0
T15	2636	0	0	0
T16	1050	0	0	0
T17	188047	0	0	0
T18	1550	3	0	0
T19	52572	0	0	0
T57	0	5605	0	0
T59	0	1190	0	0
T67	0	7	0	0
T108	0	12	0	0
T132	0	10	0	0
T133	0	2	0	0
T134	0	1	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156436161	56368	0	0
T1	271267	68	0	0
T2	659891	0	0	0
T4	60453	112	0	0
T6	1307	0	0	0
T13	0	3515	0	0
T14	1732	0	0	0
T15	2636	0	0	0
T16	1050	0	0	0
T17	188047	0	0	0
T18	1550	0	0	0
T19	52572	0	0	0
T24	0	40	0	0
T25	0	57	0	0
T27	0	13	0	0
T65	0	23	0	0
T82	0	13	0	0
T136	0	60	0	0
T137	0	51	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156436161	42744	0	0
T2	659891	0	0	0
T4	60453	67	0	0
T13	0	2476	0	0
T16	1050	0	0	0
T17	188047	0	0	0
T18	1550	0	0	0
T19	52572	0	0	0
T22	6068	0	0	0
T23	946	0	0	0
T24	2006	0	0	0
T25	1442	0	0	0
T27	0	15	0	0
T57	0	5764	0	0
T59	0	1420	0	0
T65	0	13	0	0
T138	0	13	0	0
T139	0	2206	0	0
T140	0	1994	0	0
T141	0	34	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156436161	66631	0	0
T1	271267	323	0	0
T2	659891	0	0	0
T4	60453	0	0	0
T6	1307	0	0	0
T13	0	3246	0	0
T14	1732	0	0	0
T15	2636	0	0	0
T16	1050	0	0	0
T17	188047	0	0	0
T18	1550	108	0	0
T19	52572	0	0	0
T57	0	6469	0	0
T67	0	150	0	0
T108	0	198	0	0
T132	0	141	0	0
T133	0	141	0	0
T134	0	123	0	0
T135	0	137	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156436161	48392	0	0
T13	443846	2927	0	0
T21	297655	0	0	0
T39	2668	0	0	0
T40	2192	0	0	0
T41	886	0	0	0
T42	2242	0	0	0
T43	839	0	0	0
T44	859	0	0	0
T45	1369	0	0	0
T57	0	6093	0	0
T59	0	1489	0	0
T67	510648	0	0	0
T139	0	2369	0	0
T140	0	2360	0	0
T142	0	2340	0	0
T143	0	3604	0	0
T144	0	705	0	0
T145	0	3147	0	0
T146	0	3119	0	0