Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	45500	0	0
CgEnOn_A	2147483647	36279	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	45500	0	0
T1	3219996	79	0	0
T2	6664353	12	0	0
T4	1195893	54	0	0
T5	65785	153	0	0
T6	57493	3	0	0
T14	17278	49	0	0
T15	27582	3	0	0
T16	19645	39	0	0
T17	1761497	3	0	0
T18	200035	7	0	0
T19	1676654	2	0	0
T22	22122	0	0	0
T23	8127	0	0	0
T34	0	24	0	0
T60	0	5	0	0
T79	0	7	0	0
T81	0	2	0	0
T147	0	10	0	0
T148	0	20	0	0
T149	0	15	0	0
T150	0	15	0	0
T151	0	25	0	0
T152	0	25	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36279	0	0
T1	3219996	55	0	0
T2	6664353	0	0	0
T3	0	59	0	0
T4	1195893	0	0	0
T6	57493	0	0	0
T14	17278	46	0	0
T15	27582	0	0	0
T16	19645	36	0	0
T17	1761497	0	0	0
T18	200035	4	0	0
T19	2119595	8	0	0
T22	22122	0	0	0
T23	8127	0	0	0
T26	0	27	0	0
T34	0	36	0	0
T35	0	3	0	0
T60	0	4	0	0
T79	0	7	0	0
T81	0	2	0	0
T113	0	3	0	0
T147	0	10	0	0
T148	0	20	0	0
T149	0	15	0	0
T150	0	15	0	0
T151	0	25	0	0
T152	0	25	0	0
T153	0	4	0	0
T155	0	37	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	187767898	172	0	0
CgEnOn_A	187767898	172	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187767898	172	0	0
T2	295260	0	0	0
T4	34500	0	0	0
T14	784	5	0	0
T15	1361	0	0	0
T16	831	4	0	0
T17	72877	0	0	0
T18	9294	0	0	0
T19	96523	0	0	0
T22	1519	0	0	0
T23	919	0	0	0
T34	0	4	0	0
T60	0	1	0	0
T147	0	2	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	5	0	0
T152	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187767898	172	0	0
T2	295260	0	0	0
T4	34500	0	0	0
T14	784	5	0	0
T15	1361	0	0	0
T16	831	4	0	0
T17	72877	0	0	0
T18	9294	0	0	0
T19	96523	0	0	0
T22	1519	0	0	0
T23	919	0	0	0
T34	0	4	0	0
T60	0	1	0	0
T147	0	2	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	5	0	0
T152	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	93883363	172	0	0
CgEnOn_A	93883363	172	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93883363	172	0	0
T2	147629	0	0	0
T4	17250	0	0	0
T14	392	5	0	0
T15	679	0	0	0
T16	415	4	0	0
T17	36438	0	0	0
T18	4647	0	0	0
T19	48260	0	0	0
T22	760	0	0	0
T23	460	0	0	0
T34	0	4	0	0
T60	0	1	0	0
T147	0	2	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	5	0	0
T152	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93883363	172	0	0
T2	147629	0	0	0
T4	17250	0	0	0
T14	392	5	0	0
T15	679	0	0	0
T16	415	4	0	0
T17	36438	0	0	0
T18	4647	0	0	0
T19	48260	0	0	0
T22	760	0	0	0
T23	460	0	0	0
T34	0	4	0	0
T60	0	1	0	0
T147	0	2	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	5	0	0
T152	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	377330785	172	0	0
CgEnOn_A	377330785	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377330785	172	0	0
T2	590774	0	0	0
T4	120900	0	0	0
T14	1619	5	0	0
T15	2531	0	0	0
T16	1740	4	0	0
T17	145778	0	0	0
T18	18612	0	0	0
T19	193009	0	0	0
T22	5943	0	0	0
T23	1890	0	0	0
T34	0	4	0	0
T60	0	1	0	0
T147	0	2	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	5	0	0
T152	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377330785	163	0	0
T2	590774	0	0	0
T4	120900	0	0	0
T14	1619	5	0	0
T15	2531	0	0	0
T16	1740	4	0	0
T17	145778	0	0	0
T18	18612	0	0	0
T19	193009	0	0	0
T22	5943	0	0	0
T23	1890	0	0	0
T34	0	4	0	0
T147	0	2	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	5	0	0
T152	0	5	0	0
T153	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	404249753	161	0	0
CgEnOn_A	404249753	159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404249753	161	0	0
T2	663408	0	0	0
T4	125940	0	0	0
T14	1676	6	0	0
T15	2636	0	0	0
T16	1988	4	0	0
T17	181857	0	0	0
T18	19388	0	0	0
T19	207057	0	0	0
T22	6190	0	0	0
T23	1969	0	0	0
T34	0	4	0	0
T61	0	1	0	0
T147	0	1	0	0
T148	0	4	0	0
T149	0	2	0	0
T150	0	3	0	0
T154	0	1	0	0
T156	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404249753	159	0	0
T2	663408	0	0	0
T4	125940	0	0	0
T14	1676	6	0	0
T15	2636	0	0	0
T16	1988	4	0	0
T17	181857	0	0	0
T18	19388	0	0	0
T19	207057	0	0	0
T22	6190	0	0	0
T23	1969	0	0	0
T34	0	4	0	0
T61	0	1	0	0
T147	0	1	0	0
T148	0	4	0	0
T149	0	2	0	0
T150	0	3	0	0
T154	0	1	0	0
T156	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	93883363	172	0	0
CgEnOn_A	93883363	172	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93883363	172	0	0
T2	147629	0	0	0
T4	17250	0	0	0
T14	392	5	0	0
T15	679	0	0	0
T16	415	4	0	0
T17	36438	0	0	0
T18	4647	0	0	0
T19	48260	0	0	0
T22	760	0	0	0
T23	460	0	0	0
T34	0	4	0	0
T60	0	1	0	0
T147	0	2	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	5	0	0
T152	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93883363	172	0	0
T2	147629	0	0	0
T4	17250	0	0	0
T14	392	5	0	0
T15	679	0	0	0
T16	415	4	0	0
T17	36438	0	0	0
T18	4647	0	0	0
T19	48260	0	0	0
T22	760	0	0	0
T23	460	0	0	0
T34	0	4	0	0
T60	0	1	0	0
T147	0	2	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	5	0	0
T152	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	404249753	161	0	0
CgEnOn_A	404249753	159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404249753	161	0	0
T2	663408	0	0	0
T4	125940	0	0	0
T14	1676	6	0	0
T15	2636	0	0	0
T16	1988	4	0	0
T17	181857	0	0	0
T18	19388	0	0	0
T19	207057	0	0	0
T22	6190	0	0	0
T23	1969	0	0	0
T34	0	4	0	0
T61	0	1	0	0
T147	0	1	0	0
T148	0	4	0	0
T149	0	2	0	0
T150	0	3	0	0
T154	0	1	0	0
T156	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404249753	159	0	0
T2	663408	0	0	0
T4	125940	0	0	0
T14	1676	6	0	0
T15	2636	0	0	0
T16	1988	4	0	0
T17	181857	0	0	0
T18	19388	0	0	0
T19	207057	0	0	0
T22	6190	0	0	0
T23	1969	0	0	0
T34	0	4	0	0
T61	0	1	0	0
T147	0	1	0	0
T148	0	4	0	0
T149	0	2	0	0
T150	0	3	0	0
T154	0	1	0	0
T156	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	93883363	172	0	0
CgEnOn_A	93883363	172	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93883363	172	0	0
T2	147629	0	0	0
T4	17250	0	0	0
T14	392	5	0	0
T15	679	0	0	0
T16	415	4	0	0
T17	36438	0	0	0
T18	4647	0	0	0
T19	48260	0	0	0
T22	760	0	0	0
T23	460	0	0	0
T34	0	4	0	0
T60	0	1	0	0
T147	0	2	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	5	0	0
T152	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93883363	172	0	0
T2	147629	0	0	0
T4	17250	0	0	0
T14	392	5	0	0
T15	679	0	0	0
T16	415	4	0	0
T17	36438	0	0	0
T18	4647	0	0	0
T19	48260	0	0	0
T22	760	0	0	0
T23	460	0	0	0
T34	0	4	0	0
T60	0	1	0	0
T147	0	2	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	5	0	0
T152	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T34
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	187767898	7035	0	0
CgEnOn_A	187767898	4740	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187767898	7035	0	0
T1	228546	25	0	0
T2	295260	4	0	0
T4	34500	18	0	0
T5	13132	51	0	0
T6	4439	1	0	0
T14	784	6	0	0
T15	1361	1	0	0
T16	831	5	0	0
T17	72877	1	0	0
T18	9294	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187767898	4740	0	0
T1	228546	17	0	0
T2	295260	0	0	0
T4	34500	0	0	0
T6	4439	0	0	0
T14	784	5	0	0
T15	1361	0	0	0
T16	831	4	0	0
T17	72877	0	0	0
T18	9294	1	0	0
T19	96523	2	0	0
T26	0	9	0	0
T34	0	4	0	0
T35	0	1	0	0
T113	0	1	0	0
T155	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T34
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	93883363	6972	0	0
CgEnOn_A	93883363	4677	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93883363	6972	0	0
T1	114271	23	0	0
T2	147629	4	0	0
T4	17250	18	0	0
T5	6566	51	0	0
T6	2219	1	0	0
T14	392	6	0	0
T15	679	1	0	0
T16	415	5	0	0
T17	36438	1	0	0
T18	4647	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93883363	4677	0	0
T1	114271	15	0	0
T2	147629	0	0	0
T3	0	59	0	0
T4	17250	0	0	0
T6	2219	0	0	0
T14	392	5	0	0
T15	679	0	0	0
T16	415	4	0	0
T17	36438	0	0	0
T18	4647	1	0	0
T19	48260	2	0	0
T26	0	9	0	0
T34	0	4	0	0
T113	0	1	0	0
T155	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T34
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	377330785	7020	0	0
CgEnOn_A	377330785	4716	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377330785	7020	0	0
T1	456562	23	0	0
T2	590774	4	0	0
T4	120900	18	0	0
T5	30725	51	0	0
T6	8970	1	0	0
T14	1619	6	0	0
T15	2531	1	0	0
T16	1740	5	0	0
T17	145778	1	0	0
T18	18612	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377330785	4716	0	0
T1	456562	15	0	0
T2	590774	0	0	0
T4	120900	0	0	0
T6	8970	0	0	0
T14	1619	5	0	0
T15	2531	0	0	0
T16	1740	4	0	0
T17	145778	0	0	0
T18	18612	1	0	0
T19	193009	2	0	0
T26	0	9	0	0
T34	0	4	0	0
T35	0	1	0	0
T113	0	1	0	0
T155	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T34
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	193993096	7023	0	0
CgEnOn_A	193993096	4717	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193993096	7023	0	0
T1	254213	23	0	0
T2	321321	4	0	0
T4	60453	18	0	0
T5	15362	51	0	0
T6	4485	1	0	0
T14	848	3	0	0
T15	1266	1	0	0
T16	915	6	0	0
T17	87293	1	0	0
T18	9307	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193993096	4717	0	0
T1	254213	15	0	0
T2	321321	0	0	0
T4	60453	0	0	0
T6	4485	0	0	0
T14	848	2	0	0
T15	1266	0	0	0
T16	915	5	0	0
T17	87293	0	0	0
T18	9307	1	0	0
T19	105149	2	0	0
T26	0	9	0	0
T34	0	2	0	0
T35	0	1	0	0
T113	0	1	0	0
T155	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Covered	T1,T18,T19
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	404249753	4114	0	0
CgEnOn_A	404249753	4112	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404249753	4114	0	0
T1	541601	8	0	0
T2	663408	0	0	0
T4	125940	0	0	0
T6	9345	0	0	0
T14	1676	6	0	0
T15	2636	0	0	0
T16	1988	4	0	0
T17	181857	0	0	0
T18	19388	1	0	0
T19	207057	2	0	0
T34	0	4	0	0
T35	0	1	0	0
T79	0	7	0	0
T81	0	2	0	0
T97	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404249753	4112	0	0
T1	541601	8	0	0
T2	663408	0	0	0
T4	125940	0	0	0
T6	9345	0	0	0
T14	1676	6	0	0
T15	2636	0	0	0
T16	1988	4	0	0
T17	181857	0	0	0
T18	19388	1	0	0
T19	207057	2	0	0
T34	0	4	0	0
T35	0	1	0	0
T79	0	7	0	0
T81	0	2	0	0
T97	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Covered	T1,T18,T19
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	404249753	4089	0	0
CgEnOn_A	404249753	4087	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404249753	4089	0	0
T1	541601	7	0	0
T2	663408	0	0	0
T4	125940	0	0	0
T6	9345	0	0	0
T14	1676	6	0	0
T15	2636	0	0	0
T16	1988	4	0	0
T17	181857	0	0	0
T18	19388	1	0	0
T19	207057	2	0	0
T34	0	4	0	0
T35	0	1	0	0
T79	0	7	0	0
T81	0	3	0	0
T97	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404249753	4087	0	0
T1	541601	7	0	0
T2	663408	0	0	0
T4	125940	0	0	0
T6	9345	0	0	0
T14	1676	6	0	0
T15	2636	0	0	0
T16	1988	4	0	0
T17	181857	0	0	0
T18	19388	1	0	0
T19	207057	2	0	0
T34	0	4	0	0
T35	0	1	0	0
T79	0	7	0	0
T81	0	3	0	0
T97	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Covered	T1,T18,T19
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	404249753	4042	0	0
CgEnOn_A	404249753	4040	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404249753	4042	0	0
T1	541601	7	0	0
T2	663408	0	0	0
T4	125940	0	0	0
T6	9345	0	0	0
T14	1676	6	0	0
T15	2636	0	0	0
T16	1988	4	0	0
T17	181857	0	0	0
T18	19388	1	0	0
T19	207057	2	0	0
T34	0	4	0	0
T35	0	1	0	0
T79	0	6	0	0
T81	0	3	0	0
T97	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404249753	4040	0	0
T1	541601	7	0	0
T2	663408	0	0	0
T4	125940	0	0	0
T6	9345	0	0	0
T14	1676	6	0	0
T15	2636	0	0	0
T16	1988	4	0	0
T17	181857	0	0	0
T18	19388	1	0	0
T19	207057	2	0	0
T34	0	4	0	0
T35	0	1	0	0
T79	0	6	0	0
T81	0	3	0	0
T97	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Covered	T1,T18,T19
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	404249753	4023	0	0
CgEnOn_A	404249753	4021	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404249753	4023	0	0
T1	541601	7	0	0
T2	663408	0	0	0
T4	125940	0	0	0
T6	9345	0	0	0
T14	1676	6	0	0
T15	2636	0	0	0
T16	1988	4	0	0
T17	181857	0	0	0
T18	19388	1	0	0
T19	207057	2	0	0
T34	0	4	0	0
T35	0	1	0	0
T79	0	6	0	0
T81	0	4	0	0
T97	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404249753	4021	0	0
T1	541601	7	0	0
T2	663408	0	0	0
T4	125940	0	0	0
T6	9345	0	0	0
T14	1676	6	0	0
T15	2636	0	0	0
T16	1988	4	0	0
T17	181857	0	0	0
T18	19388	1	0	0
T19	207057	2	0	0
T34	0	4	0	0
T35	0	1	0	0
T79	0	6	0	0
T81	0	4	0	0
T97	0	4	0	0