Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T16
0	1	Covered	T1,T26,T155
1	0	Covered	T5,T1,T14

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Covered	T14,T16,T34
1	1	Covered	T5,T1,T14

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	852976827	12159	0	0
GateOpen_A	852976827	12159	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	852976827	12159	0	0
T1	1053594	44	0	0
T2	1354986	0	0	0
T4	233105	0	0	0
T6	20115	0	0	0
T14	3645	17	0	0
T15	5839	0	0	0
T16	3903	17	0	0
T17	342388	0	0	0
T18	41861	4	0	0
T19	442941	8	0	0
T26	0	28	0	0
T34	0	14	0	0
T35	0	4	0	0
T113	0	4	0	0
T155	0	29	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	852976827	12159	0	0
T1	1053594	44	0	0
T2	1354986	0	0	0
T4	233105	0	0	0
T6	20115	0	0	0
T14	3645	17	0	0
T15	5839	0	0	0
T16	3903	17	0	0
T17	342388	0	0	0
T18	41861	4	0	0
T19	442941	8	0	0
T26	0	28	0	0
T34	0	14	0	0
T35	0	4	0	0
T113	0	4	0	0
T155	0	29	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T16
0	1	Covered	T1,T26,T155
1	0	Covered	T5,T1,T14

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Covered	T14,T16,T34
1	1	Covered	T5,T1,T14

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	93883791	3009	0	0
GateOpen_A	93883791	3009	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93883791	3009	0	0
T1	114272	9	0	0
T2	147629	0	0	0
T4	17251	0	0	0
T6	2220	0	0	0
T14	392	5	0	0
T15	680	0	0	0
T16	416	4	0	0
T17	36439	0	0	0
T18	4647	1	0	0
T19	48260	2	0	0
T26	0	6	0	0
T34	0	4	0	0
T35	0	1	0	0
T113	0	1	0	0
T155	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93883791	3009	0	0
T1	114272	9	0	0
T2	147629	0	0	0
T4	17251	0	0	0
T6	2220	0	0	0
T14	392	5	0	0
T15	680	0	0	0
T16	416	4	0	0
T17	36439	0	0	0
T18	4647	1	0	0
T19	48260	2	0	0
T26	0	6	0	0
T34	0	4	0	0
T35	0	1	0	0
T113	0	1	0	0
T155	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T16
0	1	Covered	T1,T26,T155
1	0	Covered	T5,T1,T14

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Covered	T14,T16,T34
1	1	Covered	T5,T1,T14

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	187768297	3057	0	0
GateOpen_A	187768297	3057	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187768297	3057	0	0
T1	228546	12	0	0
T2	295260	0	0	0
T4	34501	0	0	0
T6	4439	0	0	0
T14	784	5	0	0
T15	1361	0	0	0
T16	831	4	0	0
T17	72877	0	0	0
T18	9294	1	0	0
T19	96523	2	0	0
T26	0	7	0	0
T34	0	4	0	0
T35	0	1	0	0
T113	0	1	0	0
T155	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187768297	3057	0	0
T1	228546	12	0	0
T2	295260	0	0	0
T4	34501	0	0	0
T6	4439	0	0	0
T14	784	5	0	0
T15	1361	0	0	0
T16	831	4	0	0
T17	72877	0	0	0
T18	9294	1	0	0
T19	96523	2	0	0
T26	0	7	0	0
T34	0	4	0	0
T35	0	1	0	0
T113	0	1	0	0
T155	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T16
0	1	Covered	T1,T26,T155
1	0	Covered	T5,T1,T14

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Covered	T14,T16,T34
1	1	Covered	T5,T1,T14

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	377331233	3047	0	0
GateOpen_A	377331233	3047	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377331233	3047	0	0
T1	456563	10	0	0
T2	590775	0	0	0
T4	120900	0	0	0
T6	8971	0	0	0
T14	1620	5	0	0
T15	2532	0	0	0
T16	1741	4	0	0
T17	145779	0	0	0
T18	18613	1	0	0
T19	193009	2	0	0
T26	0	7	0	0
T34	0	4	0	0
T35	0	1	0	0
T113	0	1	0	0
T155	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377331233	3047	0	0
T1	456563	10	0	0
T2	590775	0	0	0
T4	120900	0	0	0
T6	8971	0	0	0
T14	1620	5	0	0
T15	2532	0	0	0
T16	1741	4	0	0
T17	145779	0	0	0
T18	18613	1	0	0
T19	193009	2	0	0
T26	0	7	0	0
T34	0	4	0	0
T35	0	1	0	0
T113	0	1	0	0
T155	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T16
0	1	Covered	T1,T26,T155
1	0	Covered	T5,T1,T14

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Covered	T14,T16,T34
1	1	Covered	T5,T1,T14

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	193993506	3046	0	0
GateOpen_A	193993506	3046	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193993506	3046	0	0
T1	254213	13	0	0
T2	321322	0	0	0
T4	60453	0	0	0
T6	4485	0	0	0
T14	849	2	0	0
T15	1266	0	0	0
T16	915	5	0	0
T17	87293	0	0	0
T18	9307	1	0	0
T19	105149	2	0	0
T26	0	8	0	0
T34	0	2	0	0
T35	0	1	0	0
T113	0	1	0	0
T155	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193993506	3046	0	0
T1	254213	13	0	0
T2	321322	0	0	0
T4	60453	0	0	0
T6	4485	0	0	0
T14	849	2	0	0
T15	1266	0	0	0
T16	915	5	0	0
T17	87293	0	0	0
T18	9307	1	0	0
T19	105149	2	0	0
T26	0	8	0	0
T34	0	2	0	0
T35	0	1	0	0
T113	0	1	0	0
T155	0	6	0	0