Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.47	99.11	95.67	100.00	100.00	98.71	97.01	98.80

Total test records in report: 1010

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1002	/workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.1020683570			Apr 18 01:30:59 PM PDT 24	Apr 18 01:31:07 PM PDT 24	194396459 ps
T1003	/workspace/coverage/cover_reg_top/22.clkmgr_intr_test.4032782837			Apr 18 01:30:53 PM PDT 24	Apr 18 01:30:58 PM PDT 24	16450165 ps
T1004	/workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.2765319874			Apr 18 01:30:44 PM PDT 24	Apr 18 01:30:51 PM PDT 24	360083411 ps
T1005	/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.1444457980			Apr 18 01:30:55 PM PDT 24	Apr 18 01:31:01 PM PDT 24	252233037 ps
T106	/workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.196400837			Apr 18 01:30:51 PM PDT 24	Apr 18 01:30:55 PM PDT 24	123458117 ps
T1006	/workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.182214800			Apr 18 01:30:54 PM PDT 24	Apr 18 01:31:00 PM PDT 24	36612623 ps
T1007	/workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.420821048			Apr 18 01:30:46 PM PDT 24	Apr 18 01:30:49 PM PDT 24	105962496 ps
T1008	/workspace/coverage/cover_reg_top/4.clkmgr_intr_test.2046071615			Apr 18 01:30:51 PM PDT 24	Apr 18 01:30:55 PM PDT 24	14608914 ps
T1009	/workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.2260182796			Apr 18 01:30:45 PM PDT 24	Apr 18 01:30:47 PM PDT 24	89660151 ps
T1010	/workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.221659961			Apr 18 01:30:39 PM PDT 24	Apr 18 01:30:40 PM PDT 24	22543747 ps

Test location	/workspace/coverage/default/0.clkmgr_stress_all.3801450107
Short name	T1
Test name
Test status
Simulation time	5536039140 ps
CPU time	28.39 seconds
Started	Apr 18 01:31:41 PM PDT 24
Finished	Apr 18 01:32:11 PM PDT 24
Peak memory	200968 kb
Host	smart-85696b23-2f71-448e-9367-0555c0aa7c27
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801450107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all.3801450107
Directory	/workspace/0.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/46.clkmgr_stress_all_with_rand_reset.2456367446
Short name	T3
Test name
Test status
Simulation time	33176939737 ps
CPU time	607.59 seconds
Started	Apr 18 01:33:26 PM PDT 24
Finished	Apr 18 01:43:34 PM PDT 24
Peak memory	216940 kb
Host	smart-1a44f6b9-2057-410a-bfcc-92bbf8f10c75
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2456367446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.2456367446
Directory	/workspace/46.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3837173675
Short name	T52
Test name
Test status
Simulation time	308534660 ps
CPU time	2.28 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:59 PM PDT 24
Peak memory	201100 kb
Host	smart-88929245-18cb-4b92-ab6d-e90725d21d63
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837173675 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 19.clkmgr_shadow_reg_errors.3837173675
Directory	/workspace/19.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/default/6.clkmgr_regwen.2852524298
Short name	T190
Test name
Test status
Simulation time	557136985 ps
CPU time	2.18 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:55 PM PDT 24
Peak memory	200580 kb
Host	smart-c5dc562e-f290-4683-97c7-13f84f51b09a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852524298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.2852524298
Directory	/workspace/6.clkmgr_regwen/latest

Test location	/workspace/coverage/default/4.clkmgr_sec_cm.2390341779
Short name	T37
Test name
Test status
Simulation time	286651805 ps
CPU time	2.87 seconds
Started	Apr 18 01:31:50 PM PDT 24
Finished	Apr 18 01:31:57 PM PDT 24
Peak memory	217420 kb
Host	smart-63fe4933-362c-4731-a8be-d4865404a2e4
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390341779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg r_sec_cm.2390341779
Directory	/workspace/4.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/17.clkmgr_clk_status.3805306203
Short name	T16
Test name
Test status
Simulation time	21449491 ps
CPU time	0.71 seconds
Started	Apr 18 01:31:54 PM PDT 24
Finished	Apr 18 01:31:58 PM PDT 24
Peak memory	200252 kb
Host	smart-6579fb05-1491-4197-aa37-96062260cbb1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805306203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.3805306203
Directory	/workspace/17.clkmgr_clk_status/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.1237409602
Short name	T49
Test name
Test status
Simulation time	195615436 ps
CPU time	3.25 seconds
Started	Apr 18 01:30:53 PM PDT 24
Finished	Apr 18 01:31:01 PM PDT 24
Peak memory	209360 kb
Host	smart-ff089ed7-1159-4820-ac7f-06c4c24fc70f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237409602 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.1237409602
Directory	/workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/17.clkmgr_idle_intersig_mubi.3044997507
Short name	T171
Test name
Test status
Simulation time	24103715 ps
CPU time	0.83 seconds
Started	Apr 18 01:32:05 PM PDT 24
Finished	Apr 18 01:32:06 PM PDT 24
Peak memory	200576 kb
Host	smart-0f5b6d26-6c80-4d76-940f-b85968e6dddc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044997507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_idle_intersig_mubi.3044997507
Directory	/workspace/17.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.679040153
Short name	T98
Test name
Test status
Simulation time	195561266 ps
CPU time	2.72 seconds
Started	Apr 18 01:30:41 PM PDT 24
Finished	Apr 18 01:30:44 PM PDT 24
Peak memory	200648 kb
Host	smart-1731886a-bda6-4256-a7ea-4872be4b8e9e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679040153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 5.clkmgr_tl_intg_err.679040153
Directory	/workspace/5.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/26.clkmgr_alert_test.2108739151
Short name	T6
Test name
Test status
Simulation time	93468764 ps
CPU time	0.95 seconds
Started	Apr 18 01:32:30 PM PDT 24
Finished	Apr 18 01:32:32 PM PDT 24
Peak memory	200468 kb
Host	smart-f3a2a702-639e-4013-9f6a-4794a85b0533
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108739151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk mgr_alert_test.2108739151
Directory	/workspace/26.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/26.clkmgr_stress_all_with_rand_reset.1917642318
Short name	T13
Test name
Test status
Simulation time	57642318671 ps
CPU time	687.72 seconds
Started	Apr 18 01:32:35 PM PDT 24
Finished	Apr 18 01:44:03 PM PDT 24
Peak memory	211748 kb
Host	smart-f44a1840-5ba2-43f2-acd4-e15cb5a26943
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1917642318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.1917642318
Directory	/workspace/26.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.3926445272
Short name	T78
Test name
Test status
Simulation time	26904865 ps
CPU time	0.89 seconds
Started	Apr 18 01:31:46 PM PDT 24
Finished	Apr 18 01:31:51 PM PDT 24
Peak memory	200608 kb
Host	smart-24db21a7-61ab-45bb-aa49-623939734dff
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926445272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_handshake_intersig_mubi.3926445272
Directory	/workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.676398520
Short name	T100
Test name
Test status
Simulation time	435762228 ps
CPU time	3.45 seconds
Started	Apr 18 01:30:40 PM PDT 24
Finished	Apr 18 01:30:44 PM PDT 24
Peak memory	200592 kb
Host	smart-d94e9f24-7eee-47b7-a7ec-e4e9f7274061
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676398520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 1.clkmgr_tl_intg_err.676398520
Directory	/workspace/1.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.325437388
Short name	T127
Test name
Test status
Simulation time	194747957 ps
CPU time	1.87 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:59 PM PDT 24
Peak memory	209216 kb
Host	smart-629a9157-dee0-4873-83f9-cded9abd0303
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325437388 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 12.clkmgr_shadow_reg_errors.325437388
Directory	/workspace/12.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.4235994286
Short name	T129
Test name
Test status
Simulation time	78589660 ps
CPU time	1.18 seconds
Started	Apr 18 01:30:53 PM PDT 24
Finished	Apr 18 01:30:58 PM PDT 24
Peak memory	200876 kb
Host	smart-d5c5497e-d7f5-4e70-bbae-f04dfd833d0c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235994286 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 18.clkmgr_shadow_reg_errors.4235994286
Directory	/workspace/18.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.451130448
Short name	T120
Test name
Test status
Simulation time	133485942 ps
CPU time	2.21 seconds
Started	Apr 18 01:30:46 PM PDT 24
Finished	Apr 18 01:30:49 PM PDT 24
Peak memory	201216 kb
Host	smart-024c8d70-1edb-4985-b3ba-be658c3ba1b1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451130448 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.clkmgr_shadow_reg_errors.451130448
Directory	/workspace/0.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/default/0.clkmgr_regwen.3328491700
Short name	T65
Test name
Test status
Simulation time	354726976 ps
CPU time	1.95 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:31:54 PM PDT 24
Peak memory	200548 kb
Host	smart-d1e42317-054f-44da-9c6e-3b7a518fcaf0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328491700 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.3328491700
Directory	/workspace/0.clkmgr_regwen/latest

Test location	/workspace/coverage/default/1.clkmgr_stress_all_with_rand_reset.208834487
Short name	T9
Test name
Test status
Simulation time	29602366203 ps
CPU time	540.55 seconds
Started	Apr 18 01:31:41 PM PDT 24
Finished	Apr 18 01:40:43 PM PDT 24
Peak memory	210144 kb
Host	smart-7acce679-916c-4923-a8e2-136b88f69a5d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=208834487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.208834487
Directory	/workspace/1.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.1822197992
Short name	T99
Test name
Test status
Simulation time	134732305 ps
CPU time	2.34 seconds
Started	Apr 18 01:30:50 PM PDT 24
Finished	Apr 18 01:30:55 PM PDT 24
Peak memory	200636 kb
Host	smart-add71d3f-d634-4070-ab9c-5d4c3d6dfa8c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822197992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 11.clkmgr_tl_intg_err.1822197992
Directory	/workspace/11.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.776418816
Short name	T107
Test name
Test status
Simulation time	444831692 ps
CPU time	2.62 seconds
Started	Apr 18 01:30:55 PM PDT 24
Finished	Apr 18 01:31:03 PM PDT 24
Peak memory	200660 kb
Host	smart-24784821-e877-43a3-b4b1-884fc54f87fe
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776418816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 15.clkmgr_tl_intg_err.776418816
Directory	/workspace/15.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1978358406
Short name	T102
Test name
Test status
Simulation time	95589512 ps
CPU time	2.42 seconds
Started	Apr 18 01:30:55 PM PDT 24
Finished	Apr 18 01:31:03 PM PDT 24
Peak memory	200684 kb
Host	smart-97eed6a8-8ff6-4a0e-8fde-0670ac15200f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978358406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 17.clkmgr_tl_intg_err.1978358406
Directory	/workspace/17.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/10.clkmgr_regwen.1280823337
Short name	T555
Test name
Test status
Simulation time	1247971358 ps
CPU time	7 seconds
Started	Apr 18 01:31:52 PM PDT 24
Finished	Apr 18 01:32:02 PM PDT 24
Peak memory	200656 kb
Host	smart-818e025c-652e-4f43-b46c-40585f679b0e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280823337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.1280823337
Directory	/workspace/10.clkmgr_regwen/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.2602549244
Short name	T887
Test name
Test status
Simulation time	74796528 ps
CPU time	1.33 seconds
Started	Apr 18 01:30:41 PM PDT 24
Finished	Apr 18 01:30:43 PM PDT 24
Peak memory	200432 kb
Host	smart-ffc3d930-abe5-4e6a-8610-9e35b12d9f44
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602549244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_aliasing.2602549244
Directory	/workspace/0.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.3419021094
Short name	T969
Test name
Test status
Simulation time	417165928 ps
CPU time	8.12 seconds
Started	Apr 18 01:30:38 PM PDT 24
Finished	Apr 18 01:30:46 PM PDT 24
Peak memory	200648 kb
Host	smart-faa517f6-27ca-4631-8ae2-649203a1c0b3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419021094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_bit_bash.3419021094
Directory	/workspace/0.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.3864014077
Short name	T946
Test name
Test status
Simulation time	32927253 ps
CPU time	0.86 seconds
Started	Apr 18 01:30:33 PM PDT 24
Finished	Apr 18 01:30:34 PM PDT 24
Peak memory	200280 kb
Host	smart-268fd1b1-fa7e-4954-a84b-5f5a5d89481e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864014077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_hw_reset.3864014077
Directory	/workspace/0.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2819453818
Short name	T858
Test name
Test status
Simulation time	27975095 ps
CPU time	1.41 seconds
Started	Apr 18 01:30:37 PM PDT 24
Finished	Apr 18 01:30:39 PM PDT 24
Peak memory	200744 kb
Host	smart-50245d57-1007-48fb-9d8a-6977d54d030d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819453818 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.2819453818
Directory	/workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.2956654307
Short name	T982
Test name
Test status
Simulation time	14524154 ps
CPU time	0.74 seconds
Started	Apr 18 01:30:53 PM PDT 24
Finished	Apr 18 01:30:59 PM PDT 24
Peak memory	200456 kb
Host	smart-d4519e5c-6e47-4045-9e1c-4c44217244eb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956654307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. clkmgr_csr_rw.2956654307
Directory	/workspace/0.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_intr_test.3500266059
Short name	T936
Test name
Test status
Simulation time	69486294 ps
CPU time	0.85 seconds
Started	Apr 18 01:30:37 PM PDT 24
Finished	Apr 18 01:30:38 PM PDT 24
Peak memory	198952 kb
Host	smart-3aa89a1c-98a7-4b2d-b2a0-5723a326b9ea
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500266059 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk mgr_intr_test.3500266059
Directory	/workspace/0.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.542475234
Short name	T76
Test name
Test status
Simulation time	141532715 ps
CPU time	1.47 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:58 PM PDT 24
Peak memory	200684 kb
Host	smart-5014326e-fd45-495c-9e1e-70e44a29d7a2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542475234 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 0.clkmgr_same_csr_outstanding.542475234
Directory	/workspace/0.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.2571846255
Short name	T54
Test name
Test status
Simulation time	248016316 ps
CPU time	2.05 seconds
Started	Apr 18 01:30:34 PM PDT 24
Finished	Apr 18 01:30:37 PM PDT 24
Peak memory	209368 kb
Host	smart-b19c603c-e3a8-4b0e-8ad2-0361bcf38e6d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571846255 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.2571846255
Directory	/workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.3976314123
Short name	T850
Test name
Test status
Simulation time	53339530 ps
CPU time	1.77 seconds
Started	Apr 18 01:30:51 PM PDT 24
Finished	Apr 18 01:30:56 PM PDT 24
Peak memory	200744 kb
Host	smart-beafca08-bfde-4bcc-9e2f-ee775250230b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976314123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk mgr_tl_errors.3976314123
Directory	/workspace/0.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1708713346
Short name	T907
Test name
Test status
Simulation time	106508777 ps
CPU time	1.74 seconds
Started	Apr 18 01:30:38 PM PDT 24
Finished	Apr 18 01:30:41 PM PDT 24
Peak memory	200668 kb
Host	smart-d69ab681-f007-4296-8355-56aa17415c86
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708713346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 0.clkmgr_tl_intg_err.1708713346
Directory	/workspace/0.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.3216463107
Short name	T916
Test name
Test status
Simulation time	36475184 ps
CPU time	1.14 seconds
Started	Apr 18 01:30:33 PM PDT 24
Finished	Apr 18 01:30:34 PM PDT 24
Peak memory	200380 kb
Host	smart-b8c574e0-3d9e-4d7e-ba4e-fa6665b58f84
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216463107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.clkmgr_csr_aliasing.3216463107
Directory	/workspace/1.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.2764597236
Short name	T101
Test name
Test status
Simulation time	1358017103 ps
CPU time	9.52 seconds
Started	Apr 18 01:30:38 PM PDT 24
Finished	Apr 18 01:30:48 PM PDT 24
Peak memory	200616 kb
Host	smart-c4ba7e5a-118e-4fc5-bba7-11b59cb63669
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764597236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.clkmgr_csr_bit_bash.2764597236
Directory	/workspace/1.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2185915971
Short name	T877
Test name
Test status
Simulation time	48600721 ps
CPU time	0.93 seconds
Started	Apr 18 01:30:53 PM PDT 24
Finished	Apr 18 01:30:59 PM PDT 24
Peak memory	200340 kb
Host	smart-3847a620-9155-4a5a-a05a-e18e1d03b093
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185915971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.clkmgr_csr_hw_reset.2185915971
Directory	/workspace/1.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.3807050337
Short name	T967
Test name
Test status
Simulation time	28434936 ps
CPU time	1.35 seconds
Started	Apr 18 01:30:40 PM PDT 24
Finished	Apr 18 01:30:42 PM PDT 24
Peak memory	200740 kb
Host	smart-39657647-d338-46c9-9134-e7840bbbc6bf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807050337 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.3807050337
Directory	/workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.2870768222
Short name	T938
Test name
Test status
Simulation time	58951300 ps
CPU time	0.93 seconds
Started	Apr 18 01:30:42 PM PDT 24
Finished	Apr 18 01:30:44 PM PDT 24
Peak memory	200436 kb
Host	smart-b1ab5e1e-bc4f-40c3-a94d-cba4973c7788
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870768222 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. clkmgr_csr_rw.2870768222
Directory	/workspace/1.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_intr_test.2141735131
Short name	T865
Test name
Test status
Simulation time	14757782 ps
CPU time	0.66 seconds
Started	Apr 18 01:30:34 PM PDT 24
Finished	Apr 18 01:30:35 PM PDT 24
Peak memory	198952 kb
Host	smart-00526f48-89b5-4ef3-a796-f6685ead12db
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141735131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk mgr_intr_test.2141735131
Directory	/workspace/1.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.150443827
Short name	T75
Test name
Test status
Simulation time	24034353 ps
CPU time	0.96 seconds
Started	Apr 18 01:30:44 PM PDT 24
Finished	Apr 18 01:30:46 PM PDT 24
Peak memory	200480 kb
Host	smart-c64f78ad-2b60-409f-b6c9-a11a30c58497
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150443827 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 1.clkmgr_same_csr_outstanding.150443827
Directory	/workspace/1.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.1270111145
Short name	T125
Test name
Test status
Simulation time	117335980 ps
CPU time	1.89 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:58 PM PDT 24
Peak memory	201140 kb
Host	smart-18898fd5-0f2d-4d8c-84e0-500317d059c6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270111145 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 1.clkmgr_shadow_reg_errors.1270111145
Directory	/workspace/1.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.950067175
Short name	T128
Test name
Test status
Simulation time	111423362 ps
CPU time	1.7 seconds
Started	Apr 18 01:30:46 PM PDT 24
Finished	Apr 18 01:30:48 PM PDT 24
Peak memory	201160 kb
Host	smart-0bd69447-1997-4fe7-bb4e-56bbc753b71a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950067175 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.950067175
Directory	/workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.576686862
Short name	T915
Test name
Test status
Simulation time	90585047 ps
CPU time	2.34 seconds
Started	Apr 18 01:30:42 PM PDT 24
Finished	Apr 18 01:30:45 PM PDT 24
Peak memory	200756 kb
Host	smart-6e45305b-0f3e-465c-8525-8de5f05788ca
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576686862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkm gr_tl_errors.576686862
Directory	/workspace/1.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.420821048
Short name	T1007
Test name
Test status
Simulation time	105962496 ps
CPU time	1.97 seconds
Started	Apr 18 01:30:46 PM PDT 24
Finished	Apr 18 01:30:49 PM PDT 24
Peak memory	200680 kb
Host	smart-f3281ea5-99bd-4351-95f0-68b042e3eaad
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420821048 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.420821048
Directory	/workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.4034308117
Short name	T960
Test name
Test status
Simulation time	21167260 ps
CPU time	0.86 seconds
Started	Apr 18 01:30:43 PM PDT 24
Finished	Apr 18 01:30:45 PM PDT 24
Peak memory	200368 kb
Host	smart-e000141d-4a6e-48a8-b6ba-0de3ca755d53
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034308117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .clkmgr_csr_rw.4034308117
Directory	/workspace/10.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_intr_test.2142518142
Short name	T1001
Test name
Test status
Simulation time	14596472 ps
CPU time	0.71 seconds
Started	Apr 18 01:30:43 PM PDT 24
Finished	Apr 18 01:30:44 PM PDT 24
Peak memory	198880 kb
Host	smart-14c29972-61d9-4561-b2d7-7bbd40e887c1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142518142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl kmgr_intr_test.2142518142
Directory	/workspace/10.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.3430119401
Short name	T867
Test name
Test status
Simulation time	32168186 ps
CPU time	0.95 seconds
Started	Apr 18 01:30:46 PM PDT 24
Finished	Apr 18 01:30:48 PM PDT 24
Peak memory	200308 kb
Host	smart-55932770-e184-41e8-8c5f-37cd71b4289d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430119401 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 10.clkmgr_same_csr_outstanding.3430119401
Directory	/workspace/10.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1556436585
Short name	T126
Test name
Test status
Simulation time	226912112 ps
CPU time	2.07 seconds
Started	Apr 18 01:30:47 PM PDT 24
Finished	Apr 18 01:30:51 PM PDT 24
Peak memory	200992 kb
Host	smart-6204ad6e-c5ec-4e7a-8506-d7668787b12e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556436585 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 10.clkmgr_shadow_reg_errors.1556436585
Directory	/workspace/10.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.2749915646
Short name	T953
Test name
Test status
Simulation time	65000144 ps
CPU time	1.66 seconds
Started	Apr 18 01:30:51 PM PDT 24
Finished	Apr 18 01:30:56 PM PDT 24
Peak memory	201248 kb
Host	smart-30ccf2cd-4243-409f-a3fb-6a2ac309b95f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749915646 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.2749915646
Directory	/workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.455263180
Short name	T883
Test name
Test status
Simulation time	86093607 ps
CPU time	2.85 seconds
Started	Apr 18 01:30:40 PM PDT 24
Finished	Apr 18 01:30:43 PM PDT 24
Peak memory	200728 kb
Host	smart-250a9d42-6bdb-49f3-ab1a-e8280a3ea0a0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455263180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clk mgr_tl_errors.455263180
Directory	/workspace/10.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2200012004
Short name	T958
Test name
Test status
Simulation time	333489508 ps
CPU time	2.2 seconds
Started	Apr 18 01:30:46 PM PDT 24
Finished	Apr 18 01:30:50 PM PDT 24
Peak memory	200656 kb
Host	smart-96f7c563-62ad-4b93-9705-33596f846dfa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200012004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 10.clkmgr_tl_intg_err.2200012004
Directory	/workspace/10.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.1021342592
Short name	T857
Test name
Test status
Simulation time	45279892 ps
CPU time	1.48 seconds
Started	Apr 18 01:31:01 PM PDT 24
Finished	Apr 18 01:31:06 PM PDT 24
Peak memory	200536 kb
Host	smart-0e3853f9-eafc-46d2-84a5-ac182a8715eb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021342592 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.1021342592
Directory	/workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.1004492585
Short name	T873
Test name
Test status
Simulation time	21928012 ps
CPU time	0.86 seconds
Started	Apr 18 01:30:55 PM PDT 24
Finished	Apr 18 01:31:00 PM PDT 24
Peak memory	200448 kb
Host	smart-89efb39a-0a27-48a3-a8cc-aac3896c41cc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004492585 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11 .clkmgr_csr_rw.1004492585
Directory	/workspace/11.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_intr_test.3684585897
Short name	T852
Test name
Test status
Simulation time	18720910 ps
CPU time	0.66 seconds
Started	Apr 18 01:30:48 PM PDT 24
Finished	Apr 18 01:30:50 PM PDT 24
Peak memory	198852 kb
Host	smart-a4e0e29c-f327-4bd4-ac83-e8bec86c464f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684585897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl kmgr_intr_test.3684585897
Directory	/workspace/11.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.1312941148
Short name	T964
Test name
Test status
Simulation time	37216931 ps
CPU time	1.08 seconds
Started	Apr 18 01:30:50 PM PDT 24
Finished	Apr 18 01:30:53 PM PDT 24
Peak memory	200472 kb
Host	smart-916b4ceb-7130-4bd1-9479-31bf65aebffd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312941148 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 11.clkmgr_same_csr_outstanding.1312941148
Directory	/workspace/11.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.1662484435
Short name	T122
Test name
Test status
Simulation time	69715908 ps
CPU time	1.4 seconds
Started	Apr 18 01:30:51 PM PDT 24
Finished	Apr 18 01:30:56 PM PDT 24
Peak memory	200872 kb
Host	smart-fef0a23e-8606-4547-bb23-fe26a66392cf
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662484435 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 11.clkmgr_shadow_reg_errors.1662484435
Directory	/workspace/11.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3816463184
Short name	T130
Test name
Test status
Simulation time	432696414 ps
CPU time	2.55 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:59 PM PDT 24
Peak memory	201136 kb
Host	smart-cc971f85-ab62-478b-8f93-f3057ec89e80
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816463184 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.3816463184
Directory	/workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.820144889
Short name	T974
Test name
Test status
Simulation time	585352989 ps
CPU time	2.67 seconds
Started	Apr 18 01:30:49 PM PDT 24
Finished	Apr 18 01:30:53 PM PDT 24
Peak memory	200692 kb
Host	smart-f397913f-8e32-4984-b21e-2c2497a5792b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820144889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clk mgr_tl_errors.820144889
Directory	/workspace/11.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.3396862150
Short name	T854
Test name
Test status
Simulation time	281728064 ps
CPU time	1.64 seconds
Started	Apr 18 01:30:51 PM PDT 24
Finished	Apr 18 01:30:55 PM PDT 24
Peak memory	200516 kb
Host	smart-a2db73e0-24f1-48e8-b847-a134571b3dbe
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396862150 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.3396862150
Directory	/workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.1712956978
Short name	T875
Test name
Test status
Simulation time	17843846 ps
CPU time	0.83 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:57 PM PDT 24
Peak memory	200436 kb
Host	smart-2b5222a0-5dd5-4dd6-b52f-74e376319455
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712956978 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .clkmgr_csr_rw.1712956978
Directory	/workspace/12.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_intr_test.3859960357
Short name	T921
Test name
Test status
Simulation time	17307327 ps
CPU time	0.67 seconds
Started	Apr 18 01:30:53 PM PDT 24
Finished	Apr 18 01:30:58 PM PDT 24
Peak memory	199024 kb
Host	smart-6d056bdb-910a-43c2-9484-c0ad76affaba
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859960357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl kmgr_intr_test.3859960357
Directory	/workspace/12.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.688113342
Short name	T895
Test name
Test status
Simulation time	113531450 ps
CPU time	1.25 seconds
Started	Apr 18 01:30:53 PM PDT 24
Finished	Apr 18 01:30:59 PM PDT 24
Peak memory	200480 kb
Host	smart-1f62acbe-3bbb-4df3-a5cb-f0edbbff26fd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688113342 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 12.clkmgr_same_csr_outstanding.688113342
Directory	/workspace/12.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.2885391282
Short name	T940
Test name
Test status
Simulation time	82627792 ps
CPU time	1.79 seconds
Started	Apr 18 01:30:55 PM PDT 24
Finished	Apr 18 01:31:02 PM PDT 24
Peak memory	201052 kb
Host	smart-7fcf7472-581b-493d-828c-22d0267f9dfa
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885391282 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.2885391282
Directory	/workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.3365080890
Short name	T917
Test name
Test status
Simulation time	142826398 ps
CPU time	2.78 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:59 PM PDT 24
Peak memory	200680 kb
Host	smart-e8d65dd5-e2ba-4085-9e48-d232394b7d7d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365080890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl kmgr_tl_errors.3365080890
Directory	/workspace/12.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.3660430871
Short name	T95
Test name
Test status
Simulation time	86064992 ps
CPU time	1.57 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:57 PM PDT 24
Peak memory	200700 kb
Host	smart-b97f46c0-c7e0-4f67-b62d-5d63c7642e03
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660430871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 12.clkmgr_tl_intg_err.3660430871
Directory	/workspace/12.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.1254150662
Short name	T976
Test name
Test status
Simulation time	62203336 ps
CPU time	1.23 seconds
Started	Apr 18 01:30:50 PM PDT 24
Finished	Apr 18 01:30:54 PM PDT 24
Peak memory	200516 kb
Host	smart-0e53449b-8e4d-4d33-a0b4-2fc469ee44ec
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254150662 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.1254150662
Directory	/workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.3695624784
Short name	T925
Test name
Test status
Simulation time	37797573 ps
CPU time	0.78 seconds
Started	Apr 18 01:30:51 PM PDT 24
Finished	Apr 18 01:30:55 PM PDT 24
Peak memory	200444 kb
Host	smart-3dbc015d-7674-4112-a95a-9bb580a1b884
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695624784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .clkmgr_csr_rw.3695624784
Directory	/workspace/13.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_intr_test.459988080
Short name	T929
Test name
Test status
Simulation time	13438832 ps
CPU time	0.66 seconds
Started	Apr 18 01:30:49 PM PDT 24
Finished	Apr 18 01:30:51 PM PDT 24
Peak memory	198944 kb
Host	smart-645c1bd5-b2fb-441a-847d-3043920bd416
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459988080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clk mgr_intr_test.459988080
Directory	/workspace/13.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.182214800
Short name	T1006
Test name
Test status
Simulation time	36612623 ps
CPU time	0.98 seconds
Started	Apr 18 01:30:54 PM PDT 24
Finished	Apr 18 01:31:00 PM PDT 24
Peak memory	200336 kb
Host	smart-afed8945-d762-4375-baaf-5d7c15d899fc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182214800 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 13.clkmgr_same_csr_outstanding.182214800
Directory	/workspace/13.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.1119597346
Short name	T966
Test name
Test status
Simulation time	400638073 ps
CPU time	2.7 seconds
Started	Apr 18 01:30:51 PM PDT 24
Finished	Apr 18 01:30:58 PM PDT 24
Peak memory	201088 kb
Host	smart-0b6910ee-1782-404e-8d7a-e30a0fd0f489
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119597346 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 13.clkmgr_shadow_reg_errors.1119597346
Directory	/workspace/13.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.727890092
Short name	T124
Test name
Test status
Simulation time	227871772 ps
CPU time	3.04 seconds
Started	Apr 18 01:30:57 PM PDT 24
Finished	Apr 18 01:31:05 PM PDT 24
Peak memory	201300 kb
Host	smart-8dacdb5d-b813-4c22-b1fd-f6e92ba0ddca
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727890092 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.727890092
Directory	/workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.24328154
Short name	T980
Test name
Test status
Simulation time	226149273 ps
CPU time	2.39 seconds
Started	Apr 18 01:30:48 PM PDT 24
Finished	Apr 18 01:30:52 PM PDT 24
Peak memory	200760 kb
Host	smart-4b3be06d-ea65-45e5-9b9e-e3dc7d7df9e4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24328154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ =clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkm gr_tl_errors.24328154
Directory	/workspace/13.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.2894086314
Short name	T941
Test name
Test status
Simulation time	69466122 ps
CPU time	1.6 seconds
Started	Apr 18 01:30:56 PM PDT 24
Finished	Apr 18 01:31:03 PM PDT 24
Peak memory	200688 kb
Host	smart-4223b8c8-8d3a-4906-a7f3-fba160edd312
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894086314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 13.clkmgr_tl_intg_err.2894086314
Directory	/workspace/13.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.3835481634
Short name	T911
Test name
Test status
Simulation time	32911430 ps
CPU time	1.03 seconds
Started	Apr 18 01:30:51 PM PDT 24
Finished	Apr 18 01:30:55 PM PDT 24
Peak memory	200476 kb
Host	smart-b3f771af-e6cd-4b27-8af4-c4163a32a9e1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835481634 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.3835481634
Directory	/workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.186200403
Short name	T910
Test name
Test status
Simulation time	43636219 ps
CPU time	0.83 seconds
Started	Apr 18 01:30:50 PM PDT 24
Finished	Apr 18 01:30:53 PM PDT 24
Peak memory	200352 kb
Host	smart-65cdbe75-57fa-4953-a718-86d2c5b2be99
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186200403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. clkmgr_csr_rw.186200403
Directory	/workspace/14.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_intr_test.1097562095
Short name	T957
Test name
Test status
Simulation time	19413069 ps
CPU time	0.68 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:56 PM PDT 24
Peak memory	199016 kb
Host	smart-14e64361-a09f-40fa-b571-a8732069b17c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097562095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl kmgr_intr_test.1097562095
Directory	/workspace/14.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1737076839
Short name	T996
Test name
Test status
Simulation time	93858456 ps
CPU time	1.48 seconds
Started	Apr 18 01:30:53 PM PDT 24
Finished	Apr 18 01:30:59 PM PDT 24
Peak memory	200508 kb
Host	smart-ab772a72-95d9-46f4-9928-c3762413aa69
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737076839 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 14.clkmgr_same_csr_outstanding.1737076839
Directory	/workspace/14.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.2978129002
Short name	T909
Test name
Test status
Simulation time	126922552 ps
CPU time	2.16 seconds
Started	Apr 18 01:30:54 PM PDT 24
Finished	Apr 18 01:31:01 PM PDT 24
Peak memory	201060 kb
Host	smart-fad7282b-b514-4365-8880-537f96e881e0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978129002 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 14.clkmgr_shadow_reg_errors.2978129002
Directory	/workspace/14.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.585083453
Short name	T920
Test name
Test status
Simulation time	164156098 ps
CPU time	3.04 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:31:00 PM PDT 24
Peak memory	201112 kb
Host	smart-df3da649-50ad-440e-a245-41f1fa7b25aa
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585083453 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.585083453
Directory	/workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.1103619365
Short name	T934
Test name
Test status
Simulation time	53935085 ps
CPU time	1.5 seconds
Started	Apr 18 01:30:50 PM PDT 24
Finished	Apr 18 01:30:54 PM PDT 24
Peak memory	200640 kb
Host	smart-5df7fb12-d3d9-4f26-9d92-7d1d593f40d9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103619365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl kmgr_tl_errors.1103619365
Directory	/workspace/14.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.2076656699
Short name	T104
Test name
Test status
Simulation time	100354700 ps
CPU time	1.81 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:59 PM PDT 24
Peak memory	200600 kb
Host	smart-b14198bf-1048-455c-b022-3ddfc9598500
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076656699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 14.clkmgr_tl_intg_err.2076656699
Directory	/workspace/14.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.2765436034
Short name	T988
Test name
Test status
Simulation time	29283076 ps
CPU time	1.08 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:58 PM PDT 24
Peak memory	200472 kb
Host	smart-e67a3217-f933-4615-9508-3293bd385370
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765436034 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.2765436034
Directory	/workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.782813933
Short name	T955
Test name
Test status
Simulation time	26538212 ps
CPU time	0.82 seconds
Started	Apr 18 01:30:50 PM PDT 24
Finished	Apr 18 01:30:54 PM PDT 24
Peak memory	200468 kb
Host	smart-d270ed0b-010b-4c0a-9ab4-43bd38cf6862
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782813933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. clkmgr_csr_rw.782813933
Directory	/workspace/15.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_intr_test.511509602
Short name	T868
Test name
Test status
Simulation time	34431823 ps
CPU time	0.72 seconds
Started	Apr 18 01:30:55 PM PDT 24
Finished	Apr 18 01:31:01 PM PDT 24
Peak memory	198964 kb
Host	smart-622197f1-26e0-42eb-8c04-550e84d06a1d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511509602 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clk mgr_intr_test.511509602
Directory	/workspace/15.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.2509868896
Short name	T927
Test name
Test status
Simulation time	66041129 ps
CPU time	1.04 seconds
Started	Apr 18 01:30:55 PM PDT 24
Finished	Apr 18 01:31:01 PM PDT 24
Peak memory	200496 kb
Host	smart-9a986736-d52a-4ca1-8236-fa8ec3c16863
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509868896 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 15.clkmgr_same_csr_outstanding.2509868896
Directory	/workspace/15.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.1516979193
Short name	T50
Test name
Test status
Simulation time	375915177 ps
CPU time	2.64 seconds
Started	Apr 18 01:30:56 PM PDT 24
Finished	Apr 18 01:31:04 PM PDT 24
Peak memory	201144 kb
Host	smart-9ee99fa5-cdb6-4723-b6fc-5c25b508f609
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516979193 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 15.clkmgr_shadow_reg_errors.1516979193
Directory	/workspace/15.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.1444457980
Short name	T1005
Test name
Test status
Simulation time	252233037 ps
CPU time	2.13 seconds
Started	Apr 18 01:30:55 PM PDT 24
Finished	Apr 18 01:31:01 PM PDT 24
Peak memory	201196 kb
Host	smart-7d28a799-15b8-4ce4-a076-d4e2bf968eca
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444457980 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.1444457980
Directory	/workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.4116601433
Short name	T891
Test name
Test status
Simulation time	72106117 ps
CPU time	2.35 seconds
Started	Apr 18 01:30:58 PM PDT 24
Finished	Apr 18 01:31:06 PM PDT 24
Peak memory	200664 kb
Host	smart-c1241d2b-3e48-4d4c-9a3a-1dea2a79a9da
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116601433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl kmgr_tl_errors.4116601433
Directory	/workspace/15.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.926000339
Short name	T871
Test name
Test status
Simulation time	88688332 ps
CPU time	1.14 seconds
Started	Apr 18 01:30:53 PM PDT 24
Finished	Apr 18 01:30:59 PM PDT 24
Peak memory	200360 kb
Host	smart-1f9abc82-a94e-450d-b647-b9a8f3c08535
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926000339 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.926000339
Directory	/workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.962557495
Short name	T894
Test name
Test status
Simulation time	34538288 ps
CPU time	0.87 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:56 PM PDT 24
Peak memory	200468 kb
Host	smart-74d18344-1b80-49ce-bb3d-8053cdd78089
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962557495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. clkmgr_csr_rw.962557495
Directory	/workspace/16.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_intr_test.1453238390
Short name	T900
Test name
Test status
Simulation time	21885559 ps
CPU time	0.69 seconds
Started	Apr 18 01:30:53 PM PDT 24
Finished	Apr 18 01:30:59 PM PDT 24
Peak memory	199020 kb
Host	smart-f14a4f33-3ea4-42d0-b120-2eb44b07890b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453238390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl kmgr_intr_test.1453238390
Directory	/workspace/16.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.3948101126
Short name	T943
Test name
Test status
Simulation time	66828049 ps
CPU time	1.64 seconds
Started	Apr 18 01:30:54 PM PDT 24
Finished	Apr 18 01:31:01 PM PDT 24
Peak memory	200576 kb
Host	smart-7eba3f51-b9de-4521-9df3-7110ad1e7c73
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948101126 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 16.clkmgr_same_csr_outstanding.3948101126
Directory	/workspace/16.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2528716843
Short name	T993
Test name
Test status
Simulation time	120251657 ps
CPU time	2.03 seconds
Started	Apr 18 01:30:49 PM PDT 24
Finished	Apr 18 01:30:52 PM PDT 24
Peak memory	209320 kb
Host	smart-57ada95c-60c1-47b6-bc8b-47ee4a86012e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528716843 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 16.clkmgr_shadow_reg_errors.2528716843
Directory	/workspace/16.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.151163823
Short name	T944
Test name
Test status
Simulation time	129048882 ps
CPU time	2.7 seconds
Started	Apr 18 01:30:50 PM PDT 24
Finished	Apr 18 01:30:55 PM PDT 24
Peak memory	217420 kb
Host	smart-8cde6cd0-9e52-42f8-a605-c2edef71bd9d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151163823 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.151163823
Directory	/workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.1079266351
Short name	T874
Test name
Test status
Simulation time	346660072 ps
CPU time	2.97 seconds
Started	Apr 18 01:30:54 PM PDT 24
Finished	Apr 18 01:31:02 PM PDT 24
Peak memory	200704 kb
Host	smart-f33461f1-ade5-417e-9631-b3a02b36bae8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079266351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl kmgr_tl_errors.1079266351
Directory	/workspace/16.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.1080283022
Short name	T157
Test name
Test status
Simulation time	67596802 ps
CPU time	1.74 seconds
Started	Apr 18 01:30:49 PM PDT 24
Finished	Apr 18 01:30:53 PM PDT 24
Peak memory	200684 kb
Host	smart-b0e54790-0b8f-4bb8-8e72-a0f103d38b09
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080283022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 16.clkmgr_tl_intg_err.1080283022
Directory	/workspace/16.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.733404664
Short name	T994
Test name
Test status
Simulation time	63760191 ps
CPU time	1.58 seconds
Started	Apr 18 01:30:53 PM PDT 24
Finished	Apr 18 01:30:59 PM PDT 24
Peak memory	200772 kb
Host	smart-c973e485-b15f-4af5-a34c-f72e36e92749
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733404664 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.733404664
Directory	/workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.465466648
Short name	T77
Test name
Test status
Simulation time	12697839 ps
CPU time	0.75 seconds
Started	Apr 18 01:30:50 PM PDT 24
Finished	Apr 18 01:30:53 PM PDT 24
Peak memory	200252 kb
Host	smart-280bca67-b350-4500-929d-dde183ab7f3a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465466648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. clkmgr_csr_rw.465466648
Directory	/workspace/17.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_intr_test.4215816882
Short name	T855
Test name
Test status
Simulation time	36443610 ps
CPU time	0.7 seconds
Started	Apr 18 01:30:54 PM PDT 24
Finished	Apr 18 01:31:00 PM PDT 24
Peak memory	199052 kb
Host	smart-0a55469d-4625-4b54-9c0b-47fc7abc5725
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215816882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl kmgr_intr_test.4215816882
Directory	/workspace/17.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.3015242652
Short name	T71
Test name
Test status
Simulation time	45087381 ps
CPU time	1.3 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:58 PM PDT 24
Peak memory	200680 kb
Host	smart-e0dfa46f-41d0-4a3c-af1e-6fadb48d6180
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015242652 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 17.clkmgr_same_csr_outstanding.3015242652
Directory	/workspace/17.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.1604949223
Short name	T51
Test name
Test status
Simulation time	65352336 ps
CPU time	1.26 seconds
Started	Apr 18 01:30:51 PM PDT 24
Finished	Apr 18 01:30:54 PM PDT 24
Peak memory	200924 kb
Host	smart-e572cb0a-489b-42db-9718-37586945220c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604949223 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 17.clkmgr_shadow_reg_errors.1604949223
Directory	/workspace/17.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.271448066
Short name	T937
Test name
Test status
Simulation time	161036869 ps
CPU time	2.84 seconds
Started	Apr 18 01:30:54 PM PDT 24
Finished	Apr 18 01:31:02 PM PDT 24
Peak memory	200656 kb
Host	smart-97b14812-043b-449d-b557-ef8e659fc2ca
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271448066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clk mgr_tl_errors.271448066
Directory	/workspace/17.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.2522437739
Short name	T989
Test name
Test status
Simulation time	125514045 ps
CPU time	1.91 seconds
Started	Apr 18 01:30:58 PM PDT 24
Finished	Apr 18 01:31:05 PM PDT 24
Peak memory	200684 kb
Host	smart-d1466467-cc61-4394-86f1-d8fde91e056b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522437739 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.2522437739
Directory	/workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.2463975436
Short name	T73
Test name
Test status
Simulation time	46782979 ps
CPU time	0.82 seconds
Started	Apr 18 01:30:57 PM PDT 24
Finished	Apr 18 01:31:03 PM PDT 24
Peak memory	200244 kb
Host	smart-096ea518-e596-417d-ba72-30e1c0651cca
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463975436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .clkmgr_csr_rw.2463975436
Directory	/workspace/18.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_intr_test.3193194431
Short name	T961
Test name
Test status
Simulation time	33731701 ps
CPU time	0.78 seconds
Started	Apr 18 01:30:49 PM PDT 24
Finished	Apr 18 01:30:52 PM PDT 24
Peak memory	198944 kb
Host	smart-35df405f-97ea-4626-846a-4b4e9b657ddc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193194431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl kmgr_intr_test.3193194431
Directory	/workspace/18.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.2923740995
Short name	T884
Test name
Test status
Simulation time	56418545 ps
CPU time	0.98 seconds
Started	Apr 18 01:30:57 PM PDT 24
Finished	Apr 18 01:31:03 PM PDT 24
Peak memory	200392 kb
Host	smart-a665f37f-64bc-4ac8-a8f3-82f8b1be82b5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923740995 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 18.clkmgr_same_csr_outstanding.2923740995
Directory	/workspace/18.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.1219489336
Short name	T55
Test name
Test status
Simulation time	150728214 ps
CPU time	2.56 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:58 PM PDT 24
Peak memory	201376 kb
Host	smart-06d7774e-f9cc-41c2-95f0-53a2e512ff06
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219489336 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.1219489336
Directory	/workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.1737730432
Short name	T866
Test name
Test status
Simulation time	47809636 ps
CPU time	1.68 seconds
Started	Apr 18 01:30:49 PM PDT 24
Finished	Apr 18 01:30:53 PM PDT 24
Peak memory	200736 kb
Host	smart-b6c484c4-5a23-4f3b-9b66-aa4f10a5744e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737730432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl kmgr_tl_errors.1737730432
Directory	/workspace/18.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.3362012622
Short name	T990
Test name
Test status
Simulation time	76853722 ps
CPU time	1.77 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:59 PM PDT 24
Peak memory	200656 kb
Host	smart-4e8eff74-495b-4318-b26a-80e076c45e68
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362012622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 18.clkmgr_tl_intg_err.3362012622
Directory	/workspace/18.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.1663607038
Short name	T880
Test name
Test status
Simulation time	35471329 ps
CPU time	1.2 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:58 PM PDT 24
Peak memory	200540 kb
Host	smart-fc275d1a-f792-49a3-9b8a-0c3018421dce
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663607038 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.1663607038
Directory	/workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.1215309566
Short name	T856
Test name
Test status
Simulation time	48633982 ps
CPU time	0.84 seconds
Started	Apr 18 01:30:51 PM PDT 24
Finished	Apr 18 01:30:56 PM PDT 24
Peak memory	200436 kb
Host	smart-90345908-006d-4e05-b053-1df1abaa827a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215309566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .clkmgr_csr_rw.1215309566
Directory	/workspace/19.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_intr_test.4083030745
Short name	T959
Test name
Test status
Simulation time	12751976 ps
CPU time	0.68 seconds
Started	Apr 18 01:30:50 PM PDT 24
Finished	Apr 18 01:30:54 PM PDT 24
Peak memory	198996 kb
Host	smart-5d17ab01-0612-4985-8664-c10ebf21d784
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083030745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl kmgr_intr_test.4083030745
Directory	/workspace/19.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.3937459118
Short name	T928
Test name
Test status
Simulation time	69960487 ps
CPU time	1.12 seconds
Started	Apr 18 01:30:54 PM PDT 24
Finished	Apr 18 01:31:00 PM PDT 24
Peak memory	200424 kb
Host	smart-b4ec2788-2d16-421e-8140-d3730bba4c32
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937459118 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 19.clkmgr_same_csr_outstanding.3937459118
Directory	/workspace/19.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.561768339
Short name	T888
Test name
Test status
Simulation time	461376173 ps
CPU time	3.08 seconds
Started	Apr 18 01:30:57 PM PDT 24
Finished	Apr 18 01:31:05 PM PDT 24
Peak memory	201124 kb
Host	smart-ae2827c2-56e9-474d-b9b9-31a075527623
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561768339 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.561768339
Directory	/workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.1020683570
Short name	T1002
Test name
Test status
Simulation time	194396459 ps
CPU time	3.54 seconds
Started	Apr 18 01:30:59 PM PDT 24
Finished	Apr 18 01:31:07 PM PDT 24
Peak memory	200644 kb
Host	smart-5ed2f5a2-9d5a-46de-a30b-fb76ccfd5978
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020683570 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl kmgr_tl_errors.1020683570
Directory	/workspace/19.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.196400837
Short name	T106
Test name
Test status
Simulation time	123458117 ps
CPU time	1.85 seconds
Started	Apr 18 01:30:51 PM PDT 24
Finished	Apr 18 01:30:55 PM PDT 24
Peak memory	200636 kb
Host	smart-f5979568-e4e2-47db-acc1-c77c1da97f37
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196400837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 19.clkmgr_tl_intg_err.196400837
Directory	/workspace/19.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.3092417146
Short name	T862
Test name
Test status
Simulation time	94324474 ps
CPU time	1.21 seconds
Started	Apr 18 01:30:35 PM PDT 24
Finished	Apr 18 01:30:37 PM PDT 24
Peak memory	200376 kb
Host	smart-b9c2688a-117a-49e1-a004-e01a8d51bc1b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092417146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.clkmgr_csr_aliasing.3092417146
Directory	/workspace/2.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.2909680291
Short name	T998
Test name
Test status
Simulation time	499103362 ps
CPU time	8.39 seconds
Started	Apr 18 01:30:41 PM PDT 24
Finished	Apr 18 01:30:50 PM PDT 24
Peak memory	200656 kb
Host	smart-4bdcaf21-7f5c-4f00-bedc-ac3852ca7ce7
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909680291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.clkmgr_csr_bit_bash.2909680291
Directory	/workspace/2.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.688327025
Short name	T914
Test name
Test status
Simulation time	29874720 ps
CPU time	0.85 seconds
Started	Apr 18 01:30:44 PM PDT 24
Finished	Apr 18 01:30:46 PM PDT 24
Peak memory	200296 kb
Host	smart-290cf860-3446-4bb6-90ca-eb33aac4ebc5
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688327025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 2.clkmgr_csr_hw_reset.688327025
Directory	/workspace/2.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.4037877497
Short name	T864
Test name
Test status
Simulation time	28441864 ps
CPU time	1.21 seconds
Started	Apr 18 01:30:45 PM PDT 24
Finished	Apr 18 01:30:47 PM PDT 24
Peak memory	200736 kb
Host	smart-6c0d5f04-5ee7-49a8-9c73-8d1619cb9abd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037877497 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.4037877497
Directory	/workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.2029808976
Short name	T72
Test name
Test status
Simulation time	22068764 ps
CPU time	0.83 seconds
Started	Apr 18 01:30:42 PM PDT 24
Finished	Apr 18 01:30:43 PM PDT 24
Peak memory	200448 kb
Host	smart-e049ac3b-703b-4b50-b5bf-80b243222ef6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029808976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. clkmgr_csr_rw.2029808976
Directory	/workspace/2.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_intr_test.987521514
Short name	T971
Test name
Test status
Simulation time	16877305 ps
CPU time	0.7 seconds
Started	Apr 18 01:30:49 PM PDT 24
Finished	Apr 18 01:30:50 PM PDT 24
Peak memory	199152 kb
Host	smart-e13e1158-87ba-4ae6-ae0f-d5182d102bc4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987521514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkm gr_intr_test.987521514
Directory	/workspace/2.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.4141841695
Short name	T948
Test name
Test status
Simulation time	33967537 ps
CPU time	1.19 seconds
Started	Apr 18 01:30:44 PM PDT 24
Finished	Apr 18 01:30:47 PM PDT 24
Peak memory	200424 kb
Host	smart-f36a998d-abb9-4c6f-8508-939252a669a3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141841695 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.clkmgr_same_csr_outstanding.4141841695
Directory	/workspace/2.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2625400699
Short name	T923
Test name
Test status
Simulation time	87581378 ps
CPU time	1.33 seconds
Started	Apr 18 01:30:42 PM PDT 24
Finished	Apr 18 01:30:44 PM PDT 24
Peak memory	200904 kb
Host	smart-0fd976c4-7704-4a3c-b717-7a49e9d4acf0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625400699 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 2.clkmgr_shadow_reg_errors.2625400699
Directory	/workspace/2.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.3385042358
Short name	T131
Test name
Test status
Simulation time	432192987 ps
CPU time	3.16 seconds
Started	Apr 18 01:30:49 PM PDT 24
Finished	Apr 18 01:30:53 PM PDT 24
Peak memory	201140 kb
Host	smart-3d60a2a3-af04-42bd-a0ca-807efdb032aa
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385042358 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.3385042358
Directory	/workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.391418496
Short name	T995
Test name
Test status
Simulation time	152202647 ps
CPU time	3.42 seconds
Started	Apr 18 01:30:31 PM PDT 24
Finished	Apr 18 01:30:35 PM PDT 24
Peak memory	200688 kb
Host	smart-682cff68-9b49-4a1f-8cec-075173891cc5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391418496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkm gr_tl_errors.391418496
Directory	/workspace/2.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.4079144810
Short name	T105
Test name
Test status
Simulation time	123733181 ps
CPU time	1.71 seconds
Started	Apr 18 01:30:47 PM PDT 24
Finished	Apr 18 01:30:50 PM PDT 24
Peak memory	200676 kb
Host	smart-8c6aeaf3-1d88-47a6-9e10-f3f019e5a8bf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079144810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 2.clkmgr_tl_intg_err.4079144810
Directory	/workspace/2.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.clkmgr_intr_test.3691127562
Short name	T859
Test name
Test status
Simulation time	29700589 ps
CPU time	0.73 seconds
Started	Apr 18 01:30:55 PM PDT 24
Finished	Apr 18 01:31:00 PM PDT 24
Peak memory	198924 kb
Host	smart-96c1ef22-a434-422d-9ee3-9dba738d96ac
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691127562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl kmgr_intr_test.3691127562
Directory	/workspace/20.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.clkmgr_intr_test.1118426340
Short name	T968
Test name
Test status
Simulation time	24195444 ps
CPU time	0.72 seconds
Started	Apr 18 01:30:58 PM PDT 24
Finished	Apr 18 01:31:04 PM PDT 24
Peak memory	198896 kb
Host	smart-1ed64f33-b3c9-4b2d-8818-f13cb59d96ec
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118426340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl kmgr_intr_test.1118426340
Directory	/workspace/21.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.clkmgr_intr_test.4032782837
Short name	T1003
Test name
Test status
Simulation time	16450165 ps
CPU time	0.7 seconds
Started	Apr 18 01:30:53 PM PDT 24
Finished	Apr 18 01:30:58 PM PDT 24
Peak memory	199016 kb
Host	smart-06ac05ae-b26d-47c4-9cd0-f4fc3c9ad937
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032782837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.cl kmgr_intr_test.4032782837
Directory	/workspace/22.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.clkmgr_intr_test.2537701981
Short name	T899
Test name
Test status
Simulation time	33783153 ps
CPU time	0.71 seconds
Started	Apr 18 01:30:48 PM PDT 24
Finished	Apr 18 01:30:50 PM PDT 24
Peak memory	198976 kb
Host	smart-647975f5-ca40-4aae-b8d9-3dd1fed821c5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537701981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.cl kmgr_intr_test.2537701981
Directory	/workspace/23.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.clkmgr_intr_test.241273541
Short name	T906
Test name
Test status
Simulation time	14546192 ps
CPU time	0.74 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:58 PM PDT 24
Peak memory	198960 kb
Host	smart-bdea0a48-058f-4569-a073-7ca2fdfe51e4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241273541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.clk mgr_intr_test.241273541
Directory	/workspace/24.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.clkmgr_intr_test.3415849932
Short name	T918
Test name
Test status
Simulation time	14158691 ps
CPU time	0.69 seconds
Started	Apr 18 01:31:00 PM PDT 24
Finished	Apr 18 01:31:05 PM PDT 24
Peak memory	198960 kb
Host	smart-33104d3a-89d0-4754-bdf2-776afc6176a5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415849932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.cl kmgr_intr_test.3415849932
Directory	/workspace/25.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.clkmgr_intr_test.3921636095
Short name	T949
Test name
Test status
Simulation time	41916412 ps
CPU time	0.77 seconds
Started	Apr 18 01:30:51 PM PDT 24
Finished	Apr 18 01:30:54 PM PDT 24
Peak memory	199048 kb
Host	smart-71145aaa-ba37-4624-bdad-93d9d5f1e37d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921636095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl kmgr_intr_test.3921636095
Directory	/workspace/26.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.clkmgr_intr_test.791521008
Short name	T892
Test name
Test status
Simulation time	14706164 ps
CPU time	0.71 seconds
Started	Apr 18 01:31:01 PM PDT 24
Finished	Apr 18 01:31:06 PM PDT 24
Peak memory	199032 kb
Host	smart-181be4c9-0c1a-4c09-a637-d8ce631fa5ef
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791521008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.clk mgr_intr_test.791521008
Directory	/workspace/27.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.clkmgr_intr_test.745055649
Short name	T849
Test name
Test status
Simulation time	19415383 ps
CPU time	0.67 seconds
Started	Apr 18 01:30:57 PM PDT 24
Finished	Apr 18 01:31:03 PM PDT 24
Peak memory	198740 kb
Host	smart-3429ca65-6878-4287-99e9-7ee37f691090
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745055649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.clk mgr_intr_test.745055649
Directory	/workspace/28.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.clkmgr_intr_test.3436693002
Short name	T1000
Test name
Test status
Simulation time	27586347 ps
CPU time	0.72 seconds
Started	Apr 18 01:30:55 PM PDT 24
Finished	Apr 18 01:31:01 PM PDT 24
Peak memory	199032 kb
Host	smart-9605bd5f-5370-41d9-ada9-7e2e2e1ffe79
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436693002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.cl kmgr_intr_test.3436693002
Directory	/workspace/29.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.305160277
Short name	T939
Test name
Test status
Simulation time	67273625 ps
CPU time	1.81 seconds
Started	Apr 18 01:30:47 PM PDT 24
Finished	Apr 18 01:30:50 PM PDT 24
Peak memory	200552 kb
Host	smart-43646658-c7a8-4a3d-a58f-13abfa643a16
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305160277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 3.clkmgr_csr_aliasing.305160277
Directory	/workspace/3.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.2765319874
Short name	T1004
Test name
Test status
Simulation time	360083411 ps
CPU time	6.35 seconds
Started	Apr 18 01:30:44 PM PDT 24
Finished	Apr 18 01:30:51 PM PDT 24
Peak memory	200672 kb
Host	smart-b9bd0ca3-f30f-4796-895a-73bca186aae8
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765319874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.clkmgr_csr_bit_bash.2765319874
Directory	/workspace/3.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.1289718911
Short name	T947
Test name
Test status
Simulation time	20381178 ps
CPU time	0.77 seconds
Started	Apr 18 01:30:53 PM PDT 24
Finished	Apr 18 01:30:59 PM PDT 24
Peak memory	200128 kb
Host	smart-2a958807-6dd3-4cac-8b3f-f42eaf6dee97
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289718911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.clkmgr_csr_hw_reset.1289718911
Directory	/workspace/3.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.4183376922
Short name	T981
Test name
Test status
Simulation time	32632256 ps
CPU time	1.09 seconds
Started	Apr 18 01:30:53 PM PDT 24
Finished	Apr 18 01:30:59 PM PDT 24
Peak memory	200472 kb
Host	smart-e444e7fa-16d1-4a91-ac63-96008ae31439
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183376922 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.4183376922
Directory	/workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.221659961
Short name	T1010
Test name
Test status
Simulation time	22543747 ps
CPU time	0.76 seconds
Started	Apr 18 01:30:39 PM PDT 24
Finished	Apr 18 01:30:40 PM PDT 24
Peak memory	200408 kb
Host	smart-35ab441e-326a-40d7-86f0-f02f28fe7e65
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221659961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.c lkmgr_csr_rw.221659961
Directory	/workspace/3.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_intr_test.1816393353
Short name	T898
Test name
Test status
Simulation time	31757629 ps
CPU time	0.71 seconds
Started	Apr 18 01:30:28 PM PDT 24
Finished	Apr 18 01:30:29 PM PDT 24
Peak memory	198948 kb
Host	smart-9d16aa4e-d08c-4d9f-98bc-db7295feb305
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816393353 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk mgr_intr_test.1816393353
Directory	/workspace/3.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.3422149596
Short name	T870
Test name
Test status
Simulation time	86972008 ps
CPU time	1.31 seconds
Started	Apr 18 01:30:41 PM PDT 24
Finished	Apr 18 01:30:43 PM PDT 24
Peak memory	200480 kb
Host	smart-9e46284a-52f8-4f19-884a-1262c5436381
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422149596 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.clkmgr_same_csr_outstanding.3422149596
Directory	/workspace/3.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3970471758
Short name	T123
Test name
Test status
Simulation time	391105448 ps
CPU time	2.35 seconds
Started	Apr 18 01:30:39 PM PDT 24
Finished	Apr 18 01:30:42 PM PDT 24
Peak memory	209320 kb
Host	smart-9d184f63-521d-4f81-86fd-7bf38c5b3c94
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970471758 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 3.clkmgr_shadow_reg_errors.3970471758
Directory	/workspace/3.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.1280391165
Short name	T913
Test name
Test status
Simulation time	79948525 ps
CPU time	1.79 seconds
Started	Apr 18 01:30:53 PM PDT 24
Finished	Apr 18 01:31:00 PM PDT 24
Peak memory	209316 kb
Host	smart-9636fbd6-50ef-4b7f-a091-5031b2f69c1c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280391165 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.1280391165
Directory	/workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.1671463081
Short name	T942
Test name
Test status
Simulation time	331554954 ps
CPU time	3.08 seconds
Started	Apr 18 01:30:44 PM PDT 24
Finished	Apr 18 01:30:48 PM PDT 24
Peak memory	200772 kb
Host	smart-3974be04-9769-462a-88e9-c14a2d011931
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671463081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk mgr_tl_errors.1671463081
Directory	/workspace/3.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.2432376472
Short name	T103
Test name
Test status
Simulation time	93081862 ps
CPU time	2.17 seconds
Started	Apr 18 01:30:56 PM PDT 24
Finished	Apr 18 01:31:03 PM PDT 24
Peak memory	200724 kb
Host	smart-d12eea3b-fe92-47c2-bef1-94dc24900e68
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432376472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 3.clkmgr_tl_intg_err.2432376472
Directory	/workspace/3.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.clkmgr_intr_test.795838172
Short name	T965
Test name
Test status
Simulation time	10787204 ps
CPU time	0.63 seconds
Started	Apr 18 01:30:57 PM PDT 24
Finished	Apr 18 01:31:02 PM PDT 24
Peak memory	198892 kb
Host	smart-09ec2c75-7b01-45f6-969c-7db12d449ed6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795838172 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.clk mgr_intr_test.795838172
Directory	/workspace/30.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.clkmgr_intr_test.464342449
Short name	T935
Test name
Test status
Simulation time	22851850 ps
CPU time	0.7 seconds
Started	Apr 18 01:30:58 PM PDT 24
Finished	Apr 18 01:31:04 PM PDT 24
Peak memory	198964 kb
Host	smart-6bbd0bbf-d845-476b-a78a-436c0dec0654
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464342449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.clk mgr_intr_test.464342449
Directory	/workspace/31.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.clkmgr_intr_test.2430018841
Short name	T985
Test name
Test status
Simulation time	49748013 ps
CPU time	0.78 seconds
Started	Apr 18 01:30:54 PM PDT 24
Finished	Apr 18 01:31:00 PM PDT 24
Peak memory	198952 kb
Host	smart-caa64edd-8e7c-4484-8f98-c9afa9892a12
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430018841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.cl kmgr_intr_test.2430018841
Directory	/workspace/32.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.clkmgr_intr_test.1917289312
Short name	T977
Test name
Test status
Simulation time	14828146 ps
CPU time	0.7 seconds
Started	Apr 18 01:31:01 PM PDT 24
Finished	Apr 18 01:31:05 PM PDT 24
Peak memory	199032 kb
Host	smart-cd82f80a-9c6c-48fd-b44d-50dc5c1b9cba
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917289312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl kmgr_intr_test.1917289312
Directory	/workspace/33.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.clkmgr_intr_test.1504168160
Short name	T876
Test name
Test status
Simulation time	12532595 ps
CPU time	0.66 seconds
Started	Apr 18 01:30:54 PM PDT 24
Finished	Apr 18 01:31:00 PM PDT 24
Peak memory	198952 kb
Host	smart-4b72595a-b63c-4bdc-a088-9c3e3bd48fb4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504168160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.cl kmgr_intr_test.1504168160
Directory	/workspace/34.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.clkmgr_intr_test.676694531
Short name	T853
Test name
Test status
Simulation time	25139642 ps
CPU time	0.67 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:58 PM PDT 24
Peak memory	199024 kb
Host	smart-cf7d5c51-ec02-4709-94b6-9b15a96b1cec
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676694531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.clk mgr_intr_test.676694531
Directory	/workspace/35.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.clkmgr_intr_test.3794993735
Short name	T903
Test name
Test status
Simulation time	20245869 ps
CPU time	0.66 seconds
Started	Apr 18 01:30:53 PM PDT 24
Finished	Apr 18 01:30:58 PM PDT 24
Peak memory	198968 kb
Host	smart-6683ba92-72d0-4a87-a9de-74a67e8527bc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794993735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl kmgr_intr_test.3794993735
Directory	/workspace/36.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.clkmgr_intr_test.3683586129
Short name	T983
Test name
Test status
Simulation time	132835671 ps
CPU time	0.9 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:57 PM PDT 24
Peak memory	199024 kb
Host	smart-260156b8-5eb8-43ae-8240-6d27daf02239
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683586129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.cl kmgr_intr_test.3683586129
Directory	/workspace/37.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.clkmgr_intr_test.1906144497
Short name	T987
Test name
Test status
Simulation time	25951640 ps
CPU time	0.77 seconds
Started	Apr 18 01:30:53 PM PDT 24
Finished	Apr 18 01:30:59 PM PDT 24
Peak memory	198960 kb
Host	smart-62fe14aa-f2e5-4d4a-8078-56089e71fdbd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906144497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl kmgr_intr_test.1906144497
Directory	/workspace/38.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.clkmgr_intr_test.402108441
Short name	T999
Test name
Test status
Simulation time	12899649 ps
CPU time	0.67 seconds
Started	Apr 18 01:30:54 PM PDT 24
Finished	Apr 18 01:31:00 PM PDT 24
Peak memory	198944 kb
Host	smart-d28ffb83-2eea-416f-aaae-e2699aac366b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402108441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.clk mgr_intr_test.402108441
Directory	/workspace/39.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3356880675
Short name	T950
Test name
Test status
Simulation time	209680572 ps
CPU time	2.13 seconds
Started	Apr 18 01:30:38 PM PDT 24
Finished	Apr 18 01:30:41 PM PDT 24
Peak memory	200624 kb
Host	smart-56205130-b742-4f82-9eee-71aaad2f128a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356880675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.clkmgr_csr_aliasing.3356880675
Directory	/workspace/4.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.581366065
Short name	T962
Test name
Test status
Simulation time	211948748 ps
CPU time	3.58 seconds
Started	Apr 18 01:30:37 PM PDT 24
Finished	Apr 18 01:30:41 PM PDT 24
Peak memory	200680 kb
Host	smart-bf5f651f-2611-477f-a923-7fb724a55e56
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581366065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 4.clkmgr_csr_bit_bash.581366065
Directory	/workspace/4.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.3384716038
Short name	T931
Test name
Test status
Simulation time	27495364 ps
CPU time	0.83 seconds
Started	Apr 18 01:30:45 PM PDT 24
Finished	Apr 18 01:30:46 PM PDT 24
Peak memory	200388 kb
Host	smart-02b270e9-ede2-408d-b961-42f6b4d3c14f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384716038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.clkmgr_csr_hw_reset.3384716038
Directory	/workspace/4.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.519269812
Short name	T951
Test name
Test status
Simulation time	183014928 ps
CPU time	1.55 seconds
Started	Apr 18 01:30:44 PM PDT 24
Finished	Apr 18 01:30:46 PM PDT 24
Peak memory	200568 kb
Host	smart-f8587764-8e0e-45a8-ab41-1e8b204e3db3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519269812 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.519269812
Directory	/workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.1314464774
Short name	T945
Test name
Test status
Simulation time	18051999 ps
CPU time	0.81 seconds
Started	Apr 18 01:30:47 PM PDT 24
Finished	Apr 18 01:30:49 PM PDT 24
Peak memory	200376 kb
Host	smart-d0c8e9a1-e0cb-4c42-8b2c-79b9dc5120c0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314464774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. clkmgr_csr_rw.1314464774
Directory	/workspace/4.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_intr_test.2046071615
Short name	T1008
Test name
Test status
Simulation time	14608914 ps
CPU time	0.66 seconds
Started	Apr 18 01:30:51 PM PDT 24
Finished	Apr 18 01:30:55 PM PDT 24
Peak memory	198928 kb
Host	smart-1aa761d0-230c-4ea7-956f-65121b85c894
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046071615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk mgr_intr_test.2046071615
Directory	/workspace/4.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2407698706
Short name	T893
Test name
Test status
Simulation time	193347126 ps
CPU time	1.78 seconds
Started	Apr 18 01:30:46 PM PDT 24
Finished	Apr 18 01:30:48 PM PDT 24
Peak memory	200684 kb
Host	smart-665243cb-e582-4aa5-aacb-d791d5bffa12
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407698706 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.clkmgr_same_csr_outstanding.2407698706
Directory	/workspace/4.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.2670440105
Short name	T922
Test name
Test status
Simulation time	528090663 ps
CPU time	2.73 seconds
Started	Apr 18 01:30:48 PM PDT 24
Finished	Apr 18 01:30:51 PM PDT 24
Peak memory	209336 kb
Host	smart-f368b1fd-e8a1-4319-b076-7755da970983
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670440105 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 4.clkmgr_shadow_reg_errors.2670440105
Directory	/workspace/4.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.3115563565
Short name	T997
Test name
Test status
Simulation time	286717607 ps
CPU time	2.23 seconds
Started	Apr 18 01:30:40 PM PDT 24
Finished	Apr 18 01:30:43 PM PDT 24
Peak memory	209164 kb
Host	smart-0d520234-dc8c-4fa3-b960-5570b1b7987c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115563565 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.3115563565
Directory	/workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.1698377154
Short name	T924
Test name
Test status
Simulation time	203304873 ps
CPU time	2.25 seconds
Started	Apr 18 01:30:49 PM PDT 24
Finished	Apr 18 01:30:52 PM PDT 24
Peak memory	200724 kb
Host	smart-efc17197-db4a-45d9-9013-87c4099e00cf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698377154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk mgr_tl_errors.1698377154
Directory	/workspace/4.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.2046427622
Short name	T96
Test name
Test status
Simulation time	53470014 ps
CPU time	1.53 seconds
Started	Apr 18 01:30:46 PM PDT 24
Finished	Apr 18 01:30:48 PM PDT 24
Peak memory	200704 kb
Host	smart-fba05e4f-30fe-435c-92c9-f16a4fd879f6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046427622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 4.clkmgr_tl_intg_err.2046427622
Directory	/workspace/4.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.clkmgr_intr_test.150593837
Short name	T890
Test name
Test status
Simulation time	31353674 ps
CPU time	0.68 seconds
Started	Apr 18 01:30:54 PM PDT 24
Finished	Apr 18 01:31:00 PM PDT 24
Peak memory	198924 kb
Host	smart-cd7f852a-892a-4694-a38c-0b0668413a80
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150593837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.clk mgr_intr_test.150593837
Directory	/workspace/40.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2906375843
Short name	T878
Test name
Test status
Simulation time	12712129 ps
CPU time	0.64 seconds
Started	Apr 18 01:30:54 PM PDT 24
Finished	Apr 18 01:31:00 PM PDT 24
Peak memory	198980 kb
Host	smart-635755a9-3fd1-4b6d-9923-5ef29627173a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906375843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.cl kmgr_intr_test.2906375843
Directory	/workspace/41.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.clkmgr_intr_test.2293732354
Short name	T972
Test name
Test status
Simulation time	13126361 ps
CPU time	0.65 seconds
Started	Apr 18 01:30:53 PM PDT 24
Finished	Apr 18 01:30:59 PM PDT 24
Peak memory	198876 kb
Host	smart-6b91f5d7-1405-467a-96f4-408c3a483529
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293732354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl kmgr_intr_test.2293732354
Directory	/workspace/42.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.clkmgr_intr_test.2310688081
Short name	T881
Test name
Test status
Simulation time	11867659 ps
CPU time	0.67 seconds
Started	Apr 18 01:30:50 PM PDT 24
Finished	Apr 18 01:30:52 PM PDT 24
Peak memory	198944 kb
Host	smart-9891ba34-0535-4f95-9fb1-c7246d9be8af
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310688081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl kmgr_intr_test.2310688081
Directory	/workspace/43.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.clkmgr_intr_test.1731574434
Short name	T991
Test name
Test status
Simulation time	15638117 ps
CPU time	0.71 seconds
Started	Apr 18 01:30:47 PM PDT 24
Finished	Apr 18 01:30:49 PM PDT 24
Peak memory	198888 kb
Host	smart-3df02aa9-d69a-4ee9-b5aa-1269cb407561
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731574434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl kmgr_intr_test.1731574434
Directory	/workspace/44.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.clkmgr_intr_test.2021948148
Short name	T973
Test name
Test status
Simulation time	36713374 ps
CPU time	0.74 seconds
Started	Apr 18 01:30:55 PM PDT 24
Finished	Apr 18 01:31:01 PM PDT 24
Peak memory	198952 kb
Host	smart-78681f10-fb03-4948-a5a5-649ed750641a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021948148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl kmgr_intr_test.2021948148
Directory	/workspace/45.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.clkmgr_intr_test.2113189405
Short name	T872
Test name
Test status
Simulation time	12621821 ps
CPU time	0.68 seconds
Started	Apr 18 01:30:48 PM PDT 24
Finished	Apr 18 01:30:49 PM PDT 24
Peak memory	198888 kb
Host	smart-ba83d7a1-7cf4-4b7b-981c-91399656fde9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113189405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl kmgr_intr_test.2113189405
Directory	/workspace/46.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.clkmgr_intr_test.2372138683
Short name	T885
Test name
Test status
Simulation time	36007680 ps
CPU time	0.74 seconds
Started	Apr 18 01:31:01 PM PDT 24
Finished	Apr 18 01:31:06 PM PDT 24
Peak memory	198964 kb
Host	smart-c5f764fc-81a9-4e9a-9995-b8d2aae2b571
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372138683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.cl kmgr_intr_test.2372138683
Directory	/workspace/47.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.clkmgr_intr_test.1201035320
Short name	T954
Test name
Test status
Simulation time	41428243 ps
CPU time	0.72 seconds
Started	Apr 18 01:30:45 PM PDT 24
Finished	Apr 18 01:30:47 PM PDT 24
Peak memory	198948 kb
Host	smart-e7881e90-e6a7-4ed6-8513-994f41c54b19
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201035320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.cl kmgr_intr_test.1201035320
Directory	/workspace/48.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.clkmgr_intr_test.227452213
Short name	T926
Test name
Test status
Simulation time	18665474 ps
CPU time	0.74 seconds
Started	Apr 18 01:30:46 PM PDT 24
Finished	Apr 18 01:30:48 PM PDT 24
Peak memory	198948 kb
Host	smart-260876f0-53c6-4761-a9dd-60c378c31e08
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227452213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.clk mgr_intr_test.227452213
Directory	/workspace/49.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1308728155
Short name	T863
Test name
Test status
Simulation time	42517518 ps
CPU time	1.32 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:58 PM PDT 24
Peak memory	200748 kb
Host	smart-6bbcd11f-461f-4097-9348-9ea42d53a321
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308728155 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.1308728155
Directory	/workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.1246815894
Short name	T992
Test name
Test status
Simulation time	55846165 ps
CPU time	0.84 seconds
Started	Apr 18 01:30:42 PM PDT 24
Finished	Apr 18 01:30:44 PM PDT 24
Peak memory	200440 kb
Host	smart-fce968d3-ea86-44b3-bd6e-7f3391e97e02
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246815894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. clkmgr_csr_rw.1246815894
Directory	/workspace/5.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_intr_test.2103939221
Short name	T902
Test name
Test status
Simulation time	14942089 ps
CPU time	0.67 seconds
Started	Apr 18 01:30:39 PM PDT 24
Finished	Apr 18 01:30:40 PM PDT 24
Peak memory	198820 kb
Host	smart-ec1e407e-eb4a-4507-ac97-c8db4714d140
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103939221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk mgr_intr_test.2103939221
Directory	/workspace/5.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.2260182796
Short name	T1009
Test name
Test status
Simulation time	89660151 ps
CPU time	1.27 seconds
Started	Apr 18 01:30:45 PM PDT 24
Finished	Apr 18 01:30:47 PM PDT 24
Peak memory	200336 kb
Host	smart-5e75e09f-6ddd-4a98-aebe-07a0525f1743
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260182796 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.clkmgr_same_csr_outstanding.2260182796
Directory	/workspace/5.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.4062626551
Short name	T919
Test name
Test status
Simulation time	74081491 ps
CPU time	1.42 seconds
Started	Apr 18 01:30:41 PM PDT 24
Finished	Apr 18 01:30:43 PM PDT 24
Peak memory	200888 kb
Host	smart-6017bafe-2586-46db-9c51-8e5c57a17d1b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062626551 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 5.clkmgr_shadow_reg_errors.4062626551
Directory	/workspace/5.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.2362376741
Short name	T886
Test name
Test status
Simulation time	139106768 ps
CPU time	1.65 seconds
Started	Apr 18 01:30:51 PM PDT 24
Finished	Apr 18 01:30:55 PM PDT 24
Peak memory	201148 kb
Host	smart-82790fc2-1083-4c95-8896-3ed674a72caf
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362376741 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.2362376741
Directory	/workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.945261542
Short name	T896
Test name
Test status
Simulation time	45573873 ps
CPU time	2.68 seconds
Started	Apr 18 01:30:44 PM PDT 24
Finished	Apr 18 01:30:48 PM PDT 24
Peak memory	200748 kb
Host	smart-0628dede-492f-4430-8771-780fead6973f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945261542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkm gr_tl_errors.945261542
Directory	/workspace/5.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.2348523420
Short name	T869
Test name
Test status
Simulation time	23617863 ps
CPU time	1.25 seconds
Started	Apr 18 01:30:49 PM PDT 24
Finished	Apr 18 01:30:51 PM PDT 24
Peak memory	200528 kb
Host	smart-b5bc7762-4c35-45d2-95f5-f51a55207698
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348523420 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.2348523420
Directory	/workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.1762943970
Short name	T963
Test name
Test status
Simulation time	15305156 ps
CPU time	0.72 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:56 PM PDT 24
Peak memory	200464 kb
Host	smart-3e992e67-7ae9-4b5d-8a08-40ee01343a63
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762943970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. clkmgr_csr_rw.1762943970
Directory	/workspace/6.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_intr_test.1556308729
Short name	T975
Test name
Test status
Simulation time	36597013 ps
CPU time	0.73 seconds
Started	Apr 18 01:30:49 PM PDT 24
Finished	Apr 18 01:30:52 PM PDT 24
Peak memory	198940 kb
Host	smart-74493bf8-fa81-4931-bd8f-cddc8223ea75
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556308729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk mgr_intr_test.1556308729
Directory	/workspace/6.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.2879794487
Short name	T970
Test name
Test status
Simulation time	66966133 ps
CPU time	1.06 seconds
Started	Apr 18 01:30:48 PM PDT 24
Finished	Apr 18 01:30:50 PM PDT 24
Peak memory	200352 kb
Host	smart-238b4ee3-ade7-4b0c-a066-a8e1b50ca4ef
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879794487 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.clkmgr_same_csr_outstanding.2879794487
Directory	/workspace/6.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1741506821
Short name	T933
Test name
Test status
Simulation time	467632819 ps
CPU time	2.3 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:59 PM PDT 24
Peak memory	200780 kb
Host	smart-46cf469e-0132-4f1e-88c8-d363e30a30dd
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741506821 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 6.clkmgr_shadow_reg_errors.1741506821
Directory	/workspace/6.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.3209132284
Short name	T986
Test name
Test status
Simulation time	816871413 ps
CPU time	4.22 seconds
Started	Apr 18 01:30:44 PM PDT 24
Finished	Apr 18 01:30:49 PM PDT 24
Peak memory	209348 kb
Host	smart-3530d135-9703-48c8-9b2a-bde4ec48d93a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209132284 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.3209132284
Directory	/workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.1127135807
Short name	T930
Test name
Test status
Simulation time	81694087 ps
CPU time	2.12 seconds
Started	Apr 18 01:30:44 PM PDT 24
Finished	Apr 18 01:30:47 PM PDT 24
Peak memory	200720 kb
Host	smart-be539d9f-55d9-4c1c-a06b-abd66acf87e3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127135807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk mgr_tl_errors.1127135807
Directory	/workspace/6.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.3790372830
Short name	T158
Test name
Test status
Simulation time	100263194 ps
CPU time	2.36 seconds
Started	Apr 18 01:30:54 PM PDT 24
Finished	Apr 18 01:31:02 PM PDT 24
Peak memory	200644 kb
Host	smart-1212a23a-3c19-4735-bbad-a82456995995
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790372830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 6.clkmgr_tl_intg_err.3790372830
Directory	/workspace/6.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1049176298
Short name	T912
Test name
Test status
Simulation time	32598655 ps
CPU time	1.47 seconds
Started	Apr 18 01:30:48 PM PDT 24
Finished	Apr 18 01:30:51 PM PDT 24
Peak memory	200736 kb
Host	smart-3b9e2e78-40f4-444e-88aa-fa676399dd9a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049176298 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.1049176298
Directory	/workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.1685248443
Short name	T882
Test name
Test status
Simulation time	15098599 ps
CPU time	0.71 seconds
Started	Apr 18 01:30:50 PM PDT 24
Finished	Apr 18 01:30:52 PM PDT 24
Peak memory	200452 kb
Host	smart-9d1d9029-ecb4-45a0-83c8-12cd0ae19af5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685248443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7. clkmgr_csr_rw.1685248443
Directory	/workspace/7.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_intr_test.657439906
Short name	T905
Test name
Test status
Simulation time	19019202 ps
CPU time	0.66 seconds
Started	Apr 18 01:30:42 PM PDT 24
Finished	Apr 18 01:30:44 PM PDT 24
Peak memory	198804 kb
Host	smart-92baaddd-b1cb-4119-bbde-da00eac0c495
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657439906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkm gr_intr_test.657439906
Directory	/workspace/7.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.3901242863
Short name	T897
Test name
Test status
Simulation time	29790421 ps
CPU time	0.98 seconds
Started	Apr 18 01:30:51 PM PDT 24
Finished	Apr 18 01:30:56 PM PDT 24
Peak memory	200472 kb
Host	smart-05ff4aa1-42d7-4bc1-bca1-e3d9240ba629
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901242863 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.clkmgr_same_csr_outstanding.3901242863
Directory	/workspace/7.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.1403327699
Short name	T53
Test name
Test status
Simulation time	61152815 ps
CPU time	1.28 seconds
Started	Apr 18 01:30:45 PM PDT 24
Finished	Apr 18 01:30:47 PM PDT 24
Peak memory	200908 kb
Host	smart-66d38dba-6fca-4564-945f-98763eca5546
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403327699 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 7.clkmgr_shadow_reg_errors.1403327699
Directory	/workspace/7.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.2516584416
Short name	T979
Test name
Test status
Simulation time	137338075 ps
CPU time	2.8 seconds
Started	Apr 18 01:30:49 PM PDT 24
Finished	Apr 18 01:30:54 PM PDT 24
Peak memory	201240 kb
Host	smart-61f6d5a5-cde0-4168-995c-5a562596d6e6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516584416 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.2516584416
Directory	/workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.501551680
Short name	T879
Test name
Test status
Simulation time	98099599 ps
CPU time	2.79 seconds
Started	Apr 18 01:30:54 PM PDT 24
Finished	Apr 18 01:31:02 PM PDT 24
Peak memory	200776 kb
Host	smart-0d2fec2d-a550-4298-abbd-e6b8d2715274
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501551680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkm gr_tl_errors.501551680
Directory	/workspace/7.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.2877138926
Short name	T952
Test name
Test status
Simulation time	271938837 ps
CPU time	2.81 seconds
Started	Apr 18 01:30:58 PM PDT 24
Finished	Apr 18 01:31:05 PM PDT 24
Peak memory	200704 kb
Host	smart-09a6ed8e-3457-4ef3-a278-34675e8376d6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877138926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 7.clkmgr_tl_intg_err.2877138926
Directory	/workspace/7.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.2942490902
Short name	T851
Test name
Test status
Simulation time	141818432 ps
CPU time	1.66 seconds
Started	Apr 18 01:30:49 PM PDT 24
Finished	Apr 18 01:30:52 PM PDT 24
Peak memory	200732 kb
Host	smart-b5ec1097-ccea-47b2-9b16-ec42766d5a2a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942490902 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.2942490902
Directory	/workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.942565038
Short name	T889
Test name
Test status
Simulation time	21165641 ps
CPU time	0.74 seconds
Started	Apr 18 01:30:53 PM PDT 24
Finished	Apr 18 01:30:59 PM PDT 24
Peak memory	200452 kb
Host	smart-23811591-15d4-4467-a89c-a0d18bdd42a6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942565038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.c lkmgr_csr_rw.942565038
Directory	/workspace/8.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_intr_test.1350312385
Short name	T956
Test name
Test status
Simulation time	26732723 ps
CPU time	0.73 seconds
Started	Apr 18 01:30:49 PM PDT 24
Finished	Apr 18 01:30:51 PM PDT 24
Peak memory	198952 kb
Host	smart-f310231e-8c82-4cde-a0ff-e0c1861092e8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350312385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk mgr_intr_test.1350312385
Directory	/workspace/8.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.3174094276
Short name	T984
Test name
Test status
Simulation time	65209115 ps
CPU time	1.37 seconds
Started	Apr 18 01:30:51 PM PDT 24
Finished	Apr 18 01:30:55 PM PDT 24
Peak memory	200576 kb
Host	smart-6e691d32-8ed8-4794-b85e-779f37e3f0e4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174094276 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.clkmgr_same_csr_outstanding.3174094276
Directory	/workspace/8.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.2356965680
Short name	T56
Test name
Test status
Simulation time	184939313 ps
CPU time	1.64 seconds
Started	Apr 18 01:30:46 PM PDT 24
Finished	Apr 18 01:30:49 PM PDT 24
Peak memory	200916 kb
Host	smart-fd87c040-d9ff-4fbf-b0ca-3cd59e9b6f73
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356965680 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 8.clkmgr_shadow_reg_errors.2356965680
Directory	/workspace/8.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.3523957849
Short name	T48
Test name
Test status
Simulation time	77887270 ps
CPU time	1.82 seconds
Started	Apr 18 01:30:51 PM PDT 24
Finished	Apr 18 01:30:55 PM PDT 24
Peak memory	217484 kb
Host	smart-13f3acb9-aad8-404a-b2e8-714554290918
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523957849 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.3523957849
Directory	/workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.3080058483
Short name	T978
Test name
Test status
Simulation time	81552269 ps
CPU time	1.7 seconds
Started	Apr 18 01:30:42 PM PDT 24
Finished	Apr 18 01:30:45 PM PDT 24
Peak memory	200700 kb
Host	smart-6b54c582-e26e-405c-bb16-73c44cbcf22d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080058483 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk mgr_tl_errors.3080058483
Directory	/workspace/8.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.1913559077
Short name	T908
Test name
Test status
Simulation time	66843288 ps
CPU time	1.65 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:58 PM PDT 24
Peak memory	200600 kb
Host	smart-89428201-4d89-4c71-a79c-e70d4d74f2d5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913559077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 8.clkmgr_tl_intg_err.1913559077
Directory	/workspace/8.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.2951210372
Short name	T861
Test name
Test status
Simulation time	43995059 ps
CPU time	1.34 seconds
Started	Apr 18 01:30:45 PM PDT 24
Finished	Apr 18 01:30:47 PM PDT 24
Peak memory	200464 kb
Host	smart-831afa34-6ebc-4dd0-8e73-c49852779512
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951210372 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.2951210372
Directory	/workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3218458492
Short name	T901
Test name
Test status
Simulation time	64019348 ps
CPU time	0.97 seconds
Started	Apr 18 01:30:52 PM PDT 24
Finished	Apr 18 01:30:56 PM PDT 24
Peak memory	200324 kb
Host	smart-8e17a070-815f-4442-957f-f0dec6080794
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218458492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. clkmgr_csr_rw.3218458492
Directory	/workspace/9.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_intr_test.67540951
Short name	T860
Test name
Test status
Simulation time	35477844 ps
CPU time	0.78 seconds
Started	Apr 18 01:30:46 PM PDT 24
Finished	Apr 18 01:30:48 PM PDT 24
Peak memory	198996 kb
Host	smart-7129bc91-a1c4-4d61-aab7-eca4b2886056
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67540951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ =clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmg r_intr_test.67540951
Directory	/workspace/9.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.1780116073
Short name	T74
Test name
Test status
Simulation time	54767234 ps
CPU time	1.51 seconds
Started	Apr 18 01:30:55 PM PDT 24
Finished	Apr 18 01:31:02 PM PDT 24
Peak memory	200736 kb
Host	smart-7fec0e01-111d-45e6-936e-ee2d4c2e16a2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780116073 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.clkmgr_same_csr_outstanding.1780116073
Directory	/workspace/9.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.4052569949
Short name	T121
Test name
Test status
Simulation time	393800490 ps
CPU time	1.97 seconds
Started	Apr 18 01:30:44 PM PDT 24
Finished	Apr 18 01:30:47 PM PDT 24
Peak memory	200916 kb
Host	smart-c9f3a877-9f88-4841-ba79-dd2198b722a5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052569949 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 9.clkmgr_shadow_reg_errors.4052569949
Directory	/workspace/9.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.815535881
Short name	T904
Test name
Test status
Simulation time	1709581958 ps
CPU time	6.17 seconds
Started	Apr 18 01:30:47 PM PDT 24
Finished	Apr 18 01:30:54 PM PDT 24
Peak memory	217160 kb
Host	smart-315e3d53-618a-4f67-be14-5fa2f1f1c889
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815535881 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.815535881
Directory	/workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.3029519365
Short name	T932
Test name
Test status
Simulation time	825473600 ps
CPU time	5.22 seconds
Started	Apr 18 01:30:56 PM PDT 24
Finished	Apr 18 01:31:06 PM PDT 24
Peak memory	200712 kb
Host	smart-d213b2d7-64db-4655-bf36-66c25f825d4a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029519365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk mgr_tl_errors.3029519365
Directory	/workspace/9.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.488314991
Short name	T94
Test name
Test status
Simulation time	735721970 ps
CPU time	3.11 seconds
Started	Apr 18 01:30:49 PM PDT 24
Finished	Apr 18 01:30:53 PM PDT 24
Peak memory	200696 kb
Host	smart-c9cedd62-1554-472b-a2e4-4f7288875556
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488314991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 9.clkmgr_tl_intg_err.488314991
Directory	/workspace/9.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/0.clkmgr_alert_test.3614908432
Short name	T750
Test name
Test status
Simulation time	25210932 ps
CPU time	0.74 seconds
Started	Apr 18 01:31:46 PM PDT 24
Finished	Apr 18 01:31:50 PM PDT 24
Peak memory	200504 kb
Host	smart-e12f8348-7a65-4874-8881-5efb7dbccbaa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614908432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkm gr_alert_test.3614908432
Directory	/workspace/0.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.915942977
Short name	T587
Test name
Test status
Simulation time	97041881 ps
CPU time	1.07 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:52 PM PDT 24
Peak memory	200584 kb
Host	smart-ffd48556-277c-4f8d-861e-aad41c39d06b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915942977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_handshake_intersig_mubi.915942977
Directory	/workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_clk_status.1802692280
Short name	T400
Test name
Test status
Simulation time	41589301 ps
CPU time	0.75 seconds
Started	Apr 18 01:31:35 PM PDT 24
Finished	Apr 18 01:31:37 PM PDT 24
Peak memory	199528 kb
Host	smart-2aaf860b-4f42-427f-bb45-0f0e86ba58d1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802692280 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.1802692280
Directory	/workspace/0.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/0.clkmgr_div_intersig_mubi.377592523
Short name	T558
Test name
Test status
Simulation time	54279340 ps
CPU time	0.86 seconds
Started	Apr 18 01:31:38 PM PDT 24
Finished	Apr 18 01:31:40 PM PDT 24
Peak memory	200592 kb
Host	smart-65f9d038-9060-4618-916e-224dbe3c229c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377592523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .clkmgr_div_intersig_mubi.377592523
Directory	/workspace/0.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_extclk.2140852630
Short name	T721
Test name
Test status
Simulation time	29099507 ps
CPU time	0.95 seconds
Started	Apr 18 01:31:40 PM PDT 24
Finished	Apr 18 01:31:42 PM PDT 24
Peak memory	200600 kb
Host	smart-3a23bde7-87b4-4fc0-ba7a-ef1adfcb789a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140852630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.2140852630
Directory	/workspace/0.clkmgr_extclk/latest

Test location	/workspace/coverage/default/0.clkmgr_frequency.1868827554
Short name	T714
Test name
Test status
Simulation time	351976860 ps
CPU time	2.06 seconds
Started	Apr 18 01:31:43 PM PDT 24
Finished	Apr 18 01:31:47 PM PDT 24
Peak memory	200788 kb
Host	smart-e55ad4a9-0798-4a0a-b387-afeba114b846
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868827554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.1868827554
Directory	/workspace/0.clkmgr_frequency/latest

Test location	/workspace/coverage/default/0.clkmgr_frequency_timeout.3051555800
Short name	T703
Test name
Test status
Simulation time	1792013494 ps
CPU time	7.71 seconds
Started	Apr 18 01:31:37 PM PDT 24
Finished	Apr 18 01:31:45 PM PDT 24
Peak memory	200668 kb
Host	smart-b5f6484c-6d63-4a28-8b0e-17971ece973b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051555800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti meout.3051555800
Directory	/workspace/0.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/0.clkmgr_idle_intersig_mubi.4070446815
Short name	T431
Test name
Test status
Simulation time	95930583 ps
CPU time	1.23 seconds
Started	Apr 18 01:31:34 PM PDT 24
Finished	Apr 18 01:31:35 PM PDT 24
Peak memory	200436 kb
Host	smart-98459473-3e83-460b-9f37-8a7243d146d7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070446815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_idle_intersig_mubi.4070446815
Directory	/workspace/0.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.800831026
Short name	T257
Test name
Test status
Simulation time	23974309 ps
CPU time	0.85 seconds
Started	Apr 18 01:31:39 PM PDT 24
Finished	Apr 18 01:31:40 PM PDT 24
Peak memory	200568 kb
Host	smart-df664e93-a49c-4620-b504-d48b4f7323e9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800831026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.clkmgr_lc_clk_byp_req_intersig_mubi.800831026
Directory	/workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.1404217539
Short name	T405
Test name
Test status
Simulation time	328546040 ps
CPU time	1.68 seconds
Started	Apr 18 01:31:44 PM PDT 24
Finished	Apr 18 01:31:48 PM PDT 24
Peak memory	200620 kb
Host	smart-a406449d-a4c0-494e-a3fa-8a06ff8f3786
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404217539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.clkmgr_lc_ctrl_intersig_mubi.1404217539
Directory	/workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_peri.3983192956
Short name	T296
Test name
Test status
Simulation time	16478690 ps
CPU time	0.77 seconds
Started	Apr 18 01:31:43 PM PDT 24
Finished	Apr 18 01:31:46 PM PDT 24
Peak memory	200280 kb
Host	smart-d208522d-8bf9-45e7-a689-03eae6151830
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983192956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.3983192956
Directory	/workspace/0.clkmgr_peri/latest

Test location	/workspace/coverage/default/0.clkmgr_sec_cm.2928302399
Short name	T5
Test name
Test status
Simulation time	320084594 ps
CPU time	2.22 seconds
Started	Apr 18 01:31:36 PM PDT 24
Finished	Apr 18 01:31:38 PM PDT 24
Peak memory	215996 kb
Host	smart-7b8ad7a4-7d17-4569-8a64-2eba4f6c1149
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928302399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg r_sec_cm.2928302399
Directory	/workspace/0.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/0.clkmgr_smoke.1733646975
Short name	T566
Test name
Test status
Simulation time	27254477 ps
CPU time	0.82 seconds
Started	Apr 18 01:31:41 PM PDT 24
Finished	Apr 18 01:31:44 PM PDT 24
Peak memory	200548 kb
Host	smart-38bf3c4a-8f1d-4112-a488-a0b1422eff70
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733646975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.1733646975
Directory	/workspace/0.clkmgr_smoke/latest

Test location	/workspace/coverage/default/0.clkmgr_stress_all_with_rand_reset.2329351401
Short name	T266
Test name
Test status
Simulation time	86108705302 ps
CPU time	394.13 seconds
Started	Apr 18 01:31:42 PM PDT 24
Finished	Apr 18 01:38:18 PM PDT 24
Peak memory	209244 kb
Host	smart-f408ed32-f40f-421b-892e-98d601aa017e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2329351401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.2329351401
Directory	/workspace/0.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.clkmgr_trans.3560095025
Short name	T271
Test name
Test status
Simulation time	32321801 ps
CPU time	0.83 seconds
Started	Apr 18 01:31:36 PM PDT 24
Finished	Apr 18 01:31:37 PM PDT 24
Peak memory	200576 kb
Host	smart-2f8fc815-d45f-4b0d-9e48-51e691452079
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560095025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.3560095025
Directory	/workspace/0.clkmgr_trans/latest

Test location	/workspace/coverage/default/1.clkmgr_alert_test.2007586082
Short name	T408
Test name
Test status
Simulation time	49325737 ps
CPU time	0.82 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:52 PM PDT 24
Peak memory	200504 kb
Host	smart-6bd435bd-f787-41a4-a8d8-bd0403f7c589
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007586082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm gr_alert_test.2007586082
Directory	/workspace/1.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.4188466213
Short name	T521
Test name
Test status
Simulation time	34235952 ps
CPU time	0.84 seconds
Started	Apr 18 01:31:45 PM PDT 24
Finished	Apr 18 01:31:49 PM PDT 24
Peak memory	200580 kb
Host	smart-2b9f5346-6f14-4b2c-8cc8-93b275d222ee
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188466213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_handshake_intersig_mubi.4188466213
Directory	/workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_clk_status.2186588722
Short name	T392
Test name
Test status
Simulation time	15632510 ps
CPU time	0.7 seconds
Started	Apr 18 01:31:40 PM PDT 24
Finished	Apr 18 01:31:42 PM PDT 24
Peak memory	199512 kb
Host	smart-d9a628af-453c-4f10-9e02-3db8b1726715
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186588722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.2186588722
Directory	/workspace/1.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/1.clkmgr_div_intersig_mubi.1830385420
Short name	T554
Test name
Test status
Simulation time	26140704 ps
CPU time	0.88 seconds
Started	Apr 18 01:31:40 PM PDT 24
Finished	Apr 18 01:31:42 PM PDT 24
Peak memory	200632 kb
Host	smart-92946ed1-7cc5-4fb6-8481-005a86134c3b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830385420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_div_intersig_mubi.1830385420
Directory	/workspace/1.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_extclk.1061196326
Short name	T534
Test name
Test status
Simulation time	84755925 ps
CPU time	0.98 seconds
Started	Apr 18 01:31:44 PM PDT 24
Finished	Apr 18 01:31:47 PM PDT 24
Peak memory	200544 kb
Host	smart-76da25fb-558b-4775-ad30-e4c3a074003d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061196326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.1061196326
Directory	/workspace/1.clkmgr_extclk/latest

Test location	/workspace/coverage/default/1.clkmgr_frequency.1941366167
Short name	T7
Test name
Test status
Simulation time	569850490 ps
CPU time	3.62 seconds
Started	Apr 18 01:31:44 PM PDT 24
Finished	Apr 18 01:31:50 PM PDT 24
Peak memory	200560 kb
Host	smart-ab090663-0c58-4e96-8996-d0b80467cc14
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941366167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.1941366167
Directory	/workspace/1.clkmgr_frequency/latest

Test location	/workspace/coverage/default/1.clkmgr_frequency_timeout.2169505099
Short name	T510
Test name
Test status
Simulation time	1678013049 ps
CPU time	5.87 seconds
Started	Apr 18 01:31:43 PM PDT 24
Finished	Apr 18 01:31:52 PM PDT 24
Peak memory	200712 kb
Host	smart-ac32d1c2-adba-46b6-972c-bb2130d1423a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169505099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti meout.2169505099
Directory	/workspace/1.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/1.clkmgr_idle_intersig_mubi.2643415513
Short name	T848
Test name
Test status
Simulation time	19399439 ps
CPU time	0.84 seconds
Started	Apr 18 01:31:37 PM PDT 24
Finished	Apr 18 01:31:38 PM PDT 24
Peak memory	200572 kb
Host	smart-c865fd03-6509-4b09-be11-923d0c656416
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643415513 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_idle_intersig_mubi.2643415513
Directory	/workspace/1.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.257498095
Short name	T527
Test name
Test status
Simulation time	38471992 ps
CPU time	0.85 seconds
Started	Apr 18 01:31:45 PM PDT 24
Finished	Apr 18 01:31:48 PM PDT 24
Peak memory	200560 kb
Host	smart-61694128-2b13-4937-a8b0-7a83eb2281b5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257498095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.clkmgr_lc_clk_byp_req_intersig_mubi.257498095
Directory	/workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.2792329397
Short name	T620
Test name
Test status
Simulation time	38313813 ps
CPU time	0.81 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200568 kb
Host	smart-fff3aa62-3638-456e-8faf-b031a451362e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792329397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.clkmgr_lc_ctrl_intersig_mubi.2792329397
Directory	/workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_peri.1420246094
Short name	T801
Test name
Test status
Simulation time	19289074 ps
CPU time	0.74 seconds
Started	Apr 18 01:31:39 PM PDT 24
Finished	Apr 18 01:31:41 PM PDT 24
Peak memory	200344 kb
Host	smart-4197b96f-467c-4775-b00d-f0796dc0fea8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420246094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.1420246094
Directory	/workspace/1.clkmgr_peri/latest

Test location	/workspace/coverage/default/1.clkmgr_regwen.865941527
Short name	T467
Test name
Test status
Simulation time	291752826 ps
CPU time	1.64 seconds
Started	Apr 18 01:31:52 PM PDT 24
Finished	Apr 18 01:31:57 PM PDT 24
Peak memory	200500 kb
Host	smart-19ef28cb-442a-432d-bdab-94cfe0ce52b8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865941527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.865941527
Directory	/workspace/1.clkmgr_regwen/latest

Test location	/workspace/coverage/default/1.clkmgr_sec_cm.972713080
Short name	T46
Test name
Test status
Simulation time	1115545433 ps
CPU time	4.25 seconds
Started	Apr 18 01:31:42 PM PDT 24
Finished	Apr 18 01:31:48 PM PDT 24
Peak memory	215936 kb
Host	smart-38a598f8-fe42-4ae8-b96d-e4322cb5780d
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972713080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr _sec_cm.972713080
Directory	/workspace/1.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/1.clkmgr_smoke.2347283835
Short name	T496
Test name
Test status
Simulation time	56790236 ps
CPU time	0.96 seconds
Started	Apr 18 01:31:44 PM PDT 24
Finished	Apr 18 01:31:48 PM PDT 24
Peak memory	200552 kb
Host	smart-3419a942-3fb0-46f2-9e53-c9860c22cc57
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347283835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.2347283835
Directory	/workspace/1.clkmgr_smoke/latest

Test location	/workspace/coverage/default/1.clkmgr_stress_all.1744251742
Short name	T569
Test name
Test status
Simulation time	8750642361 ps
CPU time	63.71 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:32:57 PM PDT 24
Peak memory	200904 kb
Host	smart-7860c794-e116-4611-9041-d35e3c0ec513
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744251742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all.1744251742
Directory	/workspace/1.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/1.clkmgr_trans.3857941171
Short name	T641
Test name
Test status
Simulation time	25508107 ps
CPU time	0.86 seconds
Started	Apr 18 01:31:36 PM PDT 24
Finished	Apr 18 01:31:38 PM PDT 24
Peak memory	200508 kb
Host	smart-dca68ea2-402d-461e-9c9c-a4b2b0044239
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857941171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.3857941171
Directory	/workspace/1.clkmgr_trans/latest

Test location	/workspace/coverage/default/10.clkmgr_alert_test.3493243246
Short name	T196
Test name
Test status
Simulation time	31797121 ps
CPU time	0.78 seconds
Started	Apr 18 01:31:54 PM PDT 24
Finished	Apr 18 01:31:58 PM PDT 24
Peak memory	200512 kb
Host	smart-95000f2d-8bab-4e12-96fa-4a6d07981704
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493243246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk mgr_alert_test.3493243246
Directory	/workspace/10.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.3671910939
Short name	T517
Test name
Test status
Simulation time	89420694 ps
CPU time	1.07 seconds
Started	Apr 18 01:31:51 PM PDT 24
Finished	Apr 18 01:31:56 PM PDT 24
Peak memory	200532 kb
Host	smart-a75e32a5-e4f3-4c93-8400-5f3e0d44305d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671910939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_handshake_intersig_mubi.3671910939
Directory	/workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_clk_status.248435915
Short name	T328
Test name
Test status
Simulation time	52878251 ps
CPU time	0.78 seconds
Started	Apr 18 01:31:50 PM PDT 24
Finished	Apr 18 01:31:55 PM PDT 24
Peak memory	199516 kb
Host	smart-95b3ca57-f2f9-4bd8-bf16-67a6c6248632
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248435915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.248435915
Directory	/workspace/10.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/10.clkmgr_div_intersig_mubi.1525363786
Short name	T80
Test name
Test status
Simulation time	58734137 ps
CPU time	0.98 seconds
Started	Apr 18 01:31:51 PM PDT 24
Finished	Apr 18 01:31:56 PM PDT 24
Peak memory	200500 kb
Host	smart-953a5afd-9d12-45aa-a429-c59cc75c4290
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525363786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_div_intersig_mubi.1525363786
Directory	/workspace/10.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_extclk.3046248429
Short name	T478
Test name
Test status
Simulation time	43659887 ps
CPU time	0.79 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:55 PM PDT 24
Peak memory	200576 kb
Host	smart-62df6ddc-6f71-4b3d-aa3c-17e264c57bed
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046248429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.3046248429
Directory	/workspace/10.clkmgr_extclk/latest

Test location	/workspace/coverage/default/10.clkmgr_frequency.2454469615
Short name	T694
Test name
Test status
Simulation time	1357129594 ps
CPU time	6.21 seconds
Started	Apr 18 01:31:55 PM PDT 24
Finished	Apr 18 01:32:04 PM PDT 24
Peak memory	200580 kb
Host	smart-b94cfc04-98ee-499b-a0a3-a34e97aa3547
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454469615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.2454469615
Directory	/workspace/10.clkmgr_frequency/latest

Test location	/workspace/coverage/default/10.clkmgr_frequency_timeout.700310125
Short name	T479
Test name
Test status
Simulation time	256799919 ps
CPU time	2.28 seconds
Started	Apr 18 01:31:52 PM PDT 24
Finished	Apr 18 01:31:58 PM PDT 24
Peak memory	200672 kb
Host	smart-3192d5ab-02a2-4b96-b9f3-14f602af1044
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700310125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_ti meout.700310125
Directory	/workspace/10.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/10.clkmgr_idle_intersig_mubi.1254592462
Short name	T81
Test name
Test status
Simulation time	18891086 ps
CPU time	0.78 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:54 PM PDT 24
Peak memory	200448 kb
Host	smart-9f97e98a-1e78-49c3-a601-3ec986612fe0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254592462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_idle_intersig_mubi.1254592462
Directory	/workspace/10.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.1105393372
Short name	T530
Test name
Test status
Simulation time	43923109 ps
CPU time	0.82 seconds
Started	Apr 18 01:31:51 PM PDT 24
Finished	Apr 18 01:31:55 PM PDT 24
Peak memory	200492 kb
Host	smart-fd1a23bf-fe04-4ad9-8749-4ddc4769e47e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105393372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 10.clkmgr_lc_clk_byp_req_intersig_mubi.1105393372
Directory	/workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.1301868081
Short name	T216
Test name
Test status
Simulation time	33300492 ps
CPU time	0.82 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:55 PM PDT 24
Peak memory	200584 kb
Host	smart-20a94800-3fe3-43db-9435-890d137c4524
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301868081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 10.clkmgr_lc_ctrl_intersig_mubi.1301868081
Directory	/workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_peri.3124396095
Short name	T537
Test name
Test status
Simulation time	35574837 ps
CPU time	0.75 seconds
Started	Apr 18 01:31:56 PM PDT 24
Finished	Apr 18 01:32:00 PM PDT 24
Peak memory	200336 kb
Host	smart-27289ed0-6ca1-4e64-98ba-75b5d9d8ce87
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124396095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.3124396095
Directory	/workspace/10.clkmgr_peri/latest

Test location	/workspace/coverage/default/10.clkmgr_smoke.2987021447
Short name	T183
Test name
Test status
Simulation time	19478701 ps
CPU time	0.85 seconds
Started	Apr 18 01:31:50 PM PDT 24
Finished	Apr 18 01:31:54 PM PDT 24
Peak memory	200588 kb
Host	smart-da47ef35-bd49-4ac1-8b02-770c38dde976
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987021447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.2987021447
Directory	/workspace/10.clkmgr_smoke/latest

Test location	/workspace/coverage/default/10.clkmgr_stress_all.1904154824
Short name	T499
Test name
Test status
Simulation time	4578562075 ps
CPU time	33.04 seconds
Started	Apr 18 01:31:55 PM PDT 24
Finished	Apr 18 01:32:31 PM PDT 24
Peak memory	200900 kb
Host	smart-39f10fa0-8820-4f66-ab47-e2d9892b213c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904154824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all.1904154824
Directory	/workspace/10.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/10.clkmgr_stress_all_with_rand_reset.892370162
Short name	T156
Test name
Test status
Simulation time	23029679668 ps
CPU time	350.28 seconds
Started	Apr 18 01:31:51 PM PDT 24
Finished	Apr 18 01:37:45 PM PDT 24
Peak memory	215936 kb
Host	smart-e6a19286-8a72-4acd-847b-676c93eb229d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=892370162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.892370162
Directory	/workspace/10.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.clkmgr_trans.2081358019
Short name	T114
Test name
Test status
Simulation time	23098534 ps
CPU time	0.79 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200564 kb
Host	smart-a069b4d7-8308-435e-8c2f-217fb9fa417c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081358019 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.2081358019
Directory	/workspace/10.clkmgr_trans/latest

Test location	/workspace/coverage/default/11.clkmgr_alert_test.1266798509
Short name	T30
Test name
Test status
Simulation time	45460333 ps
CPU time	0.87 seconds
Started	Apr 18 01:31:44 PM PDT 24
Finished	Apr 18 01:31:48 PM PDT 24
Peak memory	200468 kb
Host	smart-f5e6e43b-6c99-48c4-a313-a277e1d19349
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266798509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk mgr_alert_test.1266798509
Directory	/workspace/11.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/11.clkmgr_clk_status.4273402022
Short name	T676
Test name
Test status
Simulation time	59753302 ps
CPU time	0.8 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:52 PM PDT 24
Peak memory	199448 kb
Host	smart-e6e80920-9af8-40a0-8fd6-4af13d394b39
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273402022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.4273402022
Directory	/workspace/11.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/11.clkmgr_div_intersig_mubi.2758753866
Short name	T241
Test name
Test status
Simulation time	17597736 ps
CPU time	0.71 seconds
Started	Apr 18 01:31:52 PM PDT 24
Finished	Apr 18 01:31:56 PM PDT 24
Peak memory	200540 kb
Host	smart-7bb41150-ce74-4a9f-aaa0-a08c93fa85e7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758753866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_div_intersig_mubi.2758753866
Directory	/workspace/11.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_extclk.1683844645
Short name	T374
Test name
Test status
Simulation time	14985569 ps
CPU time	0.74 seconds
Started	Apr 18 01:31:45 PM PDT 24
Finished	Apr 18 01:31:49 PM PDT 24
Peak memory	200556 kb
Host	smart-28580805-4b46-4611-87b5-738f2f7c52a8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683844645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.1683844645
Directory	/workspace/11.clkmgr_extclk/latest

Test location	/workspace/coverage/default/11.clkmgr_frequency.2766842745
Short name	T618
Test name
Test status
Simulation time	1417341908 ps
CPU time	7.02 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:58 PM PDT 24
Peak memory	200636 kb
Host	smart-ca6fc402-8b2f-43d6-a3bc-e3d29c9248bd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766842745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.2766842745
Directory	/workspace/11.clkmgr_frequency/latest

Test location	/workspace/coverage/default/11.clkmgr_frequency_timeout.1697981091
Short name	T468
Test name
Test status
Simulation time	1111415505 ps
CPU time	4.74 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:55 PM PDT 24
Peak memory	200664 kb
Host	smart-943a22ff-b974-447c-85d9-c31a4c151318
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697981091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_t imeout.1697981091
Directory	/workspace/11.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/11.clkmgr_idle_intersig_mubi.2989175841
Short name	T747
Test name
Test status
Simulation time	72897536 ps
CPU time	1.14 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:52 PM PDT 24
Peak memory	200504 kb
Host	smart-9c9d7bfa-2e46-46fb-8a17-590fbeaabbcd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989175841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_idle_intersig_mubi.2989175841
Directory	/workspace/11.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.839603900
Short name	T187
Test name
Test status
Simulation time	23518203 ps
CPU time	0.82 seconds
Started	Apr 18 01:31:46 PM PDT 24
Finished	Apr 18 01:31:50 PM PDT 24
Peak memory	200584 kb
Host	smart-cbaed7fd-4411-4151-bde6-f12e63e69951
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839603900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.clkmgr_lc_clk_byp_req_intersig_mubi.839603900
Directory	/workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.2137050064
Short name	T180
Test name
Test status
Simulation time	68605714 ps
CPU time	0.88 seconds
Started	Apr 18 01:31:56 PM PDT 24
Finished	Apr 18 01:31:59 PM PDT 24
Peak memory	200620 kb
Host	smart-4ebcc665-0307-45dc-b591-f04339f74c28
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137050064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 11.clkmgr_lc_ctrl_intersig_mubi.2137050064
Directory	/workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_peri.4095748653
Short name	T292
Test name
Test status
Simulation time	18705816 ps
CPU time	0.74 seconds
Started	Apr 18 01:31:50 PM PDT 24
Finished	Apr 18 01:31:55 PM PDT 24
Peak memory	200336 kb
Host	smart-5854cb12-7fb3-4d94-b935-581c08a212d5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095748653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.4095748653
Directory	/workspace/11.clkmgr_peri/latest

Test location	/workspace/coverage/default/11.clkmgr_regwen.902397598
Short name	T70
Test name
Test status
Simulation time	1064102838 ps
CPU time	4.59 seconds
Started	Apr 18 01:31:53 PM PDT 24
Finished	Apr 18 01:32:01 PM PDT 24
Peak memory	200696 kb
Host	smart-d2e4c48b-42d3-4ad6-80fc-4fd348256ce5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902397598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.902397598
Directory	/workspace/11.clkmgr_regwen/latest

Test location	/workspace/coverage/default/11.clkmgr_smoke.2718584664
Short name	T193
Test name
Test status
Simulation time	17706017 ps
CPU time	0.82 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:31:55 PM PDT 24
Peak memory	200516 kb
Host	smart-bc98feda-1f61-4eea-bbf7-982e2ec4ca43
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718584664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.2718584664
Directory	/workspace/11.clkmgr_smoke/latest

Test location	/workspace/coverage/default/11.clkmgr_stress_all.1526095880
Short name	T837
Test name
Test status
Simulation time	12599546337 ps
CPU time	47.08 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:32:38 PM PDT 24
Peak memory	201028 kb
Host	smart-f9fbaae2-9b23-4112-bb8e-5e008f5b34d4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526095880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all.1526095880
Directory	/workspace/11.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.3643957280
Short name	T336
Test name
Test status
Simulation time	35641811130 ps
CPU time	364.85 seconds
Started	Apr 18 01:32:20 PM PDT 24
Finished	Apr 18 01:38:26 PM PDT 24
Peak memory	209232 kb
Host	smart-ae1ef781-344a-46f8-a7be-af5ef0561fbf
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3643957280 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.3643957280
Directory	/workspace/11.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.clkmgr_trans.151903689
Short name	T540
Test name
Test status
Simulation time	27214827 ps
CPU time	0.71 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:52 PM PDT 24
Peak memory	200476 kb
Host	smart-845e3182-3696-4b7d-9ba4-7301b2119d45
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151903689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.151903689
Directory	/workspace/11.clkmgr_trans/latest

Test location	/workspace/coverage/default/12.clkmgr_alert_test.3184014052
Short name	T291
Test name
Test status
Simulation time	33407648 ps
CPU time	0.85 seconds
Started	Apr 18 01:31:45 PM PDT 24
Finished	Apr 18 01:31:48 PM PDT 24
Peak memory	200624 kb
Host	smart-b06e748a-1fc2-458d-b85c-64f306369811
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184014052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk mgr_alert_test.3184014052
Directory	/workspace/12.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.3045240217
Short name	T159
Test name
Test status
Simulation time	28983622 ps
CPU time	0.79 seconds
Started	Apr 18 01:31:55 PM PDT 24
Finished	Apr 18 01:31:59 PM PDT 24
Peak memory	200596 kb
Host	smart-24764d5e-4797-460f-9f32-bf85330fe626
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045240217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_handshake_intersig_mubi.3045240217
Directory	/workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_clk_status.3502123140
Short name	T752
Test name
Test status
Simulation time	15733029 ps
CPU time	0.72 seconds
Started	Apr 18 01:31:43 PM PDT 24
Finished	Apr 18 01:31:46 PM PDT 24
Peak memory	199488 kb
Host	smart-61b24891-8bc5-4a01-a1e8-f3182e4ea214
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502123140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.3502123140
Directory	/workspace/12.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/12.clkmgr_div_intersig_mubi.770563902
Short name	T209
Test name
Test status
Simulation time	41205431 ps
CPU time	0.9 seconds
Started	Apr 18 01:31:43 PM PDT 24
Finished	Apr 18 01:31:47 PM PDT 24
Peak memory	200488 kb
Host	smart-d78d89f4-db1f-4aad-b895-7f0796060e56
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770563902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.clkmgr_div_intersig_mubi.770563902
Directory	/workspace/12.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_extclk.668896614
Short name	T389
Test name
Test status
Simulation time	74828236 ps
CPU time	0.97 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200580 kb
Host	smart-4e9e5418-9354-4bcb-9207-8861f09b1d0d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668896614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.668896614
Directory	/workspace/12.clkmgr_extclk/latest

Test location	/workspace/coverage/default/12.clkmgr_frequency.3646614186
Short name	T812
Test name
Test status
Simulation time	2120568041 ps
CPU time	16.31 seconds
Started	Apr 18 01:31:52 PM PDT 24
Finished	Apr 18 01:32:12 PM PDT 24
Peak memory	200652 kb
Host	smart-dc2e6c76-7be0-488d-b038-0b5e44cb1bb2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646614186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.3646614186
Directory	/workspace/12.clkmgr_frequency/latest

Test location	/workspace/coverage/default/12.clkmgr_frequency_timeout.4109699826
Short name	T532
Test name
Test status
Simulation time	135098280 ps
CPU time	1.46 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:31:55 PM PDT 24
Peak memory	200604 kb
Host	smart-d85566ae-68e5-4ab5-9329-44f2ab368d88
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109699826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_t imeout.4109699826
Directory	/workspace/12.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/12.clkmgr_idle_intersig_mubi.3696778014
Short name	T546
Test name
Test status
Simulation time	52822723 ps
CPU time	0.89 seconds
Started	Apr 18 01:31:51 PM PDT 24
Finished	Apr 18 01:31:55 PM PDT 24
Peak memory	200532 kb
Host	smart-72a1d396-3448-4efe-a662-c918621c854c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696778014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_idle_intersig_mubi.3696778014
Directory	/workspace/12.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.3426968412
Short name	T476
Test name
Test status
Simulation time	83907247 ps
CPU time	0.99 seconds
Started	Apr 18 01:31:50 PM PDT 24
Finished	Apr 18 01:31:56 PM PDT 24
Peak memory	200572 kb
Host	smart-2faf39b3-b777-4ebf-a4e7-a7b261246052
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426968412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 12.clkmgr_lc_clk_byp_req_intersig_mubi.3426968412
Directory	/workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.1656002856
Short name	T614
Test name
Test status
Simulation time	17918569 ps
CPU time	0.73 seconds
Started	Apr 18 01:31:46 PM PDT 24
Finished	Apr 18 01:31:50 PM PDT 24
Peak memory	200520 kb
Host	smart-fb351fb8-80ec-4108-bddb-3c41d5a99066
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656002856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 12.clkmgr_lc_ctrl_intersig_mubi.1656002856
Directory	/workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_peri.1082511132
Short name	T825
Test name
Test status
Simulation time	17905261 ps
CPU time	0.74 seconds
Started	Apr 18 01:31:53 PM PDT 24
Finished	Apr 18 01:31:57 PM PDT 24
Peak memory	200240 kb
Host	smart-85a09c61-cde7-40ba-b6c7-78fd9d72e202
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082511132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.1082511132
Directory	/workspace/12.clkmgr_peri/latest

Test location	/workspace/coverage/default/12.clkmgr_regwen.1633449291
Short name	T788
Test name
Test status
Simulation time	1399133784 ps
CPU time	7.34 seconds
Started	Apr 18 01:31:50 PM PDT 24
Finished	Apr 18 01:32:02 PM PDT 24
Peak memory	200732 kb
Host	smart-e5701f77-8a5e-4960-a61d-db23d8c5a9a6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633449291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.1633449291
Directory	/workspace/12.clkmgr_regwen/latest

Test location	/workspace/coverage/default/12.clkmgr_smoke.1143878088
Short name	T772
Test name
Test status
Simulation time	87361537 ps
CPU time	0.95 seconds
Started	Apr 18 01:31:45 PM PDT 24
Finished	Apr 18 01:31:48 PM PDT 24
Peak memory	200564 kb
Host	smart-445038f6-dfb7-48d8-b271-073e38546bfc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143878088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.1143878088
Directory	/workspace/12.clkmgr_smoke/latest

Test location	/workspace/coverage/default/12.clkmgr_stress_all.3176532156
Short name	T519
Test name
Test status
Simulation time	12596074163 ps
CPU time	49.84 seconds
Started	Apr 18 01:31:45 PM PDT 24
Finished	Apr 18 01:32:38 PM PDT 24
Peak memory	201024 kb
Host	smart-53355a30-3941-4981-9dbb-7431d99dd388
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176532156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all.3176532156
Directory	/workspace/12.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/12.clkmgr_stress_all_with_rand_reset.917556786
Short name	T146
Test name
Test status
Simulation time	98605052284 ps
CPU time	584.68 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:41:36 PM PDT 24
Peak memory	217392 kb
Host	smart-644b304b-68d2-41a9-a668-99b36889b0fb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=917556786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.917556786
Directory	/workspace/12.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.clkmgr_trans.2996912172
Short name	T512
Test name
Test status
Simulation time	52427976 ps
CPU time	0.91 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200468 kb
Host	smart-d4d6cf90-f825-488a-a959-83415924fd4e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996912172 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.2996912172
Directory	/workspace/12.clkmgr_trans/latest

Test location	/workspace/coverage/default/13.clkmgr_alert_test.227868311
Short name	T284
Test name
Test status
Simulation time	19532359 ps
CPU time	0.82 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:54 PM PDT 24
Peak memory	200636 kb
Host	smart-7c75028b-2a9c-42e2-b0cb-a1dfae0bab89
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227868311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkm gr_alert_test.227868311
Directory	/workspace/13.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.2036814229
Short name	T294
Test name
Test status
Simulation time	22182867 ps
CPU time	0.87 seconds
Started	Apr 18 01:31:55 PM PDT 24
Finished	Apr 18 01:31:59 PM PDT 24
Peak memory	200604 kb
Host	smart-4b58e5ef-aaae-41c0-ae91-04467975c083
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036814229 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_handshake_intersig_mubi.2036814229
Directory	/workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_clk_status.2384668784
Short name	T589
Test name
Test status
Simulation time	13857458 ps
CPU time	0.7 seconds
Started	Apr 18 01:31:56 PM PDT 24
Finished	Apr 18 01:32:00 PM PDT 24
Peak memory	200448 kb
Host	smart-2df8e29e-033b-4c6d-b748-eae1184726e0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384668784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.2384668784
Directory	/workspace/13.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/13.clkmgr_div_intersig_mubi.1176976073
Short name	T425
Test name
Test status
Simulation time	64827871 ps
CPU time	0.89 seconds
Started	Apr 18 01:31:55 PM PDT 24
Finished	Apr 18 01:31:58 PM PDT 24
Peak memory	200540 kb
Host	smart-c3b74b79-a718-4d6f-a401-661e90ed35fb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176976073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_div_intersig_mubi.1176976073
Directory	/workspace/13.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_extclk.588335037
Short name	T383
Test name
Test status
Simulation time	74148716 ps
CPU time	1.02 seconds
Started	Apr 18 01:31:51 PM PDT 24
Finished	Apr 18 01:31:56 PM PDT 24
Peak memory	200484 kb
Host	smart-6fa7c88c-6746-4904-8fae-fabc3b5c6f57
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588335037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.588335037
Directory	/workspace/13.clkmgr_extclk/latest

Test location	/workspace/coverage/default/13.clkmgr_frequency.1135552004
Short name	T778
Test name
Test status
Simulation time	2376725267 ps
CPU time	10.02 seconds
Started	Apr 18 01:31:56 PM PDT 24
Finished	Apr 18 01:32:09 PM PDT 24
Peak memory	200836 kb
Host	smart-a04649d7-dddc-4cd3-9c01-6c95fbeb282b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135552004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.1135552004
Directory	/workspace/13.clkmgr_frequency/latest

Test location	/workspace/coverage/default/13.clkmgr_frequency_timeout.926121892
Short name	T518
Test name
Test status
Simulation time	415612416 ps
CPU time	2.04 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:31:54 PM PDT 24
Peak memory	200704 kb
Host	smart-fff10105-adba-4521-afcd-7b5645153b11
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926121892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_ti meout.926121892
Directory	/workspace/13.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/13.clkmgr_idle_intersig_mubi.3578406291
Short name	T358
Test name
Test status
Simulation time	18215337 ps
CPU time	0.67 seconds
Started	Apr 18 01:31:46 PM PDT 24
Finished	Apr 18 01:31:51 PM PDT 24
Peak memory	200324 kb
Host	smart-2755846d-6564-412f-9d02-e3096ae04507
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578406291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_idle_intersig_mubi.3578406291
Directory	/workspace/13.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.2694825206
Short name	T557
Test name
Test status
Simulation time	56435514 ps
CPU time	0.88 seconds
Started	Apr 18 01:31:58 PM PDT 24
Finished	Apr 18 01:32:00 PM PDT 24
Peak memory	200552 kb
Host	smart-8f4c4649-8e3a-4e2a-9385-da7ecc37e8e4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694825206 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 13.clkmgr_lc_clk_byp_req_intersig_mubi.2694825206
Directory	/workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.540142900
Short name	T320
Test name
Test status
Simulation time	59950889 ps
CPU time	0.95 seconds
Started	Apr 18 01:31:53 PM PDT 24
Finished	Apr 18 01:31:57 PM PDT 24
Peak memory	200524 kb
Host	smart-61212a43-cc63-4088-aba8-e49e8e1ebd91
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540142900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.clkmgr_lc_ctrl_intersig_mubi.540142900
Directory	/workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_peri.353860796
Short name	T373
Test name
Test status
Simulation time	26464713 ps
CPU time	0.79 seconds
Started	Apr 18 01:31:52 PM PDT 24
Finished	Apr 18 01:31:56 PM PDT 24
Peak memory	200276 kb
Host	smart-fdd8bd9a-7742-4865-930c-af80fbcf348a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353860796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.353860796
Directory	/workspace/13.clkmgr_peri/latest

Test location	/workspace/coverage/default/13.clkmgr_regwen.2768040460
Short name	T615
Test name
Test status
Simulation time	470501712 ps
CPU time	3.12 seconds
Started	Apr 18 01:31:54 PM PDT 24
Finished	Apr 18 01:32:00 PM PDT 24
Peak memory	200568 kb
Host	smart-688924dd-94ed-4954-991d-97bd0a0de616
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768040460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.2768040460
Directory	/workspace/13.clkmgr_regwen/latest

Test location	/workspace/coverage/default/13.clkmgr_smoke.2826457804
Short name	T617
Test name
Test status
Simulation time	32003880 ps
CPU time	0.85 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200548 kb
Host	smart-67951f32-cc82-4e37-8657-8c8ced7092bd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826457804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.2826457804
Directory	/workspace/13.clkmgr_smoke/latest

Test location	/workspace/coverage/default/13.clkmgr_stress_all.1954607355
Short name	T673
Test name
Test status
Simulation time	7512927752 ps
CPU time	51.14 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:32:44 PM PDT 24
Peak memory	200968 kb
Host	smart-3c63a17c-c9f1-443f-b9a5-1bbac9fdac2c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954607355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all.1954607355
Directory	/workspace/13.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.4278022334
Short name	T36
Test name
Test status
Simulation time	31882777942 ps
CPU time	203.79 seconds
Started	Apr 18 01:31:52 PM PDT 24
Finished	Apr 18 01:35:19 PM PDT 24
Peak memory	209268 kb
Host	smart-f0923df4-0482-401b-9527-9c4fffbb7191
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4278022334 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.4278022334
Directory	/workspace/13.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.clkmgr_trans.318733721
Short name	T185
Test name
Test status
Simulation time	34489648 ps
CPU time	0.94 seconds
Started	Apr 18 01:31:46 PM PDT 24
Finished	Apr 18 01:31:50 PM PDT 24
Peak memory	200496 kb
Host	smart-22be79cc-2923-49e3-9d5b-dba845a9990f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318733721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.318733721
Directory	/workspace/13.clkmgr_trans/latest

Test location	/workspace/coverage/default/14.clkmgr_alert_test.4149533082
Short name	T736
Test name
Test status
Simulation time	31838141 ps
CPU time	0.75 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200472 kb
Host	smart-0f867ccb-c33b-4560-a0fc-8f2d44ad97ea
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149533082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clk mgr_alert_test.4149533082
Directory	/workspace/14.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.3176170979
Short name	T829
Test name
Test status
Simulation time	14540309 ps
CPU time	0.72 seconds
Started	Apr 18 01:31:53 PM PDT 24
Finished	Apr 18 01:31:57 PM PDT 24
Peak memory	200604 kb
Host	smart-afd173ff-9002-48cd-901f-c3088d91cebf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176170979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_handshake_intersig_mubi.3176170979
Directory	/workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_clk_status.1863447352
Short name	T596
Test name
Test status
Simulation time	15307755 ps
CPU time	0.68 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:52 PM PDT 24
Peak memory	199512 kb
Host	smart-cc27f727-25a6-4412-98a3-c19532ebd4eb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863447352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.1863447352
Directory	/workspace/14.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/14.clkmgr_div_intersig_mubi.3953762043
Short name	T305
Test name
Test status
Simulation time	71216731 ps
CPU time	0.94 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200500 kb
Host	smart-128d7929-0694-4634-85b9-e04da6d68831
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953762043 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_div_intersig_mubi.3953762043
Directory	/workspace/14.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_extclk.1808140107
Short name	T15
Test name
Test status
Simulation time	26393345 ps
CPU time	0.92 seconds
Started	Apr 18 01:31:53 PM PDT 24
Finished	Apr 18 01:31:57 PM PDT 24
Peak memory	200572 kb
Host	smart-12e0f3ed-d370-4fee-bec9-3e264c880dd5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808140107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.1808140107
Directory	/workspace/14.clkmgr_extclk/latest

Test location	/workspace/coverage/default/14.clkmgr_frequency.441298066
Short name	T489
Test name
Test status
Simulation time	1163637445 ps
CPU time	8.9 seconds
Started	Apr 18 01:31:52 PM PDT 24
Finished	Apr 18 01:32:04 PM PDT 24
Peak memory	200532 kb
Host	smart-c424fac3-7453-41d1-a82d-c7ebb39ba602
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441298066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.441298066
Directory	/workspace/14.clkmgr_frequency/latest

Test location	/workspace/coverage/default/14.clkmgr_frequency_timeout.2924419400
Short name	T236
Test name
Test status
Simulation time	1699883402 ps
CPU time	12.2 seconds
Started	Apr 18 01:31:53 PM PDT 24
Finished	Apr 18 01:32:08 PM PDT 24
Peak memory	200656 kb
Host	smart-f3236be8-72e3-4854-bbc9-da5f471a019e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924419400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_t imeout.2924419400
Directory	/workspace/14.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/14.clkmgr_idle_intersig_mubi.2932512008
Short name	T403
Test name
Test status
Simulation time	52072334 ps
CPU time	0.88 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:54 PM PDT 24
Peak memory	200556 kb
Host	smart-12d75be1-59ed-45bf-a4da-1b4f2f6ec0e2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932512008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_idle_intersig_mubi.2932512008
Directory	/workspace/14.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.138569063
Short name	T435
Test name
Test status
Simulation time	47086401 ps
CPU time	0.82 seconds
Started	Apr 18 01:31:56 PM PDT 24
Finished	Apr 18 01:31:59 PM PDT 24
Peak memory	200580 kb
Host	smart-9a7ab244-2945-45c4-8b36-f13311462b07
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138569063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.clkmgr_lc_clk_byp_req_intersig_mubi.138569063
Directory	/workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.3229097683
Short name	T826
Test name
Test status
Simulation time	16623262 ps
CPU time	0.76 seconds
Started	Apr 18 01:31:55 PM PDT 24
Finished	Apr 18 01:31:59 PM PDT 24
Peak memory	200600 kb
Host	smart-153a39c8-0ed0-4b55-8b0d-9e5630976f9e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229097683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 14.clkmgr_lc_ctrl_intersig_mubi.3229097683
Directory	/workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_peri.1789858385
Short name	T346
Test name
Test status
Simulation time	16270187 ps
CPU time	0.71 seconds
Started	Apr 18 01:31:50 PM PDT 24
Finished	Apr 18 01:31:55 PM PDT 24
Peak memory	200224 kb
Host	smart-0ab345e4-bae4-4ae9-804d-68330a006105
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789858385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.1789858385
Directory	/workspace/14.clkmgr_peri/latest

Test location	/workspace/coverage/default/14.clkmgr_regwen.2783072745
Short name	T22
Test name
Test status
Simulation time	61933521 ps
CPU time	0.97 seconds
Started	Apr 18 01:31:43 PM PDT 24
Finished	Apr 18 01:31:47 PM PDT 24
Peak memory	200504 kb
Host	smart-cf4dabda-d364-40e1-912c-e9b8bd5bd11e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783072745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.2783072745
Directory	/workspace/14.clkmgr_regwen/latest

Test location	/workspace/coverage/default/14.clkmgr_smoke.1243448184
Short name	T422
Test name
Test status
Simulation time	15121574 ps
CPU time	0.78 seconds
Started	Apr 18 01:31:52 PM PDT 24
Finished	Apr 18 01:31:57 PM PDT 24
Peak memory	200572 kb
Host	smart-bd99322d-50c2-4312-83a0-893e53e0200c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243448184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.1243448184
Directory	/workspace/14.clkmgr_smoke/latest

Test location	/workspace/coverage/default/14.clkmgr_stress_all.2807115366
Short name	T108
Test name
Test status
Simulation time	2195344851 ps
CPU time	16.15 seconds
Started	Apr 18 01:31:44 PM PDT 24
Finished	Apr 18 01:32:03 PM PDT 24
Peak memory	201020 kb
Host	smart-2c4803be-83e3-488e-8fc5-e1d31aedb715
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807115366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all.2807115366
Directory	/workspace/14.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/14.clkmgr_stress_all_with_rand_reset.189477798
Short name	T447
Test name
Test status
Simulation time	131247596059 ps
CPU time	757.6 seconds
Started	Apr 18 01:32:05 PM PDT 24
Finished	Apr 18 01:44:48 PM PDT 24
Peak memory	212740 kb
Host	smart-1338c47d-aa92-40be-a74a-ea3273e7e4d1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=189477798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.189477798
Directory	/workspace/14.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.clkmgr_trans.3963684202
Short name	T319
Test name
Test status
Simulation time	50231688 ps
CPU time	0.85 seconds
Started	Apr 18 01:31:52 PM PDT 24
Finished	Apr 18 01:31:56 PM PDT 24
Peak memory	200432 kb
Host	smart-d07099b7-a7a3-4504-abe8-6afb3bfc3c41
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963684202 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.3963684202
Directory	/workspace/14.clkmgr_trans/latest

Test location	/workspace/coverage/default/15.clkmgr_alert_test.136767797
Short name	T723
Test name
Test status
Simulation time	18808260 ps
CPU time	0.82 seconds
Started	Apr 18 01:31:56 PM PDT 24
Finished	Apr 18 01:31:59 PM PDT 24
Peak memory	200652 kb
Host	smart-23d65168-1dfb-46af-8c5a-7c3c658b5805
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136767797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkm gr_alert_test.136767797
Directory	/workspace/15.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.3816303937
Short name	T602
Test name
Test status
Simulation time	41628414 ps
CPU time	0.82 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:54 PM PDT 24
Peak memory	200572 kb
Host	smart-ee8da1c6-ba0c-4e92-a26a-e9a0f2cbfc5f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816303937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_handshake_intersig_mubi.3816303937
Directory	/workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_clk_status.3464751055
Short name	T651
Test name
Test status
Simulation time	15228781 ps
CPU time	0.73 seconds
Started	Apr 18 01:32:18 PM PDT 24
Finished	Apr 18 01:32:19 PM PDT 24
Peak memory	200244 kb
Host	smart-cac1fe8f-b4b3-4c2a-88c3-a7f193bdf06d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464751055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.3464751055
Directory	/workspace/15.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/15.clkmgr_div_intersig_mubi.2146515849
Short name	T302
Test name
Test status
Simulation time	187088049 ps
CPU time	1.28 seconds
Started	Apr 18 01:31:54 PM PDT 24
Finished	Apr 18 01:31:58 PM PDT 24
Peak memory	200516 kb
Host	smart-96eea25b-f70a-4e7e-a3a0-7eb656cc600c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146515849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_div_intersig_mubi.2146515849
Directory	/workspace/15.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_extclk.615958680
Short name	T464
Test name
Test status
Simulation time	76359882 ps
CPU time	1.04 seconds
Started	Apr 18 01:31:46 PM PDT 24
Finished	Apr 18 01:31:51 PM PDT 24
Peak memory	200552 kb
Host	smart-a152a3ef-3669-46c7-9e55-a611572d0fda
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615958680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.615958680
Directory	/workspace/15.clkmgr_extclk/latest

Test location	/workspace/coverage/default/15.clkmgr_frequency.2144776790
Short name	T285
Test name
Test status
Simulation time	201040126 ps
CPU time	2.22 seconds
Started	Apr 18 01:31:58 PM PDT 24
Finished	Apr 18 01:32:02 PM PDT 24
Peak memory	200516 kb
Host	smart-5af0001b-490d-4588-ab34-1543f9aea2c8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144776790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.2144776790
Directory	/workspace/15.clkmgr_frequency/latest

Test location	/workspace/coverage/default/15.clkmgr_frequency_timeout.3895165146
Short name	T256
Test name
Test status
Simulation time	1216219634 ps
CPU time	8.62 seconds
Started	Apr 18 01:31:54 PM PDT 24
Finished	Apr 18 01:32:06 PM PDT 24
Peak memory	200680 kb
Host	smart-0dcd559a-5274-4d49-8c0b-71eff49cced2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895165146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t imeout.3895165146
Directory	/workspace/15.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/15.clkmgr_idle_intersig_mubi.1749192695
Short name	T289
Test name
Test status
Simulation time	26775676 ps
CPU time	0.89 seconds
Started	Apr 18 01:31:53 PM PDT 24
Finished	Apr 18 01:31:57 PM PDT 24
Peak memory	200532 kb
Host	smart-7750dc7d-0346-4958-b57d-45033eb396e0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749192695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_idle_intersig_mubi.1749192695
Directory	/workspace/15.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.2363625927
Short name	T672
Test name
Test status
Simulation time	56274809 ps
CPU time	0.92 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:54 PM PDT 24
Peak memory	200536 kb
Host	smart-4ce11945-4355-43c6-9b40-f84f93f1388d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363625927 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 15.clkmgr_lc_clk_byp_req_intersig_mubi.2363625927
Directory	/workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.2421672475
Short name	T349
Test name
Test status
Simulation time	20622278 ps
CPU time	0.79 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:52 PM PDT 24
Peak memory	200608 kb
Host	smart-12d93224-4982-4739-a89e-8bac64c3a647
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421672475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 15.clkmgr_lc_ctrl_intersig_mubi.2421672475
Directory	/workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_peri.265234374
Short name	T173
Test name
Test status
Simulation time	17476413 ps
CPU time	0.81 seconds
Started	Apr 18 01:31:56 PM PDT 24
Finished	Apr 18 01:32:02 PM PDT 24
Peak memory	200360 kb
Host	smart-fe3b88e5-ce3e-445e-a6ac-2ef6f5b31843
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265234374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.265234374
Directory	/workspace/15.clkmgr_peri/latest

Test location	/workspace/coverage/default/15.clkmgr_regwen.2655224877
Short name	T109
Test name
Test status
Simulation time	1394441739 ps
CPU time	4.95 seconds
Started	Apr 18 01:31:53 PM PDT 24
Finished	Apr 18 01:32:02 PM PDT 24
Peak memory	200732 kb
Host	smart-355cdc64-2b74-4435-a10a-e67b8c6cd0c4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655224877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.2655224877
Directory	/workspace/15.clkmgr_regwen/latest

Test location	/workspace/coverage/default/15.clkmgr_smoke.3371782581
Short name	T64
Test name
Test status
Simulation time	28360299 ps
CPU time	0.81 seconds
Started	Apr 18 01:31:56 PM PDT 24
Finished	Apr 18 01:31:59 PM PDT 24
Peak memory	200588 kb
Host	smart-d2e7649e-5a12-4c87-9b33-844c239e5675
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371782581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.3371782581
Directory	/workspace/15.clkmgr_smoke/latest

Test location	/workspace/coverage/default/15.clkmgr_stress_all.1753711606
Short name	T110
Test name
Test status
Simulation time	10748034547 ps
CPU time	43.19 seconds
Started	Apr 18 01:31:57 PM PDT 24
Finished	Apr 18 01:32:42 PM PDT 24
Peak memory	200928 kb
Host	smart-cdbd4b7b-2bbf-44ec-9a55-96e8ec4f87e7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753711606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all.1753711606
Directory	/workspace/15.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/15.clkmgr_stress_all_with_rand_reset.1833238877
Short name	T276
Test name
Test status
Simulation time	37438558700 ps
CPU time	414.46 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:38:47 PM PDT 24
Peak memory	217416 kb
Host	smart-ec8a665c-4dc1-439b-823c-b49c928c9f3d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1833238877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.1833238877
Directory	/workspace/15.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.clkmgr_trans.1994831096
Short name	T818
Test name
Test status
Simulation time	54588461 ps
CPU time	0.86 seconds
Started	Apr 18 01:31:52 PM PDT 24
Finished	Apr 18 01:31:57 PM PDT 24
Peak memory	200556 kb
Host	smart-2a374782-bd72-44a8-905c-1459c80d8546
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994831096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.1994831096
Directory	/workspace/15.clkmgr_trans/latest

Test location	/workspace/coverage/default/16.clkmgr_alert_test.107099060
Short name	T214
Test name
Test status
Simulation time	30872696 ps
CPU time	0.74 seconds
Started	Apr 18 01:31:54 PM PDT 24
Finished	Apr 18 01:31:58 PM PDT 24
Peak memory	200416 kb
Host	smart-933b2f6a-7690-402c-b874-e87d00b38578
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107099060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkm gr_alert_test.107099060
Directory	/workspace/16.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.3673094430
Short name	T580
Test name
Test status
Simulation time	66184249 ps
CPU time	0.93 seconds
Started	Apr 18 01:31:56 PM PDT 24
Finished	Apr 18 01:32:00 PM PDT 24
Peak memory	200604 kb
Host	smart-72781f17-622e-43f3-b9fd-00109b544603
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673094430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_handshake_intersig_mubi.3673094430
Directory	/workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_clk_status.3613386058
Short name	T152
Test name
Test status
Simulation time	37064354 ps
CPU time	0.71 seconds
Started	Apr 18 01:31:55 PM PDT 24
Finished	Apr 18 01:31:59 PM PDT 24
Peak memory	200252 kb
Host	smart-ab021b0c-2c52-44ba-a187-8fda64136d71
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613386058 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.3613386058
Directory	/workspace/16.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/16.clkmgr_div_intersig_mubi.1435148134
Short name	T188
Test name
Test status
Simulation time	42632534 ps
CPU time	0.85 seconds
Started	Apr 18 01:31:57 PM PDT 24
Finished	Apr 18 01:32:00 PM PDT 24
Peak memory	200568 kb
Host	smart-4bcf02b0-20dc-45df-ad39-f48544a378df
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435148134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_div_intersig_mubi.1435148134
Directory	/workspace/16.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_extclk.1978191451
Short name	T428
Test name
Test status
Simulation time	20437723 ps
CPU time	0.78 seconds
Started	Apr 18 01:32:09 PM PDT 24
Finished	Apr 18 01:32:10 PM PDT 24
Peak memory	200576 kb
Host	smart-88456ef5-1e1b-4186-9ba7-b6c4882bd8be
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978191451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.1978191451
Directory	/workspace/16.clkmgr_extclk/latest

Test location	/workspace/coverage/default/16.clkmgr_frequency.1262781629
Short name	T253
Test name
Test status
Simulation time	926635862 ps
CPU time	3.91 seconds
Started	Apr 18 01:31:54 PM PDT 24
Finished	Apr 18 01:32:01 PM PDT 24
Peak memory	200584 kb
Host	smart-1a7f4e16-0219-49d1-af5c-fbf0e0dc55e2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262781629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.1262781629
Directory	/workspace/16.clkmgr_frequency/latest

Test location	/workspace/coverage/default/16.clkmgr_frequency_timeout.3332952646
Short name	T206
Test name
Test status
Simulation time	2420237876 ps
CPU time	16.2 seconds
Started	Apr 18 01:31:50 PM PDT 24
Finished	Apr 18 01:32:10 PM PDT 24
Peak memory	200896 kb
Host	smart-3805f9f1-bb8c-425e-9b45-59ab3fce4aa0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332952646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t imeout.3332952646
Directory	/workspace/16.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/16.clkmgr_idle_intersig_mubi.3064332194
Short name	T243
Test name
Test status
Simulation time	84846454 ps
CPU time	1.03 seconds
Started	Apr 18 01:31:55 PM PDT 24
Finished	Apr 18 01:31:58 PM PDT 24
Peak memory	200520 kb
Host	smart-c5172579-1914-4dbe-8cc1-a168fcbaa1fa
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064332194 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_idle_intersig_mubi.3064332194
Directory	/workspace/16.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.1539841748
Short name	T593
Test name
Test status
Simulation time	50591668 ps
CPU time	0.81 seconds
Started	Apr 18 01:31:45 PM PDT 24
Finished	Apr 18 01:31:49 PM PDT 24
Peak memory	200588 kb
Host	smart-6913dc10-267d-4809-beba-8de58dbc7f25
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539841748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 16.clkmgr_lc_clk_byp_req_intersig_mubi.1539841748
Directory	/workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.1365254052
Short name	T415
Test name
Test status
Simulation time	126401291 ps
CPU time	1.09 seconds
Started	Apr 18 01:31:53 PM PDT 24
Finished	Apr 18 01:31:57 PM PDT 24
Peak memory	200584 kb
Host	smart-16c45af5-6447-4438-abfa-5cace7da130a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365254052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 16.clkmgr_lc_ctrl_intersig_mubi.1365254052
Directory	/workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_peri.4171470497
Short name	T264
Test name
Test status
Simulation time	17760023 ps
CPU time	0.76 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200300 kb
Host	smart-f9d23200-cdbe-4736-82c3-3b9128d09991
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171470497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.4171470497
Directory	/workspace/16.clkmgr_peri/latest

Test location	/workspace/coverage/default/16.clkmgr_regwen.2853437870
Short name	T391
Test name
Test status
Simulation time	1462178579 ps
CPU time	4.56 seconds
Started	Apr 18 01:31:58 PM PDT 24
Finished	Apr 18 01:32:05 PM PDT 24
Peak memory	200728 kb
Host	smart-e3161d0a-f83a-4388-b233-99035827f78f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853437870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.2853437870
Directory	/workspace/16.clkmgr_regwen/latest

Test location	/workspace/coverage/default/16.clkmgr_smoke.3999392714
Short name	T544
Test name
Test status
Simulation time	42970834 ps
CPU time	0.89 seconds
Started	Apr 18 01:31:54 PM PDT 24
Finished	Apr 18 01:31:58 PM PDT 24
Peak memory	200568 kb
Host	smart-ce6b39cf-1fb4-468f-b3a8-6bf3560b1126
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999392714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.3999392714
Directory	/workspace/16.clkmgr_smoke/latest

Test location	/workspace/coverage/default/16.clkmgr_stress_all.3319401645
Short name	T502
Test name
Test status
Simulation time	8492711907 ps
CPU time	34.26 seconds
Started	Apr 18 01:31:43 PM PDT 24
Finished	Apr 18 01:32:20 PM PDT 24
Peak memory	200964 kb
Host	smart-4888c79b-97cd-47e7-b380-4806fe90c643
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319401645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all.3319401645
Directory	/workspace/16.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/16.clkmgr_stress_all_with_rand_reset.2734794073
Short name	T21
Test name
Test status
Simulation time	124024320808 ps
CPU time	729.61 seconds
Started	Apr 18 01:31:50 PM PDT 24
Finished	Apr 18 01:44:04 PM PDT 24
Peak memory	209260 kb
Host	smart-15ae6d9f-1c3e-426b-8088-34cf800ae246
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2734794073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.2734794073
Directory	/workspace/16.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.clkmgr_trans.184772577
Short name	T444
Test name
Test status
Simulation time	63332523 ps
CPU time	1.02 seconds
Started	Apr 18 01:31:55 PM PDT 24
Finished	Apr 18 01:31:59 PM PDT 24
Peak memory	200456 kb
Host	smart-a210e313-bab2-4f64-90e2-665f154c7741
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184772577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.184772577
Directory	/workspace/16.clkmgr_trans/latest

Test location	/workspace/coverage/default/17.clkmgr_alert_test.1750517081
Short name	T658
Test name
Test status
Simulation time	31232521 ps
CPU time	0.8 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200628 kb
Host	smart-a7714711-47cf-4959-a800-e16964442dcd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750517081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk mgr_alert_test.1750517081
Directory	/workspace/17.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.540867048
Short name	T560
Test name
Test status
Simulation time	34776836 ps
CPU time	0.83 seconds
Started	Apr 18 01:32:03 PM PDT 24
Finished	Apr 18 01:32:05 PM PDT 24
Peak memory	200564 kb
Host	smart-3638570b-1fd8-43d4-befc-56a472239596
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540867048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_handshake_intersig_mubi.540867048
Directory	/workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_div_intersig_mubi.1232552471
Short name	T272
Test name
Test status
Simulation time	13791296 ps
CPU time	0.72 seconds
Started	Apr 18 01:31:55 PM PDT 24
Finished	Apr 18 01:31:58 PM PDT 24
Peak memory	200536 kb
Host	smart-c12bb9f5-e56e-49a2-a4d2-305b455b757e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232552471 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_div_intersig_mubi.1232552471
Directory	/workspace/17.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_extclk.2214039387
Short name	T513
Test name
Test status
Simulation time	20640783 ps
CPU time	0.8 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200516 kb
Host	smart-70cdc223-c8fb-47c1-8e1a-0bfeb4a17fd7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214039387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.2214039387
Directory	/workspace/17.clkmgr_extclk/latest

Test location	/workspace/coverage/default/17.clkmgr_frequency.153214673
Short name	T669
Test name
Test status
Simulation time	1438591000 ps
CPU time	6.26 seconds
Started	Apr 18 01:31:54 PM PDT 24
Finished	Apr 18 01:32:03 PM PDT 24
Peak memory	200584 kb
Host	smart-b7ea23db-1b7c-462c-a7a0-27d34d7a6fa5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153214673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.153214673
Directory	/workspace/17.clkmgr_frequency/latest

Test location	/workspace/coverage/default/17.clkmgr_frequency_timeout.2064946458
Short name	T384
Test name
Test status
Simulation time	1103467147 ps
CPU time	5.96 seconds
Started	Apr 18 01:32:05 PM PDT 24
Finished	Apr 18 01:32:11 PM PDT 24
Peak memory	200688 kb
Host	smart-6d39e358-281d-4185-9b3a-fde9c89b30a3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064946458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t imeout.2064946458
Directory	/workspace/17.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.4144568085
Short name	T799
Test name
Test status
Simulation time	14244744 ps
CPU time	0.72 seconds
Started	Apr 18 01:31:51 PM PDT 24
Finished	Apr 18 01:31:56 PM PDT 24
Peak memory	200564 kb
Host	smart-43227dd8-0412-4e72-b9e3-197605bb5ae6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144568085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 17.clkmgr_lc_clk_byp_req_intersig_mubi.4144568085
Directory	/workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.4065912231
Short name	T137
Test name
Test status
Simulation time	93769647 ps
CPU time	1.03 seconds
Started	Apr 18 01:31:57 PM PDT 24
Finished	Apr 18 01:32:00 PM PDT 24
Peak memory	200552 kb
Host	smart-99df3b5f-ac59-4f3b-94e1-ee13b1afe593
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065912231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 17.clkmgr_lc_ctrl_intersig_mubi.4065912231
Directory	/workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_peri.28417176
Short name	T663
Test name
Test status
Simulation time	70772508 ps
CPU time	0.91 seconds
Started	Apr 18 01:31:57 PM PDT 24
Finished	Apr 18 01:32:00 PM PDT 24
Peak memory	200268 kb
Host	smart-b24576e2-94fc-41a0-8cb6-fad03488af5d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28417176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.28417176
Directory	/workspace/17.clkmgr_peri/latest

Test location	/workspace/coverage/default/17.clkmgr_regwen.1033188821
Short name	T4
Test name
Test status
Simulation time	1259432417 ps
CPU time	5.61 seconds
Started	Apr 18 01:31:57 PM PDT 24
Finished	Apr 18 01:32:05 PM PDT 24
Peak memory	200704 kb
Host	smart-10cb6323-b913-4527-aa05-584c17cb9468
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033188821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.1033188821
Directory	/workspace/17.clkmgr_regwen/latest

Test location	/workspace/coverage/default/17.clkmgr_smoke.3201445187
Short name	T529
Test name
Test status
Simulation time	86530881 ps
CPU time	1 seconds
Started	Apr 18 01:31:58 PM PDT 24
Finished	Apr 18 01:32:01 PM PDT 24
Peak memory	200576 kb
Host	smart-483428c7-c6d4-450b-9b99-5c780c09e209
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201445187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.3201445187
Directory	/workspace/17.clkmgr_smoke/latest

Test location	/workspace/coverage/default/17.clkmgr_stress_all.244398496
Short name	T416
Test name
Test status
Simulation time	1468229950 ps
CPU time	6.52 seconds
Started	Apr 18 01:32:01 PM PDT 24
Finished	Apr 18 01:32:09 PM PDT 24
Peak memory	200932 kb
Host	smart-0e4dd372-473b-4ede-b907-9e001e99358c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244398496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all.244398496
Directory	/workspace/17.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/17.clkmgr_stress_all_with_rand_reset.1790710305
Short name	T756
Test name
Test status
Simulation time	59792586987 ps
CPU time	355.18 seconds
Started	Apr 18 01:31:59 PM PDT 24
Finished	Apr 18 01:37:56 PM PDT 24
Peak memory	209212 kb
Host	smart-9927ab53-980e-452e-9e2e-24590d18806f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1790710305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.1790710305
Directory	/workspace/17.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.clkmgr_trans.294295820
Short name	T39
Test name
Test status
Simulation time	27825770 ps
CPU time	0.87 seconds
Started	Apr 18 01:31:55 PM PDT 24
Finished	Apr 18 01:31:59 PM PDT 24
Peak memory	200576 kb
Host	smart-9a5a3361-2e4c-4219-96b2-f422a1d48361
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294295820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.294295820
Directory	/workspace/17.clkmgr_trans/latest

Test location	/workspace/coverage/default/18.clkmgr_alert_test.3958504765
Short name	T363
Test name
Test status
Simulation time	64590545 ps
CPU time	0.85 seconds
Started	Apr 18 01:32:04 PM PDT 24
Finished	Apr 18 01:32:05 PM PDT 24
Peak memory	200472 kb
Host	smart-178e4c7c-25ee-4f90-a7f3-e134ca983a57
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958504765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk mgr_alert_test.3958504765
Directory	/workspace/18.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.2439836768
Short name	T845
Test name
Test status
Simulation time	18757795 ps
CPU time	0.78 seconds
Started	Apr 18 01:31:50 PM PDT 24
Finished	Apr 18 01:31:55 PM PDT 24
Peak memory	200540 kb
Host	smart-6c5c3338-ab82-4d12-9089-85f5bd4e8153
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439836768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_handshake_intersig_mubi.2439836768
Directory	/workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_clk_status.3964136475
Short name	T632
Test name
Test status
Simulation time	16960258 ps
CPU time	0.69 seconds
Started	Apr 18 01:32:04 PM PDT 24
Finished	Apr 18 01:32:06 PM PDT 24
Peak memory	200240 kb
Host	smart-b5da3363-b8f7-4559-823c-fe3213324153
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964136475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.3964136475
Directory	/workspace/18.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/18.clkmgr_div_intersig_mubi.3358948604
Short name	T579
Test name
Test status
Simulation time	37830360 ps
CPU time	0.8 seconds
Started	Apr 18 01:32:13 PM PDT 24
Finished	Apr 18 01:32:15 PM PDT 24
Peak memory	200556 kb
Host	smart-ca6125de-d726-40dc-afad-6dddac9ed9a7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358948604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_div_intersig_mubi.3358948604
Directory	/workspace/18.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_extclk.1874213548
Short name	T111
Test name
Test status
Simulation time	31905157 ps
CPU time	0.8 seconds
Started	Apr 18 01:32:00 PM PDT 24
Finished	Apr 18 01:32:02 PM PDT 24
Peak memory	200552 kb
Host	smart-9f1ab507-20f5-426a-b990-ece16c5b512e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874213548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.1874213548
Directory	/workspace/18.clkmgr_extclk/latest

Test location	/workspace/coverage/default/18.clkmgr_frequency.3270918595
Short name	T322
Test name
Test status
Simulation time	2246919658 ps
CPU time	12.02 seconds
Started	Apr 18 01:31:54 PM PDT 24
Finished	Apr 18 01:32:09 PM PDT 24
Peak memory	200844 kb
Host	smart-bc08e1f0-5dae-488c-a27f-449f33516eb9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270918595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.3270918595
Directory	/workspace/18.clkmgr_frequency/latest

Test location	/workspace/coverage/default/18.clkmgr_frequency_timeout.1257365620
Short name	T666
Test name
Test status
Simulation time	2194014454 ps
CPU time	8.65 seconds
Started	Apr 18 01:31:55 PM PDT 24
Finished	Apr 18 01:32:07 PM PDT 24
Peak memory	200868 kb
Host	smart-2752421a-672c-43da-9467-f739811ada2b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257365620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t imeout.1257365620
Directory	/workspace/18.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/18.clkmgr_idle_intersig_mubi.1306797760
Short name	T473
Test name
Test status
Simulation time	46580136 ps
CPU time	0.86 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:51 PM PDT 24
Peak memory	200440 kb
Host	smart-78896314-2f2e-4d1f-aee9-32410c8be109
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306797760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_idle_intersig_mubi.1306797760
Directory	/workspace/18.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.3202334858
Short name	T728
Test name
Test status
Simulation time	62452781 ps
CPU time	0.87 seconds
Started	Apr 18 01:31:55 PM PDT 24
Finished	Apr 18 01:31:59 PM PDT 24
Peak memory	200600 kb
Host	smart-579e6df0-dd72-4f0c-b0ea-59ba822616d1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202334858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 18.clkmgr_lc_clk_byp_req_intersig_mubi.3202334858
Directory	/workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.1839204787
Short name	T716
Test name
Test status
Simulation time	19789417 ps
CPU time	0.8 seconds
Started	Apr 18 01:31:58 PM PDT 24
Finished	Apr 18 01:32:01 PM PDT 24
Peak memory	200552 kb
Host	smart-d48a099f-b421-417e-8da4-8ba5db4adfac
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839204787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 18.clkmgr_lc_ctrl_intersig_mubi.1839204787
Directory	/workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_peri.4163180850
Short name	T306
Test name
Test status
Simulation time	14671002 ps
CPU time	0.74 seconds
Started	Apr 18 01:31:58 PM PDT 24
Finished	Apr 18 01:32:01 PM PDT 24
Peak memory	200276 kb
Host	smart-45ed6704-4453-42d1-bc23-3cb44048ba40
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163180850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.4163180850
Directory	/workspace/18.clkmgr_peri/latest

Test location	/workspace/coverage/default/18.clkmgr_regwen.3902477363
Short name	T515
Test name
Test status
Simulation time	450162698 ps
CPU time	3.14 seconds
Started	Apr 18 01:31:55 PM PDT 24
Finished	Apr 18 01:32:01 PM PDT 24
Peak memory	200696 kb
Host	smart-e4f7912d-fc57-44e1-9e9a-7c328b2099a3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902477363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.3902477363
Directory	/workspace/18.clkmgr_regwen/latest

Test location	/workspace/coverage/default/18.clkmgr_smoke.138005386
Short name	T134
Test name
Test status
Simulation time	73849833 ps
CPU time	0.98 seconds
Started	Apr 18 01:31:57 PM PDT 24
Finished	Apr 18 01:32:00 PM PDT 24
Peak memory	200568 kb
Host	smart-e9ce7976-e99b-4e8a-86bc-531a8021f340
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138005386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.138005386
Directory	/workspace/18.clkmgr_smoke/latest

Test location	/workspace/coverage/default/18.clkmgr_stress_all.4107304944
Short name	T570
Test name
Test status
Simulation time	5610567467 ps
CPU time	40.4 seconds
Started	Apr 18 01:32:07 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	200912 kb
Host	smart-2bc3c3b4-d554-401f-b3c3-dbc956b29368
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107304944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all.4107304944
Directory	/workspace/18.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.1894736920
Short name	T477
Test name
Test status
Simulation time	115893601358 ps
CPU time	714.03 seconds
Started	Apr 18 01:31:58 PM PDT 24
Finished	Apr 18 01:43:54 PM PDT 24
Peak memory	217420 kb
Host	smart-a4d85e24-fa07-439c-a172-35df1d8f6e2a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1894736920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.1894736920
Directory	/workspace/18.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.clkmgr_trans.3530917682
Short name	T552
Test name
Test status
Simulation time	39067982 ps
CPU time	1.06 seconds
Started	Apr 18 01:31:58 PM PDT 24
Finished	Apr 18 01:32:01 PM PDT 24
Peak memory	200488 kb
Host	smart-33de913a-130c-4e98-850e-99c8b0309f36
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530917682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.3530917682
Directory	/workspace/18.clkmgr_trans/latest

Test location	/workspace/coverage/default/19.clkmgr_alert_test.3902621845
Short name	T388
Test name
Test status
Simulation time	17601364 ps
CPU time	0.75 seconds
Started	Apr 18 01:32:21 PM PDT 24
Finished	Apr 18 01:32:23 PM PDT 24
Peak memory	200492 kb
Host	smart-7d4557a6-faab-4738-9fb3-60e7dc07bbbf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902621845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk mgr_alert_test.3902621845
Directory	/workspace/19.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.1439408385
Short name	T167
Test name
Test status
Simulation time	17234261 ps
CPU time	0.75 seconds
Started	Apr 18 01:31:56 PM PDT 24
Finished	Apr 18 01:31:59 PM PDT 24
Peak memory	200640 kb
Host	smart-53038234-04ce-4581-a72e-e1b3f6b7200f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439408385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_handshake_intersig_mubi.1439408385
Directory	/workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_clk_status.728278779
Short name	T744
Test name
Test status
Simulation time	78884865 ps
CPU time	0.82 seconds
Started	Apr 18 01:31:59 PM PDT 24
Finished	Apr 18 01:32:01 PM PDT 24
Peak memory	199500 kb
Host	smart-e2b28486-7295-48f9-9a46-f0774993ea3d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728278779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.728278779
Directory	/workspace/19.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/19.clkmgr_div_intersig_mubi.2902837542
Short name	T708
Test name
Test status
Simulation time	66753390 ps
CPU time	0.93 seconds
Started	Apr 18 01:31:56 PM PDT 24
Finished	Apr 18 01:31:59 PM PDT 24
Peak memory	200520 kb
Host	smart-83f0b999-15e5-4b39-8e3e-10b979955536
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902837542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_div_intersig_mubi.2902837542
Directory	/workspace/19.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_extclk.3212125375
Short name	T330
Test name
Test status
Simulation time	40454045 ps
CPU time	0.86 seconds
Started	Apr 18 01:32:11 PM PDT 24
Finished	Apr 18 01:32:12 PM PDT 24
Peak memory	200548 kb
Host	smart-da1af637-ff3b-49e0-8245-2a42808592c7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212125375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.3212125375
Directory	/workspace/19.clkmgr_extclk/latest

Test location	/workspace/coverage/default/19.clkmgr_frequency.2942338558
Short name	T571
Test name
Test status
Simulation time	799293846 ps
CPU time	4.89 seconds
Started	Apr 18 01:31:58 PM PDT 24
Finished	Apr 18 01:32:05 PM PDT 24
Peak memory	200628 kb
Host	smart-d94c6e5b-f7c4-4da7-9e05-fa3c505b1ab8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942338558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.2942338558
Directory	/workspace/19.clkmgr_frequency/latest

Test location	/workspace/coverage/default/19.clkmgr_frequency_timeout.80346531
Short name	T650
Test name
Test status
Simulation time	750124962 ps
CPU time	4.23 seconds
Started	Apr 18 01:31:55 PM PDT 24
Finished	Apr 18 01:32:02 PM PDT 24
Peak memory	200680 kb
Host	smart-22629d1f-7803-4a77-ad51-b8c027b8a340
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80346531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_tim eout.80346531
Directory	/workspace/19.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/19.clkmgr_idle_intersig_mubi.1861043879
Short name	T440
Test name
Test status
Simulation time	55816576 ps
CPU time	1.07 seconds
Started	Apr 18 01:32:07 PM PDT 24
Finished	Apr 18 01:32:09 PM PDT 24
Peak memory	200524 kb
Host	smart-a989edf0-13c0-483b-a06f-3bb75c236cb5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861043879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_idle_intersig_mubi.1861043879
Directory	/workspace/19.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.2056945900
Short name	T208
Test name
Test status
Simulation time	43080224 ps
CPU time	0.78 seconds
Started	Apr 18 01:32:12 PM PDT 24
Finished	Apr 18 01:32:13 PM PDT 24
Peak memory	200516 kb
Host	smart-481bc395-02b4-4eb3-ba27-ecd14ee8135d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056945900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 19.clkmgr_lc_clk_byp_req_intersig_mubi.2056945900
Directory	/workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.2698801108
Short name	T535
Test name
Test status
Simulation time	50390081 ps
CPU time	0.85 seconds
Started	Apr 18 01:31:59 PM PDT 24
Finished	Apr 18 01:32:01 PM PDT 24
Peak memory	200568 kb
Host	smart-f4b95665-bd87-4430-b1a7-778535178326
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698801108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 19.clkmgr_lc_ctrl_intersig_mubi.2698801108
Directory	/workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_peri.237453173
Short name	T357
Test name
Test status
Simulation time	15056822 ps
CPU time	0.74 seconds
Started	Apr 18 01:32:10 PM PDT 24
Finished	Apr 18 01:32:11 PM PDT 24
Peak memory	200268 kb
Host	smart-b3d2217b-0771-4b60-8fae-95fc638b4d01
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237453173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.237453173
Directory	/workspace/19.clkmgr_peri/latest

Test location	/workspace/coverage/default/19.clkmgr_regwen.2336845904
Short name	T372
Test name
Test status
Simulation time	571587122 ps
CPU time	3.63 seconds
Started	Apr 18 01:32:13 PM PDT 24
Finished	Apr 18 01:32:17 PM PDT 24
Peak memory	200512 kb
Host	smart-7a80865a-3918-4c4c-bd56-310650e65368
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336845904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.2336845904
Directory	/workspace/19.clkmgr_regwen/latest

Test location	/workspace/coverage/default/19.clkmgr_smoke.302123003
Short name	T787
Test name
Test status
Simulation time	60554471 ps
CPU time	0.96 seconds
Started	Apr 18 01:32:16 PM PDT 24
Finished	Apr 18 01:32:17 PM PDT 24
Peak memory	200612 kb
Host	smart-6134b415-aea4-4942-baef-151969e0042e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302123003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.302123003
Directory	/workspace/19.clkmgr_smoke/latest

Test location	/workspace/coverage/default/19.clkmgr_stress_all.638958404
Short name	T487
Test name
Test status
Simulation time	5685416883 ps
CPU time	22.57 seconds
Started	Apr 18 01:32:10 PM PDT 24
Finished	Apr 18 01:32:33 PM PDT 24
Peak memory	200896 kb
Host	smart-b424c844-370b-4225-81ce-2ed5b74782b3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638958404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all.638958404
Directory	/workspace/19.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/19.clkmgr_stress_all_with_rand_reset.181556742
Short name	T446
Test name
Test status
Simulation time	37941191196 ps
CPU time	350.66 seconds
Started	Apr 18 01:32:18 PM PDT 24
Finished	Apr 18 01:38:09 PM PDT 24
Peak memory	216740 kb
Host	smart-ebb0bb80-bf33-43a0-846d-49f6a1f6e24d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=181556742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.181556742
Directory	/workspace/19.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.clkmgr_trans.2698486560
Short name	T753
Test name
Test status
Simulation time	96620474 ps
CPU time	1.12 seconds
Started	Apr 18 01:32:17 PM PDT 24
Finished	Apr 18 01:32:18 PM PDT 24
Peak memory	200500 kb
Host	smart-6ac53203-55e1-4e93-9d1f-fa94fb379ba6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698486560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.2698486560
Directory	/workspace/19.clkmgr_trans/latest

Test location	/workspace/coverage/default/2.clkmgr_alert_test.1458897717
Short name	T600
Test name
Test status
Simulation time	48141675 ps
CPU time	0.83 seconds
Started	Apr 18 01:31:45 PM PDT 24
Finished	Apr 18 01:31:48 PM PDT 24
Peak memory	200488 kb
Host	smart-c4acc6ac-ce34-478f-9858-24f069060093
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458897717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkm gr_alert_test.1458897717
Directory	/workspace/2.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.2191428166
Short name	T697
Test name
Test status
Simulation time	68037704 ps
CPU time	0.93 seconds
Started	Apr 18 01:31:42 PM PDT 24
Finished	Apr 18 01:31:45 PM PDT 24
Peak memory	200600 kb
Host	smart-aa5328ce-4088-4378-a4c8-69abebf99ce6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191428166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_handshake_intersig_mubi.2191428166
Directory	/workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_clk_status.1681776504
Short name	T395
Test name
Test status
Simulation time	47037951 ps
CPU time	0.76 seconds
Started	Apr 18 01:31:45 PM PDT 24
Finished	Apr 18 01:31:48 PM PDT 24
Peak memory	200256 kb
Host	smart-76394300-fb4d-4250-80d4-e435635abe68
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681776504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.1681776504
Directory	/workspace/2.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/2.clkmgr_div_intersig_mubi.2630925843
Short name	T240
Test name
Test status
Simulation time	22175368 ps
CPU time	0.79 seconds
Started	Apr 18 01:31:36 PM PDT 24
Finished	Apr 18 01:31:38 PM PDT 24
Peak memory	200512 kb
Host	smart-eb055f58-c031-44d0-b04c-d297df2e9052
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630925843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_div_intersig_mubi.2630925843
Directory	/workspace/2.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_extclk.2226070278
Short name	T213
Test name
Test status
Simulation time	188631420 ps
CPU time	1.26 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:55 PM PDT 24
Peak memory	200560 kb
Host	smart-6b3861c6-6d37-4338-ae8c-56274cfa97d7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226070278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.2226070278
Directory	/workspace/2.clkmgr_extclk/latest

Test location	/workspace/coverage/default/2.clkmgr_frequency.3888051416
Short name	T119
Test name
Test status
Simulation time	1480688491 ps
CPU time	6.5 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:57 PM PDT 24
Peak memory	200640 kb
Host	smart-a56e6639-031d-49e0-a1de-510a381ba6b2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888051416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.3888051416
Directory	/workspace/2.clkmgr_frequency/latest

Test location	/workspace/coverage/default/2.clkmgr_frequency_timeout.2602732674
Short name	T381
Test name
Test status
Simulation time	1908430897 ps
CPU time	7.72 seconds
Started	Apr 18 01:31:45 PM PDT 24
Finished	Apr 18 01:31:55 PM PDT 24
Peak memory	200708 kb
Host	smart-83bb9206-3ad0-4995-904f-a4122bed259a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602732674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti meout.2602732674
Directory	/workspace/2.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/2.clkmgr_idle_intersig_mubi.2790297576
Short name	T539
Test name
Test status
Simulation time	19122262 ps
CPU time	0.79 seconds
Started	Apr 18 01:31:43 PM PDT 24
Finished	Apr 18 01:31:47 PM PDT 24
Peak memory	200552 kb
Host	smart-fb599340-8a8c-4f53-97f1-b969eb675a6c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790297576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_idle_intersig_mubi.2790297576
Directory	/workspace/2.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.1744259196
Short name	T83
Test name
Test status
Simulation time	35553574 ps
CPU time	0.87 seconds
Started	Apr 18 01:31:41 PM PDT 24
Finished	Apr 18 01:31:44 PM PDT 24
Peak memory	200588 kb
Host	smart-a7b1866f-1700-455c-83ae-198fbe36fcf3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744259196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.clkmgr_lc_clk_byp_req_intersig_mubi.1744259196
Directory	/workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.1713116913
Short name	T574
Test name
Test status
Simulation time	89568913 ps
CPU time	1.01 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200520 kb
Host	smart-3925f4e2-7330-41f9-82cc-1afb350c07ee
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713116913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.clkmgr_lc_ctrl_intersig_mubi.1713116913
Directory	/workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_peri.4264136187
Short name	T443
Test name
Test status
Simulation time	14696162 ps
CPU time	0.72 seconds
Started	Apr 18 01:31:43 PM PDT 24
Finished	Apr 18 01:31:46 PM PDT 24
Peak memory	200284 kb
Host	smart-ffc0724e-bde3-4796-86b9-1cb0fc61b74d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264136187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.4264136187
Directory	/workspace/2.clkmgr_peri/latest

Test location	/workspace/coverage/default/2.clkmgr_regwen.2068608447
Short name	T27
Test name
Test status
Simulation time	164692043 ps
CPU time	1.49 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:31:54 PM PDT 24
Peak memory	200520 kb
Host	smart-7b989163-9d85-4d26-9418-366a36fd8b92
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068608447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.2068608447
Directory	/workspace/2.clkmgr_regwen/latest

Test location	/workspace/coverage/default/2.clkmgr_sec_cm.3070533679
Short name	T38
Test name
Test status
Simulation time	537152446 ps
CPU time	3.42 seconds
Started	Apr 18 01:31:30 PM PDT 24
Finished	Apr 18 01:31:34 PM PDT 24
Peak memory	217496 kb
Host	smart-02aba72d-6582-479d-9356-09c0d2135722
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070533679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg r_sec_cm.3070533679
Directory	/workspace/2.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/2.clkmgr_smoke.3813744757
Short name	T281
Test name
Test status
Simulation time	15290733 ps
CPU time	0.79 seconds
Started	Apr 18 01:31:42 PM PDT 24
Finished	Apr 18 01:31:45 PM PDT 24
Peak memory	200584 kb
Host	smart-3f64f6c2-96fb-4478-9a85-6e6356c045b2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813744757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.3813744757
Directory	/workspace/2.clkmgr_smoke/latest

Test location	/workspace/coverage/default/2.clkmgr_stress_all.3047589874
Short name	T740
Test name
Test status
Simulation time	2657708899 ps
CPU time	13.33 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:32:06 PM PDT 24
Peak memory	200904 kb
Host	smart-0e2ed3ee-b272-4ce9-a5be-09f98872ba02
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047589874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all.3047589874
Directory	/workspace/2.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/2.clkmgr_stress_all_with_rand_reset.2180516628
Short name	T140
Test name
Test status
Simulation time	21073427991 ps
CPU time	313.87 seconds
Started	Apr 18 01:31:43 PM PDT 24
Finished	Apr 18 01:36:59 PM PDT 24
Peak memory	209196 kb
Host	smart-6034adca-369e-4b38-bacf-6d163569d980
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2180516628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.2180516628
Directory	/workspace/2.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.clkmgr_trans.1651249183
Short name	T267
Test name
Test status
Simulation time	34915892 ps
CPU time	0.93 seconds
Started	Apr 18 01:31:41 PM PDT 24
Finished	Apr 18 01:31:44 PM PDT 24
Peak memory	200540 kb
Host	smart-39561a3e-f90e-44d1-a8a6-7275b7cae4d9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651249183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.1651249183
Directory	/workspace/2.clkmgr_trans/latest

Test location	/workspace/coverage/default/20.clkmgr_alert_test.725844338
Short name	T168
Test name
Test status
Simulation time	88164474 ps
CPU time	1.03 seconds
Started	Apr 18 01:32:18 PM PDT 24
Finished	Apr 18 01:32:20 PM PDT 24
Peak memory	200436 kb
Host	smart-33f89e2a-a272-4803-93cb-0335bd0b1eac
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725844338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkm gr_alert_test.725844338
Directory	/workspace/20.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.4016185338
Short name	T585
Test name
Test status
Simulation time	15050508 ps
CPU time	0.8 seconds
Started	Apr 18 01:32:18 PM PDT 24
Finished	Apr 18 01:32:20 PM PDT 24
Peak memory	200504 kb
Host	smart-4b07344f-e473-4076-8f4d-af9da1ad2a4d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016185338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_handshake_intersig_mubi.4016185338
Directory	/workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_clk_status.1768752089
Short name	T368
Test name
Test status
Simulation time	12234295 ps
CPU time	0.72 seconds
Started	Apr 18 01:32:17 PM PDT 24
Finished	Apr 18 01:32:18 PM PDT 24
Peak memory	200168 kb
Host	smart-b19bc8f0-2e2b-432e-8518-a8e42c53986b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768752089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.1768752089
Directory	/workspace/20.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/20.clkmgr_div_intersig_mubi.1884373087
Short name	T195
Test name
Test status
Simulation time	43616750 ps
CPU time	0.94 seconds
Started	Apr 18 01:32:27 PM PDT 24
Finished	Apr 18 01:32:28 PM PDT 24
Peak memory	200480 kb
Host	smart-a5bb1aa2-1e92-4de6-9122-1ec902e2b40b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884373087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_div_intersig_mubi.1884373087
Directory	/workspace/20.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_extclk.1412535180
Short name	T568
Test name
Test status
Simulation time	19090106 ps
CPU time	0.83 seconds
Started	Apr 18 01:32:02 PM PDT 24
Finished	Apr 18 01:32:03 PM PDT 24
Peak memory	200528 kb
Host	smart-1af30e04-8b42-4e16-9809-65715612168c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412535180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.1412535180
Directory	/workspace/20.clkmgr_extclk/latest

Test location	/workspace/coverage/default/20.clkmgr_frequency.2713426335
Short name	T68
Test name
Test status
Simulation time	1285790207 ps
CPU time	7.82 seconds
Started	Apr 18 01:32:20 PM PDT 24
Finished	Apr 18 01:32:28 PM PDT 24
Peak memory	200564 kb
Host	smart-206f36c9-c082-4e22-94b6-6aac5d3bd0f7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713426335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.2713426335
Directory	/workspace/20.clkmgr_frequency/latest

Test location	/workspace/coverage/default/20.clkmgr_frequency_timeout.1409170126
Short name	T204
Test name
Test status
Simulation time	623593088 ps
CPU time	3.58 seconds
Started	Apr 18 01:32:04 PM PDT 24
Finished	Apr 18 01:32:08 PM PDT 24
Peak memory	200888 kb
Host	smart-6b3edbc5-1fad-4a61-8376-210cc41d102c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409170126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_t imeout.1409170126
Directory	/workspace/20.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/20.clkmgr_idle_intersig_mubi.3230395958
Short name	T162
Test name
Test status
Simulation time	47698246 ps
CPU time	1.06 seconds
Started	Apr 18 01:32:18 PM PDT 24
Finished	Apr 18 01:32:19 PM PDT 24
Peak memory	200544 kb
Host	smart-25fb328f-1a8b-4890-bf38-f60bfa7175c6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230395958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_idle_intersig_mubi.3230395958
Directory	/workspace/20.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.1145057176
Short name	T842
Test name
Test status
Simulation time	63779715 ps
CPU time	0.94 seconds
Started	Apr 18 01:32:01 PM PDT 24
Finished	Apr 18 01:32:03 PM PDT 24
Peak memory	200556 kb
Host	smart-180694ad-6181-47a9-a8b9-85f080b337bd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145057176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 20.clkmgr_lc_clk_byp_req_intersig_mubi.1145057176
Directory	/workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.1059350700
Short name	T393
Test name
Test status
Simulation time	22836068 ps
CPU time	0.83 seconds
Started	Apr 18 01:32:24 PM PDT 24
Finished	Apr 18 01:32:25 PM PDT 24
Peak memory	200580 kb
Host	smart-bcd42bc1-78b5-44d7-b862-a1c8baf4d7bf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059350700 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 20.clkmgr_lc_ctrl_intersig_mubi.1059350700
Directory	/workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_peri.2162522473
Short name	T308
Test name
Test status
Simulation time	79088726 ps
CPU time	0.93 seconds
Started	Apr 18 01:32:07 PM PDT 24
Finished	Apr 18 01:32:09 PM PDT 24
Peak memory	200288 kb
Host	smart-35592bf4-61e0-4844-8184-99f66a48b6a2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162522473 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.2162522473
Directory	/workspace/20.clkmgr_peri/latest

Test location	/workspace/coverage/default/20.clkmgr_regwen.1443898856
Short name	T583
Test name
Test status
Simulation time	307057453 ps
CPU time	1.89 seconds
Started	Apr 18 01:32:20 PM PDT 24
Finished	Apr 18 01:32:23 PM PDT 24
Peak memory	200552 kb
Host	smart-9fec408c-84ef-4082-b4bd-098d13792b3b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443898856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.1443898856
Directory	/workspace/20.clkmgr_regwen/latest

Test location	/workspace/coverage/default/20.clkmgr_smoke.2619282464
Short name	T754
Test name
Test status
Simulation time	24764356 ps
CPU time	0.84 seconds
Started	Apr 18 01:32:20 PM PDT 24
Finished	Apr 18 01:32:21 PM PDT 24
Peak memory	200584 kb
Host	smart-73d0af99-3efa-4ba2-a20b-448714c1c7cd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619282464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.2619282464
Directory	/workspace/20.clkmgr_smoke/latest

Test location	/workspace/coverage/default/20.clkmgr_stress_all.3866238252
Short name	T32
Test name
Test status
Simulation time	9029278335 ps
CPU time	30.66 seconds
Started	Apr 18 01:32:27 PM PDT 24
Finished	Apr 18 01:32:58 PM PDT 24
Peak memory	200964 kb
Host	smart-ac4fd7e3-fb82-436d-9dda-91f393437836
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866238252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all.3866238252
Directory	/workspace/20.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/20.clkmgr_stress_all_with_rand_reset.3190931571
Short name	T645
Test name
Test status
Simulation time	16830861214 ps
CPU time	233.16 seconds
Started	Apr 18 01:32:05 PM PDT 24
Finished	Apr 18 01:35:59 PM PDT 24
Peak memory	209256 kb
Host	smart-18013706-f4f6-4526-9417-f69abd599778
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3190931571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.3190931571
Directory	/workspace/20.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.clkmgr_trans.2837620573
Short name	T332
Test name
Test status
Simulation time	50750916 ps
CPU time	0.98 seconds
Started	Apr 18 01:32:18 PM PDT 24
Finished	Apr 18 01:32:20 PM PDT 24
Peak memory	200452 kb
Host	smart-10390ec2-5fae-4034-93e0-e11f42398ec2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837620573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.2837620573
Directory	/workspace/20.clkmgr_trans/latest

Test location	/workspace/coverage/default/21.clkmgr_alert_test.1520263986
Short name	T649
Test name
Test status
Simulation time	159799269 ps
CPU time	1.07 seconds
Started	Apr 18 01:32:24 PM PDT 24
Finished	Apr 18 01:32:25 PM PDT 24
Peak memory	200492 kb
Host	smart-cfd720f7-c32b-4ade-9b10-e010afdfc20a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520263986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clk mgr_alert_test.1520263986
Directory	/workspace/21.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.2581007809
Short name	T249
Test name
Test status
Simulation time	87073332 ps
CPU time	1.01 seconds
Started	Apr 18 01:32:18 PM PDT 24
Finished	Apr 18 01:32:20 PM PDT 24
Peak memory	200480 kb
Host	smart-8a2cbe8b-5ed5-4b6a-af33-a992403faeae
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581007809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_handshake_intersig_mubi.2581007809
Directory	/workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_clk_status.2820763888
Short name	T147
Test name
Test status
Simulation time	27029115 ps
CPU time	0.69 seconds
Started	Apr 18 01:32:33 PM PDT 24
Finished	Apr 18 01:32:34 PM PDT 24
Peak memory	199508 kb
Host	smart-1f772b74-0819-43c9-bf53-acebcd37e4d5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820763888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.2820763888
Directory	/workspace/21.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/21.clkmgr_div_intersig_mubi.1084003129
Short name	T559
Test name
Test status
Simulation time	61588402 ps
CPU time	0.96 seconds
Started	Apr 18 01:32:22 PM PDT 24
Finished	Apr 18 01:32:24 PM PDT 24
Peak memory	200508 kb
Host	smart-1e6e3317-3c5e-4691-8683-fe3906980a0b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084003129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_div_intersig_mubi.1084003129
Directory	/workspace/21.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_extclk.398232215
Short name	T41
Test name
Test status
Simulation time	18472974 ps
CPU time	0.71 seconds
Started	Apr 18 01:32:18 PM PDT 24
Finished	Apr 18 01:32:19 PM PDT 24
Peak memory	200512 kb
Host	smart-4049a5ae-227b-44c8-bb62-3a8af28f0a27
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398232215 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.398232215
Directory	/workspace/21.clkmgr_extclk/latest

Test location	/workspace/coverage/default/21.clkmgr_frequency.2908555606
Short name	T118
Test name
Test status
Simulation time	453498852 ps
CPU time	2.42 seconds
Started	Apr 18 01:32:23 PM PDT 24
Finished	Apr 18 01:32:26 PM PDT 24
Peak memory	200552 kb
Host	smart-f68e0ebb-4aae-4cfb-a7f9-521b5eb25e97
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908555606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.2908555606
Directory	/workspace/21.clkmgr_frequency/latest

Test location	/workspace/coverage/default/21.clkmgr_frequency_timeout.393246713
Short name	T628
Test name
Test status
Simulation time	1459795462 ps
CPU time	10.53 seconds
Started	Apr 18 01:32:32 PM PDT 24
Finished	Apr 18 01:32:43 PM PDT 24
Peak memory	200668 kb
Host	smart-a3770d92-5fcf-4b4c-b3aa-64cfef5ef1ca
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393246713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_ti meout.393246713
Directory	/workspace/21.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/21.clkmgr_idle_intersig_mubi.428328524
Short name	T500
Test name
Test status
Simulation time	51927449 ps
CPU time	0.85 seconds
Started	Apr 18 01:32:31 PM PDT 24
Finished	Apr 18 01:32:33 PM PDT 24
Peak memory	200524 kb
Host	smart-58f68a47-860f-40b4-9656-807695082c38
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428328524 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.clkmgr_idle_intersig_mubi.428328524
Directory	/workspace/21.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.2674865831
Short name	T523
Test name
Test status
Simulation time	34248400 ps
CPU time	0.89 seconds
Started	Apr 18 01:32:25 PM PDT 24
Finished	Apr 18 01:32:27 PM PDT 24
Peak memory	200536 kb
Host	smart-b5339a4d-d0da-425a-9a95-ee725196d312
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674865831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 21.clkmgr_lc_clk_byp_req_intersig_mubi.2674865831
Directory	/workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.1125851088
Short name	T353
Test name
Test status
Simulation time	68832149 ps
CPU time	0.97 seconds
Started	Apr 18 01:32:32 PM PDT 24
Finished	Apr 18 01:32:34 PM PDT 24
Peak memory	200584 kb
Host	smart-78de5f5a-a210-4bc8-a875-7e7c874947a6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125851088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 21.clkmgr_lc_ctrl_intersig_mubi.1125851088
Directory	/workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_peri.2400039611
Short name	T820
Test name
Test status
Simulation time	19090027 ps
CPU time	0.81 seconds
Started	Apr 18 01:32:28 PM PDT 24
Finished	Apr 18 01:32:30 PM PDT 24
Peak memory	200292 kb
Host	smart-30af6528-aeff-45cc-9ec7-4f9559212dce
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400039611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.2400039611
Directory	/workspace/21.clkmgr_peri/latest

Test location	/workspace/coverage/default/21.clkmgr_regwen.2881733198
Short name	T631
Test name
Test status
Simulation time	1389304803 ps
CPU time	5.75 seconds
Started	Apr 18 01:32:32 PM PDT 24
Finished	Apr 18 01:32:39 PM PDT 24
Peak memory	200700 kb
Host	smart-9bf72e36-07ae-47d5-bd60-74c64fdb111a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881733198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.2881733198
Directory	/workspace/21.clkmgr_regwen/latest

Test location	/workspace/coverage/default/21.clkmgr_smoke.3763289762
Short name	T261
Test name
Test status
Simulation time	82712113 ps
CPU time	1.07 seconds
Started	Apr 18 01:32:11 PM PDT 24
Finished	Apr 18 01:32:13 PM PDT 24
Peak memory	200584 kb
Host	smart-d389086c-9161-4a7a-a525-29ca22d81152
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763289762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.3763289762
Directory	/workspace/21.clkmgr_smoke/latest

Test location	/workspace/coverage/default/21.clkmgr_stress_all.4126021645
Short name	T667
Test name
Test status
Simulation time	12197580918 ps
CPU time	85.79 seconds
Started	Apr 18 01:32:18 PM PDT 24
Finished	Apr 18 01:33:44 PM PDT 24
Peak memory	201144 kb
Host	smart-faf88208-96d0-423f-9683-ecf11dc44dfc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126021645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all.4126021645
Directory	/workspace/21.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/21.clkmgr_stress_all_with_rand_reset.1869724827
Short name	T160
Test name
Test status
Simulation time	58780498141 ps
CPU time	553.26 seconds
Started	Apr 18 01:32:24 PM PDT 24
Finished	Apr 18 01:41:38 PM PDT 24
Peak memory	217412 kb
Host	smart-9dbe0975-9083-4fe5-846f-237692b0542d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1869724827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.1869724827
Directory	/workspace/21.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.clkmgr_trans.2852236450
Short name	T485
Test name
Test status
Simulation time	31361828 ps
CPU time	0.91 seconds
Started	Apr 18 01:32:29 PM PDT 24
Finished	Apr 18 01:32:31 PM PDT 24
Peak memory	200556 kb
Host	smart-0f19afc4-be54-4191-87fc-ae27d6ab4168
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852236450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.2852236450
Directory	/workspace/21.clkmgr_trans/latest

Test location	/workspace/coverage/default/22.clkmgr_alert_test.759878866
Short name	T696
Test name
Test status
Simulation time	15288957 ps
CPU time	0.79 seconds
Started	Apr 18 01:32:32 PM PDT 24
Finished	Apr 18 01:32:34 PM PDT 24
Peak memory	200508 kb
Host	smart-461c1b06-912e-48fb-853e-6ab5cb30fddf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759878866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkm gr_alert_test.759878866
Directory	/workspace/22.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.782492539
Short name	T520
Test name
Test status
Simulation time	25593181 ps
CPU time	0.87 seconds
Started	Apr 18 01:32:17 PM PDT 24
Finished	Apr 18 01:32:19 PM PDT 24
Peak memory	200552 kb
Host	smart-5adad2e7-0d5d-4a3b-b247-2ca0ae8e4835
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782492539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_handshake_intersig_mubi.782492539
Directory	/workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_clk_status.1350352079
Short name	T151
Test name
Test status
Simulation time	39386010 ps
CPU time	0.73 seconds
Started	Apr 18 01:32:13 PM PDT 24
Finished	Apr 18 01:32:14 PM PDT 24
Peak memory	199464 kb
Host	smart-2f201a5b-a366-4d52-9220-1f3118c1109e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350352079 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.1350352079
Directory	/workspace/22.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/22.clkmgr_div_intersig_mubi.3380428452
Short name	T418
Test name
Test status
Simulation time	28603957 ps
CPU time	0.88 seconds
Started	Apr 18 01:32:40 PM PDT 24
Finished	Apr 18 01:32:44 PM PDT 24
Peak memory	200576 kb
Host	smart-dd7eb778-db08-4a0d-8ed3-824dbcde28ae
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380428452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_div_intersig_mubi.3380428452
Directory	/workspace/22.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_extclk.4180585592
Short name	T268
Test name
Test status
Simulation time	151828972 ps
CPU time	1.19 seconds
Started	Apr 18 01:32:30 PM PDT 24
Finished	Apr 18 01:32:32 PM PDT 24
Peak memory	200576 kb
Host	smart-aafdabab-5cfd-4037-a17c-cf13b1159ebc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180585592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.4180585592
Directory	/workspace/22.clkmgr_extclk/latest

Test location	/workspace/coverage/default/22.clkmgr_frequency.314910128
Short name	T8
Test name
Test status
Simulation time	2482743721 ps
CPU time	19.04 seconds
Started	Apr 18 01:32:24 PM PDT 24
Finished	Apr 18 01:32:43 PM PDT 24
Peak memory	200856 kb
Host	smart-bbe36911-9eb7-4bb7-87a3-96444412b43a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314910128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.314910128
Directory	/workspace/22.clkmgr_frequency/latest

Test location	/workspace/coverage/default/22.clkmgr_frequency_timeout.3970767362
Short name	T525
Test name
Test status
Simulation time	656994581 ps
CPU time	3.2 seconds
Started	Apr 18 01:32:33 PM PDT 24
Finished	Apr 18 01:32:37 PM PDT 24
Peak memory	200736 kb
Host	smart-70ba593c-1418-4650-8dcc-8b3ec415c017
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970767362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_t imeout.3970767362
Directory	/workspace/22.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/22.clkmgr_idle_intersig_mubi.2966478742
Short name	T575
Test name
Test status
Simulation time	83538746 ps
CPU time	1.05 seconds
Started	Apr 18 01:32:36 PM PDT 24
Finished	Apr 18 01:32:38 PM PDT 24
Peak memory	200564 kb
Host	smart-66e7cc67-060e-4803-86d7-d0e312cc8e9a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966478742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_idle_intersig_mubi.2966478742
Directory	/workspace/22.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.3238237212
Short name	T207
Test name
Test status
Simulation time	101011471 ps
CPU time	0.99 seconds
Started	Apr 18 01:32:11 PM PDT 24
Finished	Apr 18 01:32:13 PM PDT 24
Peak memory	200580 kb
Host	smart-490dc7ae-55ec-402d-9dea-2677e745dd3e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238237212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 22.clkmgr_lc_clk_byp_req_intersig_mubi.3238237212
Directory	/workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.4148833852
Short name	T430
Test name
Test status
Simulation time	76035208 ps
CPU time	0.99 seconds
Started	Apr 18 01:32:27 PM PDT 24
Finished	Apr 18 01:32:29 PM PDT 24
Peak memory	200580 kb
Host	smart-e6f55f5b-fc3e-462b-9a45-4082c0453a04
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148833852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 22.clkmgr_lc_ctrl_intersig_mubi.4148833852
Directory	/workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_peri.205965454
Short name	T460
Test name
Test status
Simulation time	33732898 ps
CPU time	0.83 seconds
Started	Apr 18 01:32:33 PM PDT 24
Finished	Apr 18 01:32:35 PM PDT 24
Peak memory	200228 kb
Host	smart-dba2cf4a-c004-4754-aa87-8508e208bc70
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205965454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.205965454
Directory	/workspace/22.clkmgr_peri/latest

Test location	/workspace/coverage/default/22.clkmgr_regwen.601877667
Short name	T773
Test name
Test status
Simulation time	220080130 ps
CPU time	1.49 seconds
Started	Apr 18 01:32:26 PM PDT 24
Finished	Apr 18 01:32:28 PM PDT 24
Peak memory	200520 kb
Host	smart-20107b85-6f4c-4ad6-b19c-6aa0c8de10c3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601877667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.601877667
Directory	/workspace/22.clkmgr_regwen/latest

Test location	/workspace/coverage/default/22.clkmgr_smoke.2805838839
Short name	T304
Test name
Test status
Simulation time	39757418 ps
CPU time	0.88 seconds
Started	Apr 18 01:32:37 PM PDT 24
Finished	Apr 18 01:32:39 PM PDT 24
Peak memory	200584 kb
Host	smart-b73ffc7e-6786-4676-9d2c-82871fc25c73
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805838839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.2805838839
Directory	/workspace/22.clkmgr_smoke/latest

Test location	/workspace/coverage/default/22.clkmgr_stress_all.173562390
Short name	T2
Test name
Test status
Simulation time	6874112415 ps
CPU time	47.74 seconds
Started	Apr 18 01:32:16 PM PDT 24
Finished	Apr 18 01:33:04 PM PDT 24
Peak memory	200912 kb
Host	smart-46d6c1c4-7771-4844-aa73-6e7ee09dd7e2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173562390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all.173562390
Directory	/workspace/22.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/22.clkmgr_stress_all_with_rand_reset.1864090150
Short name	T139
Test name
Test status
Simulation time	44479259001 ps
CPU time	656.69 seconds
Started	Apr 18 01:32:22 PM PDT 24
Finished	Apr 18 01:43:19 PM PDT 24
Peak memory	209196 kb
Host	smart-ed2a8ab4-cf17-4029-a028-4bad26b8af02
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1864090150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.1864090150
Directory	/workspace/22.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.clkmgr_trans.379737903
Short name	T482
Test name
Test status
Simulation time	39525818 ps
CPU time	1.06 seconds
Started	Apr 18 01:32:17 PM PDT 24
Finished	Apr 18 01:32:19 PM PDT 24
Peak memory	200584 kb
Host	smart-cf9e2326-8635-438e-9f39-6d0dba3536eb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379737903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.379737903
Directory	/workspace/22.clkmgr_trans/latest

Test location	/workspace/coverage/default/23.clkmgr_alert_test.3634278387
Short name	T528
Test name
Test status
Simulation time	37824991 ps
CPU time	0.84 seconds
Started	Apr 18 01:32:37 PM PDT 24
Finished	Apr 18 01:32:40 PM PDT 24
Peak memory	200476 kb
Host	smart-89f8821c-07d1-49c1-bf75-fd78124fa98f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634278387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk mgr_alert_test.3634278387
Directory	/workspace/23.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.3752828324
Short name	T709
Test name
Test status
Simulation time	18469348 ps
CPU time	0.77 seconds
Started	Apr 18 01:32:22 PM PDT 24
Finished	Apr 18 01:32:24 PM PDT 24
Peak memory	200600 kb
Host	smart-9af0d813-5850-40d3-afa7-1738290b8032
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752828324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_handshake_intersig_mubi.3752828324
Directory	/workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_clk_status.1959124680
Short name	T149
Test name
Test status
Simulation time	14881752 ps
CPU time	0.71 seconds
Started	Apr 18 01:32:33 PM PDT 24
Finished	Apr 18 01:32:35 PM PDT 24
Peak memory	199584 kb
Host	smart-4b4ed622-fbd3-499b-83d4-bd7aa48a3878
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959124680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.1959124680
Directory	/workspace/23.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/23.clkmgr_div_intersig_mubi.1837689225
Short name	T816
Test name
Test status
Simulation time	80165032 ps
CPU time	1.03 seconds
Started	Apr 18 01:32:31 PM PDT 24
Finished	Apr 18 01:32:33 PM PDT 24
Peak memory	200620 kb
Host	smart-25276092-3ee9-4a52-9caf-c591dc2c8642
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837689225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_div_intersig_mubi.1837689225
Directory	/workspace/23.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_extclk.3750606872
Short name	T42
Test name
Test status
Simulation time	23386446 ps
CPU time	0.85 seconds
Started	Apr 18 01:32:34 PM PDT 24
Finished	Apr 18 01:32:36 PM PDT 24
Peak memory	200504 kb
Host	smart-241cc4e8-c37c-41f6-a3bb-e492b3523428
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750606872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.3750606872
Directory	/workspace/23.clkmgr_extclk/latest

Test location	/workspace/coverage/default/23.clkmgr_frequency.3073820319
Short name	T445
Test name
Test status
Simulation time	2000984731 ps
CPU time	14.96 seconds
Started	Apr 18 01:32:21 PM PDT 24
Finished	Apr 18 01:32:36 PM PDT 24
Peak memory	200744 kb
Host	smart-6d5627c3-b790-4199-a794-b9a858c81439
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073820319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.3073820319
Directory	/workspace/23.clkmgr_frequency/latest

Test location	/workspace/coverage/default/23.clkmgr_frequency_timeout.2298072349
Short name	T17
Test name
Test status
Simulation time	1938601144 ps
CPU time	14.27 seconds
Started	Apr 18 01:32:31 PM PDT 24
Finished	Apr 18 01:32:46 PM PDT 24
Peak memory	200700 kb
Host	smart-fdc480d3-426b-4066-addf-1bc7c00144c6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298072349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_t imeout.2298072349
Directory	/workspace/23.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/23.clkmgr_idle_intersig_mubi.2512368333
Short name	T434
Test name
Test status
Simulation time	20730569 ps
CPU time	0.82 seconds
Started	Apr 18 01:32:33 PM PDT 24
Finished	Apr 18 01:32:35 PM PDT 24
Peak memory	200588 kb
Host	smart-0b5fa053-037e-4fe0-aeec-ae349065c2dd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512368333 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_idle_intersig_mubi.2512368333
Directory	/workspace/23.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.4077571810
Short name	T263
Test name
Test status
Simulation time	81709120 ps
CPU time	0.98 seconds
Started	Apr 18 01:32:20 PM PDT 24
Finished	Apr 18 01:32:22 PM PDT 24
Peak memory	200580 kb
Host	smart-ca4eb89c-3547-43b2-a182-dff2bc66cb6c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077571810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 23.clkmgr_lc_clk_byp_req_intersig_mubi.4077571810
Directory	/workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.786400360
Short name	T784
Test name
Test status
Simulation time	55297932 ps
CPU time	0.98 seconds
Started	Apr 18 01:32:30 PM PDT 24
Finished	Apr 18 01:32:31 PM PDT 24
Peak memory	200548 kb
Host	smart-53e3f64c-98e4-4df0-988c-cb254b908b02
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786400360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 23.clkmgr_lc_ctrl_intersig_mubi.786400360
Directory	/workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_peri.3968688968
Short name	T611
Test name
Test status
Simulation time	40743306 ps
CPU time	0.79 seconds
Started	Apr 18 01:32:27 PM PDT 24
Finished	Apr 18 01:32:29 PM PDT 24
Peak memory	200284 kb
Host	smart-cfb0d5b2-bfb2-4744-8266-bde879a04986
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968688968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.3968688968
Directory	/workspace/23.clkmgr_peri/latest

Test location	/workspace/coverage/default/23.clkmgr_regwen.733451214
Short name	T287
Test name
Test status
Simulation time	674981438 ps
CPU time	4.14 seconds
Started	Apr 18 01:32:33 PM PDT 24
Finished	Apr 18 01:32:38 PM PDT 24
Peak memory	200728 kb
Host	smart-fcc002e7-ec57-4a39-b0e9-daca02bde3f9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733451214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.733451214
Directory	/workspace/23.clkmgr_regwen/latest

Test location	/workspace/coverage/default/23.clkmgr_smoke.1583000217
Short name	T840
Test name
Test status
Simulation time	40632317 ps
CPU time	0.87 seconds
Started	Apr 18 01:32:33 PM PDT 24
Finished	Apr 18 01:32:35 PM PDT 24
Peak memory	200568 kb
Host	smart-2b2143d3-eb9d-4553-b9aa-eb8d50cc91f6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583000217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.1583000217
Directory	/workspace/23.clkmgr_smoke/latest

Test location	/workspace/coverage/default/23.clkmgr_stress_all.1353427307
Short name	T671
Test name
Test status
Simulation time	1636604636 ps
CPU time	6.63 seconds
Started	Apr 18 01:32:29 PM PDT 24
Finished	Apr 18 01:32:36 PM PDT 24
Peak memory	200688 kb
Host	smart-be2f9460-5810-4ee9-a7dd-afe7f99b9b22
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353427307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all.1353427307
Directory	/workspace/23.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/23.clkmgr_stress_all_with_rand_reset.945860762
Short name	T486
Test name
Test status
Simulation time	37241544505 ps
CPU time	347.77 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:38:28 PM PDT 24
Peak memory	217452 kb
Host	smart-160d0f88-0395-43d5-9eb7-f1e557a0bb8a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=945860762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.945860762
Directory	/workspace/23.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.clkmgr_trans.83170576
Short name	T265
Test name
Test status
Simulation time	69426658 ps
CPU time	0.95 seconds
Started	Apr 18 01:32:29 PM PDT 24
Finished	Apr 18 01:32:31 PM PDT 24
Peak memory	200520 kb
Host	smart-25cf5b53-4920-4705-a020-e0948b75d8c7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83170576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.83170576
Directory	/workspace/23.clkmgr_trans/latest

Test location	/workspace/coverage/default/24.clkmgr_alert_test.4197663912
Short name	T200
Test name
Test status
Simulation time	16084220 ps
CPU time	0.8 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:47 PM PDT 24
Peak memory	200100 kb
Host	smart-ee64973e-e6cc-4f47-8cd1-e7c525f96b45
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197663912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk mgr_alert_test.4197663912
Directory	/workspace/24.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.2499136959
Short name	T685
Test name
Test status
Simulation time	197099544 ps
CPU time	1.32 seconds
Started	Apr 18 01:32:29 PM PDT 24
Finished	Apr 18 01:32:31 PM PDT 24
Peak memory	200564 kb
Host	smart-c1f32cbe-9072-4e10-a8e4-cafcb979be58
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499136959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_handshake_intersig_mubi.2499136959
Directory	/workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_clk_status.2081828144
Short name	T807
Test name
Test status
Simulation time	15881361 ps
CPU time	0.7 seconds
Started	Apr 18 01:32:40 PM PDT 24
Finished	Apr 18 01:32:43 PM PDT 24
Peak memory	199508 kb
Host	smart-10e025c7-ecca-4a6a-ae37-ddba59732f14
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081828144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.2081828144
Directory	/workspace/24.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/24.clkmgr_div_intersig_mubi.1244083569
Short name	T402
Test name
Test status
Simulation time	41618382 ps
CPU time	0.78 seconds
Started	Apr 18 01:32:30 PM PDT 24
Finished	Apr 18 01:32:32 PM PDT 24
Peak memory	200552 kb
Host	smart-0b2dc96c-0b8e-4bd4-9641-d70efa214847
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244083569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_div_intersig_mubi.1244083569
Directory	/workspace/24.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_extclk.3938392414
Short name	T777
Test name
Test status
Simulation time	56905584 ps
CPU time	0.95 seconds
Started	Apr 18 01:32:21 PM PDT 24
Finished	Apr 18 01:32:23 PM PDT 24
Peak memory	200512 kb
Host	smart-80ed2d5f-a1fa-428a-b1e6-73662f6ed75a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938392414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.3938392414
Directory	/workspace/24.clkmgr_extclk/latest

Test location	/workspace/coverage/default/24.clkmgr_frequency.935536300
Short name	T371
Test name
Test status
Simulation time	1160715262 ps
CPU time	9.06 seconds
Started	Apr 18 01:32:35 PM PDT 24
Finished	Apr 18 01:32:45 PM PDT 24
Peak memory	200580 kb
Host	smart-dc2802f7-57c1-4baf-91fb-b13f1fe913a1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935536300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.935536300
Directory	/workspace/24.clkmgr_frequency/latest

Test location	/workspace/coverage/default/24.clkmgr_frequency_timeout.2125901153
Short name	T695
Test name
Test status
Simulation time	643668999 ps
CPU time	3.12 seconds
Started	Apr 18 01:32:33 PM PDT 24
Finished	Apr 18 01:32:37 PM PDT 24
Peak memory	200616 kb
Host	smart-72173e7f-067e-4f3f-b340-5695fbb5e2be
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125901153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t imeout.2125901153
Directory	/workspace/24.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/24.clkmgr_idle_intersig_mubi.2618551163
Short name	T722
Test name
Test status
Simulation time	24810723 ps
CPU time	0.79 seconds
Started	Apr 18 01:32:34 PM PDT 24
Finished	Apr 18 01:32:36 PM PDT 24
Peak memory	200512 kb
Host	smart-a1390f80-4751-4770-8b22-282156a00029
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618551163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_idle_intersig_mubi.2618551163
Directory	/workspace/24.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.952788802
Short name	T248
Test name
Test status
Simulation time	69261610 ps
CPU time	0.99 seconds
Started	Apr 18 01:32:31 PM PDT 24
Finished	Apr 18 01:32:32 PM PDT 24
Peak memory	200576 kb
Host	smart-744e8263-ef2b-40a6-9d9c-ff44af402579
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952788802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 24.clkmgr_lc_clk_byp_req_intersig_mubi.952788802
Directory	/workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.2494276441
Short name	T621
Test name
Test status
Simulation time	71239705 ps
CPU time	0.98 seconds
Started	Apr 18 01:32:33 PM PDT 24
Finished	Apr 18 01:32:35 PM PDT 24
Peak memory	200620 kb
Host	smart-b7b18c25-c693-445f-b041-f88a650cc4d8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494276441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 24.clkmgr_lc_ctrl_intersig_mubi.2494276441
Directory	/workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_peri.2017765464
Short name	T202
Test name
Test status
Simulation time	23924203 ps
CPU time	0.79 seconds
Started	Apr 18 01:32:22 PM PDT 24
Finished	Apr 18 01:32:24 PM PDT 24
Peak memory	200300 kb
Host	smart-778835af-06d2-4ac3-8b8b-a0dd16b5042a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017765464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.2017765464
Directory	/workspace/24.clkmgr_peri/latest

Test location	/workspace/coverage/default/24.clkmgr_regwen.3106043230
Short name	T846
Test name
Test status
Simulation time	1893609923 ps
CPU time	6.07 seconds
Started	Apr 18 01:32:35 PM PDT 24
Finished	Apr 18 01:32:42 PM PDT 24
Peak memory	200720 kb
Host	smart-4da6802b-d9c1-4af2-930d-7ce444820ae5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106043230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.3106043230
Directory	/workspace/24.clkmgr_regwen/latest

Test location	/workspace/coverage/default/24.clkmgr_smoke.2316028755
Short name	T132
Test name
Test status
Simulation time	84757592 ps
CPU time	0.99 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:49 PM PDT 24
Peak memory	200592 kb
Host	smart-15ca0745-cc37-4f89-ac35-aab7a86b28b8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316028755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.2316028755
Directory	/workspace/24.clkmgr_smoke/latest

Test location	/workspace/coverage/default/24.clkmgr_stress_all.1704627354
Short name	T239
Test name
Test status
Simulation time	181245833 ps
CPU time	1.45 seconds
Started	Apr 18 01:32:35 PM PDT 24
Finished	Apr 18 01:32:38 PM PDT 24
Peak memory	200524 kb
Host	smart-e02c65ed-3655-41de-b187-8e734f7f572b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704627354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all.1704627354
Directory	/workspace/24.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/24.clkmgr_stress_all_with_rand_reset.2977900048
Short name	T789
Test name
Test status
Simulation time	74507047300 ps
CPU time	420.85 seconds
Started	Apr 18 01:32:31 PM PDT 24
Finished	Apr 18 01:39:33 PM PDT 24
Peak memory	209236 kb
Host	smart-ab53b136-9610-433c-87f1-18c10c1c2802
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2977900048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.2977900048
Directory	/workspace/24.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.clkmgr_trans.632213176
Short name	T394
Test name
Test status
Simulation time	129543576 ps
CPU time	1.24 seconds
Started	Apr 18 01:32:24 PM PDT 24
Finished	Apr 18 01:32:26 PM PDT 24
Peak memory	200488 kb
Host	smart-69e6b326-a6b9-423c-a69b-d2dc64d7afda
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632213176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.632213176
Directory	/workspace/24.clkmgr_trans/latest

Test location	/workspace/coverage/default/25.clkmgr_alert_test.708319311
Short name	T164
Test name
Test status
Simulation time	21214166 ps
CPU time	0.74 seconds
Started	Apr 18 01:32:38 PM PDT 24
Finished	Apr 18 01:32:40 PM PDT 24
Peak memory	200628 kb
Host	smart-0ad9cb63-f7a5-4276-9ad1-b8348fbca65e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708319311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkm gr_alert_test.708319311
Directory	/workspace/25.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.4003983850
Short name	T219
Test name
Test status
Simulation time	20630584 ps
CPU time	0.74 seconds
Started	Apr 18 01:32:29 PM PDT 24
Finished	Apr 18 01:32:30 PM PDT 24
Peak memory	200472 kb
Host	smart-bbaa5729-5cd6-4856-ac7b-34f0c58c213b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003983850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_handshake_intersig_mubi.4003983850
Directory	/workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_clk_status.913606994
Short name	T150
Test name
Test status
Simulation time	34468537 ps
CPU time	0.76 seconds
Started	Apr 18 01:32:32 PM PDT 24
Finished	Apr 18 01:32:34 PM PDT 24
Peak memory	200240 kb
Host	smart-7c4200c5-dae7-4d03-bee9-8a5977cf46d3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913606994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.913606994
Directory	/workspace/25.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/25.clkmgr_div_intersig_mubi.3230775798
Short name	T458
Test name
Test status
Simulation time	65083884 ps
CPU time	0.91 seconds
Started	Apr 18 01:32:34 PM PDT 24
Finished	Apr 18 01:32:35 PM PDT 24
Peak memory	200552 kb
Host	smart-084e9be9-e0bf-4089-bb60-e383e5f7dcf9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230775798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_div_intersig_mubi.3230775798
Directory	/workspace/25.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_extclk.541348574
Short name	T235
Test name
Test status
Simulation time	41756868 ps
CPU time	0.9 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:32:42 PM PDT 24
Peak memory	200544 kb
Host	smart-53e431e5-ca4f-4272-84e8-d7bb1d0f80e3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541348574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.541348574
Directory	/workspace/25.clkmgr_extclk/latest

Test location	/workspace/coverage/default/25.clkmgr_frequency.3692391485
Short name	T255
Test name
Test status
Simulation time	1041786300 ps
CPU time	6.02 seconds
Started	Apr 18 01:32:35 PM PDT 24
Finished	Apr 18 01:32:42 PM PDT 24
Peak memory	200564 kb
Host	smart-0aa9d464-f17d-4c40-9e04-39d2ab47358a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692391485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.3692391485
Directory	/workspace/25.clkmgr_frequency/latest

Test location	/workspace/coverage/default/25.clkmgr_frequency_timeout.417037308
Short name	T62
Test name
Test status
Simulation time	1974168563 ps
CPU time	6.47 seconds
Started	Apr 18 01:32:24 PM PDT 24
Finished	Apr 18 01:32:31 PM PDT 24
Peak memory	200700 kb
Host	smart-42f50196-9031-45d5-b66f-911a82403bb3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417037308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_ti meout.417037308
Directory	/workspace/25.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/25.clkmgr_idle_intersig_mubi.1480656023
Short name	T712
Test name
Test status
Simulation time	35872259 ps
CPU time	0.98 seconds
Started	Apr 18 01:32:40 PM PDT 24
Finished	Apr 18 01:32:50 PM PDT 24
Peak memory	200440 kb
Host	smart-1623381d-c3b1-48ed-8da3-cf5116db8e34
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480656023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_idle_intersig_mubi.1480656023
Directory	/workspace/25.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.3596028401
Short name	T592
Test name
Test status
Simulation time	12774202 ps
CPU time	0.77 seconds
Started	Apr 18 01:32:38 PM PDT 24
Finished	Apr 18 01:32:41 PM PDT 24
Peak memory	200560 kb
Host	smart-b1460f96-c707-4e1c-8b91-975add0d22af
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596028401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 25.clkmgr_lc_clk_byp_req_intersig_mubi.3596028401
Directory	/workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.4284833925
Short name	T626
Test name
Test status
Simulation time	26320001 ps
CPU time	0.73 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:46 PM PDT 24
Peak memory	200500 kb
Host	smart-c24002bb-8793-4352-855c-e20ef1ac4709
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284833925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 25.clkmgr_lc_ctrl_intersig_mubi.4284833925
Directory	/workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_peri.3147879494
Short name	T588
Test name
Test status
Simulation time	68023127 ps
CPU time	0.88 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:32:42 PM PDT 24
Peak memory	200280 kb
Host	smart-45ebf9d1-c22d-44f9-8a0f-23939bf54dbe
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147879494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.3147879494
Directory	/workspace/25.clkmgr_peri/latest

Test location	/workspace/coverage/default/25.clkmgr_regwen.2982821241
Short name	T718
Test name
Test status
Simulation time	134024178 ps
CPU time	1.01 seconds
Started	Apr 18 01:32:36 PM PDT 24
Finished	Apr 18 01:32:38 PM PDT 24
Peak memory	200512 kb
Host	smart-a274c948-8924-432d-8ed8-92e49e2a00bd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982821241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.2982821241
Directory	/workspace/25.clkmgr_regwen/latest

Test location	/workspace/coverage/default/25.clkmgr_smoke.3740576134
Short name	T433
Test name
Test status
Simulation time	260400046 ps
CPU time	1.46 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:45 PM PDT 24
Peak memory	200504 kb
Host	smart-7618034c-c6d6-48c1-8144-fc677dbdaf0a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740576134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.3740576134
Directory	/workspace/25.clkmgr_smoke/latest

Test location	/workspace/coverage/default/25.clkmgr_stress_all.671324043
Short name	T755
Test name
Test status
Simulation time	255403400 ps
CPU time	1.69 seconds
Started	Apr 18 01:32:32 PM PDT 24
Finished	Apr 18 01:32:35 PM PDT 24
Peak memory	200636 kb
Host	smart-7b1ca751-e819-4503-bcd8-3eba5e2d98db
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671324043 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all.671324043
Directory	/workspace/25.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/25.clkmgr_stress_all_with_rand_reset.3060826533
Short name	T838
Test name
Test status
Simulation time	139069812401 ps
CPU time	792.1 seconds
Started	Apr 18 01:32:37 PM PDT 24
Finished	Apr 18 01:45:50 PM PDT 24
Peak memory	212684 kb
Host	smart-4682c8fe-baa6-4f64-96ad-bd094df8daee
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3060826533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.3060826533
Directory	/workspace/25.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.clkmgr_trans.1124182670
Short name	T660
Test name
Test status
Simulation time	128809638 ps
CPU time	1.21 seconds
Started	Apr 18 01:32:33 PM PDT 24
Finished	Apr 18 01:32:35 PM PDT 24
Peak memory	200516 kb
Host	smart-a866d68d-c837-42b3-913e-564f54abb711
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124182670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.1124182670
Directory	/workspace/25.clkmgr_trans/latest

Test location	/workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.2614243282
Short name	T822
Test name
Test status
Simulation time	53274238 ps
CPU time	1.01 seconds
Started	Apr 18 01:32:33 PM PDT 24
Finished	Apr 18 01:32:35 PM PDT 24
Peak memory	200580 kb
Host	smart-d0bea66f-d01c-4311-9bf6-ec621a1cbba2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614243282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_handshake_intersig_mubi.2614243282
Directory	/workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_clk_status.1280504601
Short name	T417
Test name
Test status
Simulation time	17539074 ps
CPU time	0.7 seconds
Started	Apr 18 01:32:35 PM PDT 24
Finished	Apr 18 01:32:37 PM PDT 24
Peak memory	199424 kb
Host	smart-b8e441b2-46cf-463d-8631-0a377c0b859a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280504601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.1280504601
Directory	/workspace/26.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/26.clkmgr_div_intersig_mubi.3438207169
Short name	T174
Test name
Test status
Simulation time	26182991 ps
CPU time	0.85 seconds
Started	Apr 18 01:32:40 PM PDT 24
Finished	Apr 18 01:32:44 PM PDT 24
Peak memory	200508 kb
Host	smart-836e33ed-e90a-4413-805f-095abdbec113
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438207169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_div_intersig_mubi.3438207169
Directory	/workspace/26.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_extclk.1878522349
Short name	T201
Test name
Test status
Simulation time	19694397 ps
CPU time	0.76 seconds
Started	Apr 18 01:32:35 PM PDT 24
Finished	Apr 18 01:32:37 PM PDT 24
Peak memory	200492 kb
Host	smart-83d2f36b-7f43-41f9-9fca-aa56fc3ec1b4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878522349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.1878522349
Directory	/workspace/26.clkmgr_extclk/latest

Test location	/workspace/coverage/default/26.clkmgr_frequency.2904668321
Short name	T501
Test name
Test status
Simulation time	855055404 ps
CPU time	4.05 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:49 PM PDT 24
Peak memory	200520 kb
Host	smart-2e242b0c-5df3-4881-8464-d17008eb9a9c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904668321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.2904668321
Directory	/workspace/26.clkmgr_frequency/latest

Test location	/workspace/coverage/default/26.clkmgr_frequency_timeout.807996590
Short name	T798
Test name
Test status
Simulation time	1939287132 ps
CPU time	13.35 seconds
Started	Apr 18 01:32:32 PM PDT 24
Finished	Apr 18 01:32:45 PM PDT 24
Peak memory	200640 kb
Host	smart-8ca1d975-5aee-455c-be8e-0dacec6b537a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807996590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_ti meout.807996590
Directory	/workspace/26.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/26.clkmgr_idle_intersig_mubi.1493405783
Short name	T258
Test name
Test status
Simulation time	67889285 ps
CPU time	0.92 seconds
Started	Apr 18 01:32:37 PM PDT 24
Finished	Apr 18 01:32:39 PM PDT 24
Peak memory	200444 kb
Host	smart-640adef3-00df-48ae-a55e-b9c6e093faae
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493405783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_idle_intersig_mubi.1493405783
Directory	/workspace/26.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.1124860998
Short name	T653
Test name
Test status
Simulation time	77365578 ps
CPU time	0.96 seconds
Started	Apr 18 01:32:34 PM PDT 24
Finished	Apr 18 01:32:36 PM PDT 24
Peak memory	200500 kb
Host	smart-67fce407-f4cc-485a-b803-e396735c55eb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124860998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 26.clkmgr_lc_clk_byp_req_intersig_mubi.1124860998
Directory	/workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.88199070
Short name	T250
Test name
Test status
Simulation time	35035120 ps
CPU time	0.94 seconds
Started	Apr 18 01:32:29 PM PDT 24
Finished	Apr 18 01:32:30 PM PDT 24
Peak memory	200568 kb
Host	smart-9cc9d532-e04d-4836-a55b-dc55bed5c6b8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88199070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_lc_ctrl_intersig_mubi.88199070
Directory	/workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_peri.454697748
Short name	T759
Test name
Test status
Simulation time	16690377 ps
CPU time	0.78 seconds
Started	Apr 18 01:32:37 PM PDT 24
Finished	Apr 18 01:32:39 PM PDT 24
Peak memory	200316 kb
Host	smart-124378e2-abb8-4655-a2be-a64bb6a71b07
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454697748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.454697748
Directory	/workspace/26.clkmgr_peri/latest

Test location	/workspace/coverage/default/26.clkmgr_regwen.2239813731
Short name	T713
Test name
Test status
Simulation time	947033409 ps
CPU time	3.99 seconds
Started	Apr 18 01:32:35 PM PDT 24
Finished	Apr 18 01:32:40 PM PDT 24
Peak memory	200732 kb
Host	smart-e463e634-5603-4914-8281-d000fc43c907
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239813731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.2239813731
Directory	/workspace/26.clkmgr_regwen/latest

Test location	/workspace/coverage/default/26.clkmgr_smoke.3850275606
Short name	T283
Test name
Test status
Simulation time	30219999 ps
CPU time	0.81 seconds
Started	Apr 18 01:32:37 PM PDT 24
Finished	Apr 18 01:32:40 PM PDT 24
Peak memory	200560 kb
Host	smart-13847798-5d2f-464e-8d74-a39fd6ad2d9f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850275606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.3850275606
Directory	/workspace/26.clkmgr_smoke/latest

Test location	/workspace/coverage/default/26.clkmgr_stress_all.1387427133
Short name	T800
Test name
Test status
Simulation time	8405900133 ps
CPU time	32.49 seconds
Started	Apr 18 01:32:38 PM PDT 24
Finished	Apr 18 01:33:12 PM PDT 24
Peak memory	200908 kb
Host	smart-47c6b169-17c6-4b5a-a6c2-5fe45085ddb8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387427133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all.1387427133
Directory	/workspace/26.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/26.clkmgr_trans.566087059
Short name	T550
Test name
Test status
Simulation time	115311599 ps
CPU time	1 seconds
Started	Apr 18 01:32:37 PM PDT 24
Finished	Apr 18 01:32:39 PM PDT 24
Peak memory	200560 kb
Host	smart-74da1fb3-6a9d-4a31-b8dd-1494dd855018
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566087059 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.566087059
Directory	/workspace/26.clkmgr_trans/latest

Test location	/workspace/coverage/default/27.clkmgr_alert_test.1096028835
Short name	T514
Test name
Test status
Simulation time	28297681 ps
CPU time	0.76 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:46 PM PDT 24
Peak memory	200608 kb
Host	smart-c8b424e5-45c7-4d0e-940a-f599a25334b4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096028835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk mgr_alert_test.1096028835
Directory	/workspace/27.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.1304584285
Short name	T705
Test name
Test status
Simulation time	51728673 ps
CPU time	0.86 seconds
Started	Apr 18 01:32:38 PM PDT 24
Finished	Apr 18 01:32:41 PM PDT 24
Peak memory	200588 kb
Host	smart-a77770fb-4c7e-48bb-9109-c97a08400503
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304584285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_handshake_intersig_mubi.1304584285
Directory	/workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_clk_status.3551598903
Short name	T14
Test name
Test status
Simulation time	18251766 ps
CPU time	0.7 seconds
Started	Apr 18 01:32:34 PM PDT 24
Finished	Apr 18 01:32:36 PM PDT 24
Peak memory	199488 kb
Host	smart-077b5655-2975-413b-a14e-f9ef92f003e4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551598903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.3551598903
Directory	/workspace/27.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/27.clkmgr_div_intersig_mubi.846525838
Short name	T220
Test name
Test status
Simulation time	27879714 ps
CPU time	0.79 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:47 PM PDT 24
Peak memory	200536 kb
Host	smart-3a16bf88-66b2-4697-af5b-4fcddd203bcf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846525838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.clkmgr_div_intersig_mubi.846525838
Directory	/workspace/27.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_extclk.4066215158
Short name	T576
Test name
Test status
Simulation time	42010716 ps
CPU time	0.87 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	200572 kb
Host	smart-4e3c88e3-6e4d-4985-a914-a73a481e7110
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066215158 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.4066215158
Directory	/workspace/27.clkmgr_extclk/latest

Test location	/workspace/coverage/default/27.clkmgr_frequency.2589693066
Short name	T495
Test name
Test status
Simulation time	795179736 ps
CPU time	6.37 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:53 PM PDT 24
Peak memory	200584 kb
Host	smart-a8126973-e3c3-4efb-bc88-13d804fda145
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589693066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.2589693066
Directory	/workspace/27.clkmgr_frequency/latest

Test location	/workspace/coverage/default/27.clkmgr_frequency_timeout.1654395113
Short name	T378
Test name
Test status
Simulation time	985642450 ps
CPU time	5.42 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:32:46 PM PDT 24
Peak memory	200660 kb
Host	smart-b94a8751-92ec-4b59-aecc-e0057fd3ab73
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654395113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t imeout.1654395113
Directory	/workspace/27.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/27.clkmgr_idle_intersig_mubi.4122776113
Short name	T563
Test name
Test status
Simulation time	25675630 ps
CPU time	0.76 seconds
Started	Apr 18 01:32:33 PM PDT 24
Finished	Apr 18 01:32:35 PM PDT 24
Peak memory	200572 kb
Host	smart-49b9817c-7a38-4610-bbd1-68541193fe70
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122776113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_idle_intersig_mubi.4122776113
Directory	/workspace/27.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.1679652792
Short name	T739
Test name
Test status
Simulation time	15738927 ps
CPU time	0.74 seconds
Started	Apr 18 01:32:29 PM PDT 24
Finished	Apr 18 01:32:30 PM PDT 24
Peak memory	200468 kb
Host	smart-48a36023-709b-4ba4-a1b8-62a9e8b85e04
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679652792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 27.clkmgr_lc_clk_byp_req_intersig_mubi.1679652792
Directory	/workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.3576916388
Short name	T698
Test name
Test status
Simulation time	16788700 ps
CPU time	0.75 seconds
Started	Apr 18 01:32:37 PM PDT 24
Finished	Apr 18 01:32:39 PM PDT 24
Peak memory	200564 kb
Host	smart-d2b93970-b3fb-4206-831f-71f5ed54ac48
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576916388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 27.clkmgr_lc_ctrl_intersig_mubi.3576916388
Directory	/workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_peri.272162025
Short name	T376
Test name
Test status
Simulation time	122613856 ps
CPU time	1 seconds
Started	Apr 18 01:32:33 PM PDT 24
Finished	Apr 18 01:32:35 PM PDT 24
Peak memory	200268 kb
Host	smart-e18f363a-913c-4e92-8851-60e6fe9dfd24
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272162025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.272162025
Directory	/workspace/27.clkmgr_peri/latest

Test location	/workspace/coverage/default/27.clkmgr_regwen.4042567513
Short name	T765
Test name
Test status
Simulation time	976759514 ps
CPU time	3.56 seconds
Started	Apr 18 01:32:32 PM PDT 24
Finished	Apr 18 01:32:36 PM PDT 24
Peak memory	200620 kb
Host	smart-542dd6d8-4df0-48da-ab84-957dcdd6a624
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042567513 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.4042567513
Directory	/workspace/27.clkmgr_regwen/latest

Test location	/workspace/coverage/default/27.clkmgr_smoke.2580873045
Short name	T186
Test name
Test status
Simulation time	37199357 ps
CPU time	0.93 seconds
Started	Apr 18 01:32:38 PM PDT 24
Finished	Apr 18 01:32:40 PM PDT 24
Peak memory	200524 kb
Host	smart-9d094535-2394-4d7d-9c20-923117854537
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580873045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.2580873045
Directory	/workspace/27.clkmgr_smoke/latest

Test location	/workspace/coverage/default/27.clkmgr_stress_all.2239917698
Short name	T199
Test name
Test status
Simulation time	8528236397 ps
CPU time	30.7 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:33:18 PM PDT 24
Peak memory	201000 kb
Host	smart-f13e0de9-94f3-401c-96ba-ea9a66f0c395
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239917698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all.2239917698
Directory	/workspace/27.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.2255684447
Short name	T379
Test name
Test status
Simulation time	33287181378 ps
CPU time	600.99 seconds
Started	Apr 18 01:32:32 PM PDT 24
Finished	Apr 18 01:42:34 PM PDT 24
Peak memory	217392 kb
Host	smart-e9055f8b-17f3-429e-9bce-d847f72d18d6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2255684447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.2255684447
Directory	/workspace/27.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.clkmgr_trans.2758853243
Short name	T572
Test name
Test status
Simulation time	60102602 ps
CPU time	0.94 seconds
Started	Apr 18 01:32:33 PM PDT 24
Finished	Apr 18 01:32:35 PM PDT 24
Peak memory	200508 kb
Host	smart-2319201c-7afd-4ede-b626-75326c3e1178
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758853243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.2758853243
Directory	/workspace/27.clkmgr_trans/latest

Test location	/workspace/coverage/default/28.clkmgr_alert_test.917088749
Short name	T238
Test name
Test status
Simulation time	15670382 ps
CPU time	0.77 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:45 PM PDT 24
Peak memory	200640 kb
Host	smart-e3c2e128-ef86-4664-a4f1-20e83debbd54
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917088749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkm gr_alert_test.917088749
Directory	/workspace/28.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.1349571579
Short name	T771
Test name
Test status
Simulation time	28494508 ps
CPU time	0.93 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:45 PM PDT 24
Peak memory	200604 kb
Host	smart-5b87bccc-edf8-4453-85da-46d051ffdb26
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349571579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_handshake_intersig_mubi.1349571579
Directory	/workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_clk_status.3169487728
Short name	T345
Test name
Test status
Simulation time	14992732 ps
CPU time	0.79 seconds
Started	Apr 18 01:32:36 PM PDT 24
Finished	Apr 18 01:32:38 PM PDT 24
Peak memory	200256 kb
Host	smart-ad054b25-b787-429b-bce1-48fa2320f7e5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169487728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.3169487728
Directory	/workspace/28.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/28.clkmgr_div_intersig_mubi.2837723098
Short name	T556
Test name
Test status
Simulation time	107315101 ps
CPU time	1.07 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	200580 kb
Host	smart-18b5f17b-1947-4aac-815c-bcd363df56cd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837723098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_div_intersig_mubi.2837723098
Directory	/workspace/28.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_extclk.2096869460
Short name	T163
Test name
Test status
Simulation time	77649195 ps
CPU time	1 seconds
Started	Apr 18 01:32:36 PM PDT 24
Finished	Apr 18 01:32:38 PM PDT 24
Peak memory	200224 kb
Host	smart-5da70705-eb37-4033-95a9-ab2113e466e7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096869460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.2096869460
Directory	/workspace/28.clkmgr_extclk/latest

Test location	/workspace/coverage/default/28.clkmgr_frequency.4025569497
Short name	T656
Test name
Test status
Simulation time	2354681069 ps
CPU time	16.57 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:33:02 PM PDT 24
Peak memory	200480 kb
Host	smart-b11584cd-cfc6-4c69-82ee-d90301adf476
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025569497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.4025569497
Directory	/workspace/28.clkmgr_frequency/latest

Test location	/workspace/coverage/default/28.clkmgr_frequency_timeout.496779638
Short name	T508
Test name
Test status
Simulation time	2055108524 ps
CPU time	14.34 seconds
Started	Apr 18 01:32:34 PM PDT 24
Finished	Apr 18 01:32:50 PM PDT 24
Peak memory	200812 kb
Host	smart-320dcb45-d829-427b-a72f-addbcbe62300
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496779638 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_ti meout.496779638
Directory	/workspace/28.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/28.clkmgr_idle_intersig_mubi.99559964
Short name	T662
Test name
Test status
Simulation time	76105883 ps
CPU time	1.04 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:32:42 PM PDT 24
Peak memory	200756 kb
Host	smart-5d4397e6-880c-4a29-982e-29f4e8f10683
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99559964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28 .clkmgr_idle_intersig_mubi.99559964
Directory	/workspace/28.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.403534090
Short name	T767
Test name
Test status
Simulation time	20177804 ps
CPU time	0.84 seconds
Started	Apr 18 01:32:34 PM PDT 24
Finished	Apr 18 01:32:35 PM PDT 24
Peak memory	200580 kb
Host	smart-dcbd912a-3725-460b-b536-12d16cf85356
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403534090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.clkmgr_lc_clk_byp_req_intersig_mubi.403534090
Directory	/workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.1248890433
Short name	T273
Test name
Test status
Simulation time	19188258 ps
CPU time	0.79 seconds
Started	Apr 18 01:32:38 PM PDT 24
Finished	Apr 18 01:32:40 PM PDT 24
Peak memory	200548 kb
Host	smart-6ff8e73a-0c7f-4a38-909d-d196f9aa7d3a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248890433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 28.clkmgr_lc_ctrl_intersig_mubi.1248890433
Directory	/workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_peri.1837972753
Short name	T715
Test name
Test status
Simulation time	15894438 ps
CPU time	0.75 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:46 PM PDT 24
Peak memory	200228 kb
Host	smart-949935d8-19f5-447c-8ba7-c1d4dcb45abb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837972753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.1837972753
Directory	/workspace/28.clkmgr_peri/latest

Test location	/workspace/coverage/default/28.clkmgr_regwen.2108597029
Short name	T745
Test name
Test status
Simulation time	2046580731 ps
CPU time	5.93 seconds
Started	Apr 18 01:32:37 PM PDT 24
Finished	Apr 18 01:32:45 PM PDT 24
Peak memory	200716 kb
Host	smart-406d9299-04d8-4e8f-8807-7f3a57792b07
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108597029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.2108597029
Directory	/workspace/28.clkmgr_regwen/latest

Test location	/workspace/coverage/default/28.clkmgr_smoke.3052895841
Short name	T135
Test name
Test status
Simulation time	206461255 ps
CPU time	1.3 seconds
Started	Apr 18 01:32:35 PM PDT 24
Finished	Apr 18 01:32:37 PM PDT 24
Peak memory	200612 kb
Host	smart-e7682007-d9ab-4a81-8cf2-406b5438f4f8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052895841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.3052895841
Directory	/workspace/28.clkmgr_smoke/latest

Test location	/workspace/coverage/default/28.clkmgr_stress_all.2821109010
Short name	T746
Test name
Test status
Simulation time	5363677748 ps
CPU time	39.15 seconds
Started	Apr 18 01:32:34 PM PDT 24
Finished	Apr 18 01:33:14 PM PDT 24
Peak memory	200984 kb
Host	smart-e9601050-f915-43bf-8f0d-233ab61f09ed
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821109010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all.2821109010
Directory	/workspace/28.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/28.clkmgr_stress_all_with_rand_reset.3724038743
Short name	T310
Test name
Test status
Simulation time	17465650338 ps
CPU time	324.41 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:38:06 PM PDT 24
Peak memory	209216 kb
Host	smart-23a60fb1-8d42-474c-8931-cda652649c31
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3724038743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.3724038743
Directory	/workspace/28.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.clkmgr_trans.19316166
Short name	T802
Test name
Test status
Simulation time	54694782 ps
CPU time	1.02 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:32:42 PM PDT 24
Peak memory	200496 kb
Host	smart-b870b871-488e-4c1b-89a5-1278bdaf4ef8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19316166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.19316166
Directory	/workspace/28.clkmgr_trans/latest

Test location	/workspace/coverage/default/29.clkmgr_alert_test.1531454094
Short name	T212
Test name
Test status
Simulation time	20701127 ps
CPU time	0.72 seconds
Started	Apr 18 01:32:37 PM PDT 24
Finished	Apr 18 01:32:39 PM PDT 24
Peak memory	200432 kb
Host	smart-f24768f4-4578-42f0-a8a5-d8abe12ad818
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531454094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clk mgr_alert_test.1531454094
Directory	/workspace/29.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.2511515589
Short name	T85
Test name
Test status
Simulation time	47314037 ps
CPU time	0.96 seconds
Started	Apr 18 01:32:40 PM PDT 24
Finished	Apr 18 01:32:44 PM PDT 24
Peak memory	200584 kb
Host	smart-faa6dec7-fd9c-4e31-80b8-104b554b2314
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511515589 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_handshake_intersig_mubi.2511515589
Directory	/workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_clk_status.473373415
Short name	T491
Test name
Test status
Simulation time	55620966 ps
CPU time	0.77 seconds
Started	Apr 18 01:32:37 PM PDT 24
Finished	Apr 18 01:32:38 PM PDT 24
Peak memory	200252 kb
Host	smart-231c0b1f-6d08-4ba1-a905-8559a2bc3530
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473373415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.473373415
Directory	/workspace/29.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/29.clkmgr_div_intersig_mubi.2956476358
Short name	T654
Test name
Test status
Simulation time	25093909 ps
CPU time	0.85 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	200568 kb
Host	smart-fbf06983-350b-4a23-b426-c3f914eacd79
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956476358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_div_intersig_mubi.2956476358
Directory	/workspace/29.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_extclk.711039138
Short name	T509
Test name
Test status
Simulation time	183885147 ps
CPU time	1.24 seconds
Started	Apr 18 01:32:30 PM PDT 24
Finished	Apr 18 01:32:32 PM PDT 24
Peak memory	200552 kb
Host	smart-e09b452e-ef62-4236-b352-8e616db079aa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711039138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.711039138
Directory	/workspace/29.clkmgr_extclk/latest

Test location	/workspace/coverage/default/29.clkmgr_frequency.647022289
Short name	T774
Test name
Test status
Simulation time	932835128 ps
CPU time	4.18 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:52 PM PDT 24
Peak memory	200704 kb
Host	smart-073adf82-41c9-429b-a41e-5e9b408614c9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647022289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.647022289
Directory	/workspace/29.clkmgr_frequency/latest

Test location	/workspace/coverage/default/29.clkmgr_frequency_timeout.683685715
Short name	T804
Test name
Test status
Simulation time	513011169 ps
CPU time	2.41 seconds
Started	Apr 18 01:32:35 PM PDT 24
Finished	Apr 18 01:32:38 PM PDT 24
Peak memory	200652 kb
Host	smart-64e7e8d5-0c44-4e6f-9165-8e86936cc85e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683685715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_ti meout.683685715
Directory	/workspace/29.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/29.clkmgr_idle_intersig_mubi.3687621667
Short name	T338
Test name
Test status
Simulation time	41196181 ps
CPU time	0.81 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:45 PM PDT 24
Peak memory	200584 kb
Host	smart-a9b7a564-d5cd-44e7-97d6-c12c5164ef2d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687621667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_idle_intersig_mubi.3687621667
Directory	/workspace/29.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.2669201573
Short name	T221
Test name
Test status
Simulation time	46071676 ps
CPU time	0.83 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:32:49 PM PDT 24
Peak memory	200604 kb
Host	smart-1de27661-d480-4e36-95ee-922e258e8fdd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669201573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 29.clkmgr_lc_clk_byp_req_intersig_mubi.2669201573
Directory	/workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.3528099361
Short name	T828
Test name
Test status
Simulation time	157225959 ps
CPU time	1.21 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:49 PM PDT 24
Peak memory	200212 kb
Host	smart-184bfef7-dea9-4e69-bd90-0d0767a3bf5a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528099361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 29.clkmgr_lc_ctrl_intersig_mubi.3528099361
Directory	/workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_peri.1961909957
Short name	T437
Test name
Test status
Simulation time	16397876 ps
CPU time	0.74 seconds
Started	Apr 18 01:32:37 PM PDT 24
Finished	Apr 18 01:32:40 PM PDT 24
Peak memory	200332 kb
Host	smart-6fa7f371-85cd-4ffc-a4ef-8a968a7b94db
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961909957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.1961909957
Directory	/workspace/29.clkmgr_peri/latest

Test location	/workspace/coverage/default/29.clkmgr_regwen.2095496447
Short name	T791
Test name
Test status
Simulation time	496204621 ps
CPU time	3.46 seconds
Started	Apr 18 01:32:36 PM PDT 24
Finished	Apr 18 01:32:40 PM PDT 24
Peak memory	200688 kb
Host	smart-b1ed7acc-3077-496c-a626-afcb7718a6f8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095496447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.2095496447
Directory	/workspace/29.clkmgr_regwen/latest

Test location	/workspace/coverage/default/29.clkmgr_smoke.1892188866
Short name	T35
Test name
Test status
Simulation time	15954189 ps
CPU time	0.82 seconds
Started	Apr 18 01:32:33 PM PDT 24
Finished	Apr 18 01:32:35 PM PDT 24
Peak memory	200552 kb
Host	smart-fa6f69f7-e6c8-409d-ad3a-5548af97889a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892188866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.1892188866
Directory	/workspace/29.clkmgr_smoke/latest

Test location	/workspace/coverage/default/29.clkmgr_stress_all.850241323
Short name	T586
Test name
Test status
Simulation time	3989146548 ps
CPU time	19.8 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:33:04 PM PDT 24
Peak memory	201020 kb
Host	smart-d1d61519-79ff-49a0-8021-54c8c6ba8258
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850241323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all.850241323
Directory	/workspace/29.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.3301936016
Short name	T90
Test name
Test status
Simulation time	30830934411 ps
CPU time	537.52 seconds
Started	Apr 18 01:32:36 PM PDT 24
Finished	Apr 18 01:41:35 PM PDT 24
Peak memory	209272 kb
Host	smart-9f5bec04-bd65-4a21-b772-ac8d5cb72edb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3301936016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.3301936016
Directory	/workspace/29.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.clkmgr_trans.2189731778
Short name	T764
Test name
Test status
Simulation time	98787200 ps
CPU time	1.04 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:45 PM PDT 24
Peak memory	200460 kb
Host	smart-ced3127f-33e9-450c-9ed8-5ca3aade5bab
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189731778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.2189731778
Directory	/workspace/29.clkmgr_trans/latest

Test location	/workspace/coverage/default/3.clkmgr_alert_test.1760523181
Short name	T599
Test name
Test status
Simulation time	321365783 ps
CPU time	1.71 seconds
Started	Apr 18 01:31:42 PM PDT 24
Finished	Apr 18 01:31:46 PM PDT 24
Peak memory	200616 kb
Host	smart-b105bc62-1c58-4304-8c25-67255ca2b636
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760523181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm gr_alert_test.1760523181
Directory	/workspace/3.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.2323044523
Short name	T493
Test name
Test status
Simulation time	88668237 ps
CPU time	1.04 seconds
Started	Apr 18 01:31:46 PM PDT 24
Finished	Apr 18 01:31:50 PM PDT 24
Peak memory	200616 kb
Host	smart-4f531f2b-4d3a-46f9-ae1d-bf99b4cb4522
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323044523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_handshake_intersig_mubi.2323044523
Directory	/workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_clk_status.2435764853
Short name	T516
Test name
Test status
Simulation time	13574550 ps
CPU time	0.66 seconds
Started	Apr 18 01:31:37 PM PDT 24
Finished	Apr 18 01:31:38 PM PDT 24
Peak memory	199512 kb
Host	smart-abaa0b37-47dd-480d-bc5b-537024c6aa96
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435764853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.2435764853
Directory	/workspace/3.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/3.clkmgr_div_intersig_mubi.2205608444
Short name	T254
Test name
Test status
Simulation time	42318016 ps
CPU time	0.81 seconds
Started	Apr 18 01:31:50 PM PDT 24
Finished	Apr 18 01:31:55 PM PDT 24
Peak memory	200584 kb
Host	smart-d6a0e14a-63b8-41a1-aabd-505ab781831d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205608444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_div_intersig_mubi.2205608444
Directory	/workspace/3.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_extclk.3418592155
Short name	T215
Test name
Test status
Simulation time	21234009 ps
CPU time	0.85 seconds
Started	Apr 18 01:31:42 PM PDT 24
Finished	Apr 18 01:31:45 PM PDT 24
Peak memory	200540 kb
Host	smart-c45edad7-acba-4aab-b074-bf22e97a76d3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418592155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.3418592155
Directory	/workspace/3.clkmgr_extclk/latest

Test location	/workspace/coverage/default/3.clkmgr_frequency.1846180039
Short name	T453
Test name
Test status
Simulation time	2480520399 ps
CPU time	13.33 seconds
Started	Apr 18 01:31:43 PM PDT 24
Finished	Apr 18 01:31:59 PM PDT 24
Peak memory	200808 kb
Host	smart-924444ac-12f4-4530-8296-643e28a4b18f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846180039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.1846180039
Directory	/workspace/3.clkmgr_frequency/latest

Test location	/workspace/coverage/default/3.clkmgr_frequency_timeout.1544448238
Short name	T449
Test name
Test status
Simulation time	982552174 ps
CPU time	5.24 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:56 PM PDT 24
Peak memory	200700 kb
Host	smart-1c647ee4-5144-4ea6-826f-f9bc0ee037a9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544448238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_ti meout.1544448238
Directory	/workspace/3.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/3.clkmgr_idle_intersig_mubi.235580899
Short name	T737
Test name
Test status
Simulation time	23739468 ps
CPU time	0.77 seconds
Started	Apr 18 01:31:42 PM PDT 24
Finished	Apr 18 01:31:44 PM PDT 24
Peak memory	200536 kb
Host	smart-bff894ac-343f-435f-91c1-7c59c2cd33bc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235580899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .clkmgr_idle_intersig_mubi.235580899
Directory	/workspace/3.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.527198732
Short name	T448
Test name
Test status
Simulation time	52505751 ps
CPU time	0.83 seconds
Started	Apr 18 01:31:43 PM PDT 24
Finished	Apr 18 01:31:46 PM PDT 24
Peak memory	200572 kb
Host	smart-23283061-5910-40c0-9463-e4027c18c82a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527198732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.clkmgr_lc_clk_byp_req_intersig_mubi.527198732
Directory	/workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.84911956
Short name	T217
Test name
Test status
Simulation time	18583488 ps
CPU time	0.83 seconds
Started	Apr 18 01:31:44 PM PDT 24
Finished	Apr 18 01:31:48 PM PDT 24
Peak memory	200584 kb
Host	smart-b349f718-9524-437a-bfb3-e39d88865837
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84911956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_lc_ctrl_intersig_mubi.84911956
Directory	/workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_peri.87514316
Short name	T333
Test name
Test status
Simulation time	25544519 ps
CPU time	0.7 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200432 kb
Host	smart-04cc9c0f-fb5b-4228-974c-b39a40255800
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87514316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.87514316
Directory	/workspace/3.clkmgr_peri/latest

Test location	/workspace/coverage/default/3.clkmgr_regwen.2789599103
Short name	T644
Test name
Test status
Simulation time	660024554 ps
CPU time	2.84 seconds
Started	Apr 18 01:31:40 PM PDT 24
Finished	Apr 18 01:31:44 PM PDT 24
Peak memory	200616 kb
Host	smart-c945ddaa-773e-4fe3-91f0-8958f720362e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789599103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.2789599103
Directory	/workspace/3.clkmgr_regwen/latest

Test location	/workspace/coverage/default/3.clkmgr_sec_cm.1221998371
Short name	T47
Test name
Test status
Simulation time	418777111 ps
CPU time	2.49 seconds
Started	Apr 18 01:31:42 PM PDT 24
Finished	Apr 18 01:31:47 PM PDT 24
Peak memory	219884 kb
Host	smart-5cde5104-8db8-49f3-9f7d-288bff921a95
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221998371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg r_sec_cm.1221998371
Directory	/workspace/3.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/3.clkmgr_smoke.2230459849
Short name	T831
Test name
Test status
Simulation time	22063890 ps
CPU time	0.84 seconds
Started	Apr 18 01:31:51 PM PDT 24
Finished	Apr 18 01:31:55 PM PDT 24
Peak memory	200560 kb
Host	smart-6f97a2de-bf5a-4abf-be56-6c367d2dc849
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230459849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.2230459849
Directory	/workspace/3.clkmgr_smoke/latest

Test location	/workspace/coverage/default/3.clkmgr_stress_all.1330122982
Short name	T480
Test name
Test status
Simulation time	2211341374 ps
CPU time	9.51 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:32:01 PM PDT 24
Peak memory	200920 kb
Host	smart-a3247f34-d29c-4d98-a06a-3f7cd95a0652
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330122982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all.1330122982
Directory	/workspace/3.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/3.clkmgr_stress_all_with_rand_reset.3039745419
Short name	T58
Test name
Test status
Simulation time	64802230977 ps
CPU time	578.68 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:41:39 PM PDT 24
Peak memory	209232 kb
Host	smart-7f8b1583-2571-482f-b7a2-fa706a015b42
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3039745419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.3039745419
Directory	/workspace/3.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.clkmgr_trans.1659103944
Short name	T497
Test name
Test status
Simulation time	29119337 ps
CPU time	0.84 seconds
Started	Apr 18 01:31:39 PM PDT 24
Finished	Apr 18 01:31:41 PM PDT 24
Peak memory	200524 kb
Host	smart-b9fad3bb-d65e-485b-9fb3-770d275ecef3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659103944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.1659103944
Directory	/workspace/3.clkmgr_trans/latest

Test location	/workspace/coverage/default/30.clkmgr_alert_test.434810928
Short name	T166
Test name
Test status
Simulation time	51676202 ps
CPU time	0.86 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:47 PM PDT 24
Peak memory	200504 kb
Host	smart-ac5aaa41-76d5-43eb-b3d6-16c143fcb286
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434810928 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkm gr_alert_test.434810928
Directory	/workspace/30.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.2349561060
Short name	T87
Test name
Test status
Simulation time	120762299 ps
CPU time	1.18 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:32:42 PM PDT 24
Peak memory	200560 kb
Host	smart-8169f85f-4620-4a1a-92e2-29c04d16b023
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349561060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_handshake_intersig_mubi.2349561060
Directory	/workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_clk_status.1183596494
Short name	T670
Test name
Test status
Simulation time	15894042 ps
CPU time	0.68 seconds
Started	Apr 18 01:32:34 PM PDT 24
Finished	Apr 18 01:32:35 PM PDT 24
Peak memory	199460 kb
Host	smart-e73f09e9-2d2b-45e1-874e-922c46c1e367
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183596494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.1183596494
Directory	/workspace/30.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/30.clkmgr_div_intersig_mubi.3873287913
Short name	T197
Test name
Test status
Simulation time	155586044 ps
CPU time	1.1 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:49 PM PDT 24
Peak memory	200208 kb
Host	smart-a9a47f07-bfe4-4c90-91be-d8fc74982c1a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873287913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_div_intersig_mubi.3873287913
Directory	/workspace/30.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_extclk.2606613534
Short name	T169
Test name
Test status
Simulation time	44534455 ps
CPU time	0.89 seconds
Started	Apr 18 01:32:38 PM PDT 24
Finished	Apr 18 01:32:41 PM PDT 24
Peak memory	200532 kb
Host	smart-ceb53b89-7e25-434e-8b04-0fe70e572c6c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606613534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.2606613534
Directory	/workspace/30.clkmgr_extclk/latest

Test location	/workspace/coverage/default/30.clkmgr_frequency.3412117975
Short name	T606
Test name
Test status
Simulation time	916434396 ps
CPU time	7.36 seconds
Started	Apr 18 01:32:38 PM PDT 24
Finished	Apr 18 01:32:47 PM PDT 24
Peak memory	200536 kb
Host	smart-b3e3fe04-5c42-4b23-9b4c-96f58df4396e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412117975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.3412117975
Directory	/workspace/30.clkmgr_frequency/latest

Test location	/workspace/coverage/default/30.clkmgr_frequency_timeout.3148297842
Short name	T757
Test name
Test status
Simulation time	1221889371 ps
CPU time	9.06 seconds
Started	Apr 18 01:32:40 PM PDT 24
Finished	Apr 18 01:32:52 PM PDT 24
Peak memory	200688 kb
Host	smart-8cde473a-3d94-4ce1-b935-0691e69d9651
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148297842 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_t imeout.3148297842
Directory	/workspace/30.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/30.clkmgr_idle_intersig_mubi.2556923692
Short name	T223
Test name
Test status
Simulation time	68297185 ps
CPU time	0.92 seconds
Started	Apr 18 01:32:35 PM PDT 24
Finished	Apr 18 01:32:37 PM PDT 24
Peak memory	200568 kb
Host	smart-33166a2e-b1ce-42b0-b236-64b6eb9d7dd4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556923692 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_idle_intersig_mubi.2556923692
Directory	/workspace/30.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.3731369083
Short name	T637
Test name
Test status
Simulation time	75552836 ps
CPU time	0.93 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:32:42 PM PDT 24
Peak memory	200760 kb
Host	smart-c37340a6-48b3-414c-af1b-28fac51a8af7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731369083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 30.clkmgr_lc_clk_byp_req_intersig_mubi.3731369083
Directory	/workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.1231448345
Short name	T321
Test name
Test status
Simulation time	74861747 ps
CPU time	0.9 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:46 PM PDT 24
Peak memory	200516 kb
Host	smart-b1ffd08d-b384-4b8b-ad08-45b42ebdbb14
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231448345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 30.clkmgr_lc_ctrl_intersig_mubi.1231448345
Directory	/workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_peri.3050093155
Short name	T26
Test name
Test status
Simulation time	42970258 ps
CPU time	0.79 seconds
Started	Apr 18 01:32:38 PM PDT 24
Finished	Apr 18 01:32:40 PM PDT 24
Peak memory	200276 kb
Host	smart-b2131b48-6f2e-4883-b202-eb3f085377f7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050093155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.3050093155
Directory	/workspace/30.clkmgr_peri/latest

Test location	/workspace/coverage/default/30.clkmgr_regwen.3619888977
Short name	T316
Test name
Test status
Simulation time	1108098720 ps
CPU time	5.95 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:32:54 PM PDT 24
Peak memory	200712 kb
Host	smart-8cf7399d-d33b-4259-88b6-21920c291302
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619888977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.3619888977
Directory	/workspace/30.clkmgr_regwen/latest

Test location	/workspace/coverage/default/30.clkmgr_smoke.742745115
Short name	T324
Test name
Test status
Simulation time	23132197 ps
CPU time	0.79 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:32:43 PM PDT 24
Peak memory	200588 kb
Host	smart-58400a81-f827-4eef-8959-9f9fe68d5446
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742745115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.742745115
Directory	/workspace/30.clkmgr_smoke/latest

Test location	/workspace/coverage/default/30.clkmgr_stress_all.2404133620
Short name	T760
Test name
Test status
Simulation time	10628579017 ps
CPU time	76.74 seconds
Started	Apr 18 01:32:36 PM PDT 24
Finished	Apr 18 01:33:54 PM PDT 24
Peak memory	200972 kb
Host	smart-850aec54-93fa-4066-b1d6-ecac4dd05675
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404133620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all.2404133620
Directory	/workspace/30.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/30.clkmgr_stress_all_with_rand_reset.3738625732
Short name	T143
Test name
Test status
Simulation time	112756982196 ps
CPU time	671.55 seconds
Started	Apr 18 01:32:48 PM PDT 24
Finished	Apr 18 01:44:02 PM PDT 24
Peak memory	212216 kb
Host	smart-d9118fbe-0052-425f-afc6-b750d99cfc08
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3738625732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.3738625732
Directory	/workspace/30.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.clkmgr_trans.1779213920
Short name	T288
Test name
Test status
Simulation time	100655301 ps
CPU time	1.07 seconds
Started	Apr 18 01:32:45 PM PDT 24
Finished	Apr 18 01:32:50 PM PDT 24
Peak memory	200568 kb
Host	smart-4dc6bf69-f6f0-472c-ada7-852e83349122
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779213920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.1779213920
Directory	/workspace/30.clkmgr_trans/latest

Test location	/workspace/coverage/default/31.clkmgr_alert_test.774038025
Short name	T643
Test name
Test status
Simulation time	27375580 ps
CPU time	0.72 seconds
Started	Apr 18 01:32:34 PM PDT 24
Finished	Apr 18 01:32:36 PM PDT 24
Peak memory	200480 kb
Host	smart-b913ee29-72fd-45a6-92ff-e6b783042f22
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774038025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkm gr_alert_test.774038025
Directory	/workspace/31.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.3504846674
Short name	T549
Test name
Test status
Simulation time	69786053 ps
CPU time	0.86 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:52 PM PDT 24
Peak memory	200604 kb
Host	smart-cce5a409-2e78-4ebc-9f61-672228e6860f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504846674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_handshake_intersig_mubi.3504846674
Directory	/workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_clk_status.973898366
Short name	T578
Test name
Test status
Simulation time	45229534 ps
CPU time	0.76 seconds
Started	Apr 18 01:32:37 PM PDT 24
Finished	Apr 18 01:32:38 PM PDT 24
Peak memory	199456 kb
Host	smart-38c767fa-5467-4dad-9be2-9a59e1fcf568
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973898366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.973898366
Directory	/workspace/31.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/31.clkmgr_div_intersig_mubi.3793124872
Short name	T484
Test name
Test status
Simulation time	39523472 ps
CPU time	0.84 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:47 PM PDT 24
Peak memory	200604 kb
Host	smart-064abfb6-4b5b-4d3d-869f-9cf5d376708a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793124872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_div_intersig_mubi.3793124872
Directory	/workspace/31.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_extclk.2023657720
Short name	T325
Test name
Test status
Simulation time	73283162 ps
CPU time	0.97 seconds
Started	Apr 18 01:32:36 PM PDT 24
Finished	Apr 18 01:32:38 PM PDT 24
Peak memory	200572 kb
Host	smart-d7d8c323-c2a4-44a2-a954-7c4e04562de8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023657720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.2023657720
Directory	/workspace/31.clkmgr_extclk/latest

Test location	/workspace/coverage/default/31.clkmgr_frequency.857494237
Short name	T664
Test name
Test status
Simulation time	2253557648 ps
CPU time	11.67 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:57 PM PDT 24
Peak memory	200848 kb
Host	smart-fc28f77c-edc3-4e18-8b6e-647ae747f45a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857494237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.857494237
Directory	/workspace/31.clkmgr_frequency/latest

Test location	/workspace/coverage/default/31.clkmgr_frequency_timeout.159039374
Short name	T562
Test name
Test status
Simulation time	157711796 ps
CPU time	1.24 seconds
Started	Apr 18 01:32:37 PM PDT 24
Finished	Apr 18 01:32:39 PM PDT 24
Peak memory	200700 kb
Host	smart-58e53cf3-a392-4dcb-b52a-940b79b2d08b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159039374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_ti meout.159039374
Directory	/workspace/31.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/31.clkmgr_idle_intersig_mubi.1694630233
Short name	T505
Test name
Test status
Simulation time	25620949 ps
CPU time	0.79 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	200520 kb
Host	smart-5d0a7c3b-7999-4a51-9a15-10a1913994a0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694630233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_idle_intersig_mubi.1694630233
Directory	/workspace/31.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.269138649
Short name	T442
Test name
Test status
Simulation time	69773588 ps
CPU time	0.93 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:47 PM PDT 24
Peak memory	200620 kb
Host	smart-4661ba86-8492-422e-880e-0108750cc48e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269138649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 31.clkmgr_lc_clk_byp_req_intersig_mubi.269138649
Directory	/workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.3594664932
Short name	T397
Test name
Test status
Simulation time	13782827 ps
CPU time	0.69 seconds
Started	Apr 18 01:32:34 PM PDT 24
Finished	Apr 18 01:32:35 PM PDT 24
Peak memory	200564 kb
Host	smart-7fa3256c-8594-4c43-9ac0-61dbf98acb04
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594664932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 31.clkmgr_lc_ctrl_intersig_mubi.3594664932
Directory	/workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_peri.38732741
Short name	T362
Test name
Test status
Simulation time	38156890 ps
CPU time	0.76 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	200304 kb
Host	smart-f2835b77-b0e4-4792-88f7-6821aee40cc8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38732741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.38732741
Directory	/workspace/31.clkmgr_peri/latest

Test location	/workspace/coverage/default/31.clkmgr_regwen.3488179054
Short name	T348
Test name
Test status
Simulation time	866483438 ps
CPU time	4.96 seconds
Started	Apr 18 01:32:34 PM PDT 24
Finished	Apr 18 01:32:40 PM PDT 24
Peak memory	200720 kb
Host	smart-dab53a1e-ff3f-4811-9982-cb24f5802653
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488179054 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.3488179054
Directory	/workspace/31.clkmgr_regwen/latest

Test location	/workspace/coverage/default/31.clkmgr_smoke.2542551154
Short name	T327
Test name
Test status
Simulation time	14790429 ps
CPU time	0.81 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	200624 kb
Host	smart-0ff04936-d28a-4242-9224-245e78d93cc0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542551154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.2542551154
Directory	/workspace/31.clkmgr_smoke/latest

Test location	/workspace/coverage/default/31.clkmgr_stress_all.465041271
Short name	T824
Test name
Test status
Simulation time	1075150304 ps
CPU time	4.65 seconds
Started	Apr 18 01:32:38 PM PDT 24
Finished	Apr 18 01:32:44 PM PDT 24
Peak memory	200756 kb
Host	smart-9c0cac3b-201f-4766-9d52-27d9b58df8ca
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465041271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all.465041271
Directory	/workspace/31.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.3672502459
Short name	T609
Test name
Test status
Simulation time	69373607737 ps
CPU time	385.38 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:39:07 PM PDT 24
Peak memory	209252 kb
Host	smart-eccdb237-bfa1-4e23-9474-d9a1bb406129
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3672502459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.3672502459
Directory	/workspace/31.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.clkmgr_trans.185457681
Short name	T469
Test name
Test status
Simulation time	81300270 ps
CPU time	0.99 seconds
Started	Apr 18 01:32:37 PM PDT 24
Finished	Apr 18 01:32:39 PM PDT 24
Peak memory	200512 kb
Host	smart-809bff3e-f4da-4686-9e41-8aec8df04243
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185457681 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.185457681
Directory	/workspace/31.clkmgr_trans/latest

Test location	/workspace/coverage/default/32.clkmgr_alert_test.3850319895
Short name	T432
Test name
Test status
Simulation time	45496272 ps
CPU time	0.83 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:32:49 PM PDT 24
Peak memory	200584 kb
Host	smart-eecdbe3b-9ea4-4fb7-8a23-764d5d585988
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850319895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk mgr_alert_test.3850319895
Directory	/workspace/32.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.87799877
Short name	T359
Test name
Test status
Simulation time	18111109 ps
CPU time	0.75 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:46 PM PDT 24
Peak memory	200524 kb
Host	smart-cecd57cf-1817-4a4f-93b7-2b21dc3ef718
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87799877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.clkmgr_clk_handshake_intersig_mubi.87799877
Directory	/workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_clk_status.1803009091
Short name	T833
Test name
Test status
Simulation time	18733158 ps
CPU time	0.74 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:32:42 PM PDT 24
Peak memory	200224 kb
Host	smart-ea01f629-fa3a-494f-bcc5-3df2f2a7f4d8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803009091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.1803009091
Directory	/workspace/32.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/32.clkmgr_div_intersig_mubi.782076629
Short name	T717
Test name
Test status
Simulation time	138551042 ps
CPU time	1.03 seconds
Started	Apr 18 01:32:46 PM PDT 24
Finished	Apr 18 01:32:50 PM PDT 24
Peak memory	200576 kb
Host	smart-6556abe3-3329-4ee1-8b4d-65177cbb1a25
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782076629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.clkmgr_div_intersig_mubi.782076629
Directory	/workspace/32.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_extclk.2420631502
Short name	T597
Test name
Test status
Simulation time	26012031 ps
CPU time	0.88 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:49 PM PDT 24
Peak memory	200640 kb
Host	smart-a64f79fb-7482-4911-8bd1-5679cc2fe5ab
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420631502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.2420631502
Directory	/workspace/32.clkmgr_extclk/latest

Test location	/workspace/coverage/default/32.clkmgr_frequency.715871085
Short name	T657
Test name
Test status
Simulation time	417195961 ps
CPU time	1.86 seconds
Started	Apr 18 01:32:37 PM PDT 24
Finished	Apr 18 01:32:40 PM PDT 24
Peak memory	200576 kb
Host	smart-65f90562-7d5a-4031-8c03-95e66e0cb0ae
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715871085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.715871085
Directory	/workspace/32.clkmgr_frequency/latest

Test location	/workspace/coverage/default/32.clkmgr_frequency_timeout.3862686953
Short name	T604
Test name
Test status
Simulation time	500456514 ps
CPU time	4.02 seconds
Started	Apr 18 01:32:35 PM PDT 24
Finished	Apr 18 01:32:40 PM PDT 24
Peak memory	200692 kb
Host	smart-2612ad9d-4d09-4fc4-bb57-a320abd2635a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862686953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_t imeout.3862686953
Directory	/workspace/32.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/32.clkmgr_idle_intersig_mubi.768464764
Short name	T823
Test name
Test status
Simulation time	17235868 ps
CPU time	0.78 seconds
Started	Apr 18 01:32:40 PM PDT 24
Finished	Apr 18 01:32:44 PM PDT 24
Peak memory	200552 kb
Host	smart-55017d49-4cca-4259-9d10-bae6fe9171cf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768464764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.clkmgr_idle_intersig_mubi.768464764
Directory	/workspace/32.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.3193211883
Short name	T366
Test name
Test status
Simulation time	46401208 ps
CPU time	0.89 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:32:49 PM PDT 24
Peak memory	200476 kb
Host	smart-b5f203cb-6d03-4c15-bee8-9da290d5969d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193211883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 32.clkmgr_lc_clk_byp_req_intersig_mubi.3193211883
Directory	/workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.9302140
Short name	T279
Test name
Test status
Simulation time	18789820 ps
CPU time	0.84 seconds
Started	Apr 18 01:32:38 PM PDT 24
Finished	Apr 18 01:32:40 PM PDT 24
Peak memory	200508 kb
Host	smart-2de9b026-2775-4e8e-a3da-fdaea6299fc1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9302140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_lc_ctrl_intersig_mubi.9302140
Directory	/workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_peri.1711679865
Short name	T411
Test name
Test status
Simulation time	25051448 ps
CPU time	0.74 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:47 PM PDT 24
Peak memory	200272 kb
Host	smart-e8c33348-5002-4805-9988-b67a0403b6f5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711679865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.1711679865
Directory	/workspace/32.clkmgr_peri/latest

Test location	/workspace/coverage/default/32.clkmgr_regwen.1601634699
Short name	T738
Test name
Test status
Simulation time	155684119 ps
CPU time	1.17 seconds
Started	Apr 18 01:32:38 PM PDT 24
Finished	Apr 18 01:32:41 PM PDT 24
Peak memory	200480 kb
Host	smart-a91f886b-d787-4077-81e9-6a39f0d3acff
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601634699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.1601634699
Directory	/workspace/32.clkmgr_regwen/latest

Test location	/workspace/coverage/default/32.clkmgr_smoke.3940346791
Short name	T545
Test name
Test status
Simulation time	23782642 ps
CPU time	0.85 seconds
Started	Apr 18 01:32:34 PM PDT 24
Finished	Apr 18 01:32:36 PM PDT 24
Peak memory	200576 kb
Host	smart-30bc3450-724f-4458-a6a6-619a94fbe451
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940346791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.3940346791
Directory	/workspace/32.clkmgr_smoke/latest

Test location	/workspace/coverage/default/32.clkmgr_stress_all.1691557883
Short name	T307
Test name
Test status
Simulation time	6009097823 ps
CPU time	31.23 seconds
Started	Apr 18 01:32:46 PM PDT 24
Finished	Apr 18 01:33:21 PM PDT 24
Peak memory	200980 kb
Host	smart-1dfa205d-b59a-4721-b778-5af9ae844c34
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691557883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all.1691557883
Directory	/workspace/32.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/32.clkmgr_stress_all_with_rand_reset.2921946310
Short name	T60
Test name
Test status
Simulation time	26612724056 ps
CPU time	362.59 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:38:47 PM PDT 24
Peak memory	209308 kb
Host	smart-e6168cca-6504-4582-b8d6-32c5f1bb756b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2921946310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.2921946310
Directory	/workspace/32.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.clkmgr_trans.2172192689
Short name	T79
Test name
Test status
Simulation time	53521721 ps
CPU time	0.97 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	200536 kb
Host	smart-eeae1df1-9e20-4f0b-b62b-1a921840d71e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172192689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.2172192689
Directory	/workspace/32.clkmgr_trans/latest

Test location	/workspace/coverage/default/33.clkmgr_alert_test.2215146724
Short name	T262
Test name
Test status
Simulation time	20206367 ps
CPU time	0.73 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:47 PM PDT 24
Peak memory	200520 kb
Host	smart-6acec926-b8f4-4d58-8269-7e29b0ece17c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215146724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk mgr_alert_test.2215146724
Directory	/workspace/33.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.31369317
Short name	T675
Test name
Test status
Simulation time	36604386 ps
CPU time	0.87 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:32:42 PM PDT 24
Peak memory	200588 kb
Host	smart-2c4bbce9-7668-497d-a940-4d17fdfb37a7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31369317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.clkmgr_clk_handshake_intersig_mubi.31369317
Directory	/workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_clk_status.3613115751
Short name	T619
Test name
Test status
Simulation time	73277776 ps
CPU time	0.82 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	199552 kb
Host	smart-69e37719-7167-4e63-b39f-521324f0f01e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613115751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.3613115751
Directory	/workspace/33.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/33.clkmgr_div_intersig_mubi.66994149
Short name	T790
Test name
Test status
Simulation time	24428556 ps
CPU time	0.83 seconds
Started	Apr 18 01:32:45 PM PDT 24
Finished	Apr 18 01:32:50 PM PDT 24
Peak memory	200576 kb
Host	smart-030dd3ca-6089-4dfb-9d35-d630bfb537d0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66994149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33 .clkmgr_div_intersig_mubi.66994149
Directory	/workspace/33.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_extclk.3190837361
Short name	T404
Test name
Test status
Simulation time	44112472 ps
CPU time	0.87 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:32:42 PM PDT 24
Peak memory	200544 kb
Host	smart-baadfba4-7c0d-47f9-a3a8-95458d768fe4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190837361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.3190837361
Directory	/workspace/33.clkmgr_extclk/latest

Test location	/workspace/coverage/default/33.clkmgr_frequency.1324683118
Short name	T252
Test name
Test status
Simulation time	1462781264 ps
CPU time	6.27 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:53 PM PDT 24
Peak memory	200632 kb
Host	smart-4a31ba0a-b58e-4114-9dfb-695c96f1331d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324683118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.1324683118
Directory	/workspace/33.clkmgr_frequency/latest

Test location	/workspace/coverage/default/33.clkmgr_frequency_timeout.3952335625
Short name	T28
Test name
Test status
Simulation time	615343777 ps
CPU time	4.77 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:32:53 PM PDT 24
Peak memory	200648 kb
Host	smart-9276df71-bbe5-4fae-ae3a-f19c02ea3f40
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952335625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_t imeout.3952335625
Directory	/workspace/33.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/33.clkmgr_idle_intersig_mubi.3788422924
Short name	T763
Test name
Test status
Simulation time	20069839 ps
CPU time	0.72 seconds
Started	Apr 18 01:33:37 PM PDT 24
Finished	Apr 18 01:33:40 PM PDT 24
Peak memory	199116 kb
Host	smart-f91259ae-1c2b-4700-bcbc-2648835cf1eb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788422924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_idle_intersig_mubi.3788422924
Directory	/workspace/33.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.3172281538
Short name	T793
Test name
Test status
Simulation time	20340522 ps
CPU time	0.8 seconds
Started	Apr 18 01:32:40 PM PDT 24
Finished	Apr 18 01:32:43 PM PDT 24
Peak memory	200556 kb
Host	smart-e662a625-7dd1-4e90-8909-cf9d89984edd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172281538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 33.clkmgr_lc_clk_byp_req_intersig_mubi.3172281538
Directory	/workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.4024558229
Short name	T277
Test name
Test status
Simulation time	63788654 ps
CPU time	0.9 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:46 PM PDT 24
Peak memory	200520 kb
Host	smart-24871b89-4e3c-4e00-9aa6-08a78ea6235e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024558229 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 33.clkmgr_lc_ctrl_intersig_mubi.4024558229
Directory	/workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_peri.173154064
Short name	T181
Test name
Test status
Simulation time	17292375 ps
CPU time	0.7 seconds
Started	Apr 18 01:33:05 PM PDT 24
Finished	Apr 18 01:33:06 PM PDT 24
Peak memory	200316 kb
Host	smart-cd3c4209-a7db-44a3-8eb1-eac32dd23b16
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173154064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.173154064
Directory	/workspace/33.clkmgr_peri/latest

Test location	/workspace/coverage/default/33.clkmgr_regwen.2678567634
Short name	T343
Test name
Test status
Simulation time	734511748 ps
CPU time	2.63 seconds
Started	Apr 18 01:32:48 PM PDT 24
Finished	Apr 18 01:32:54 PM PDT 24
Peak memory	200548 kb
Host	smart-1afa2f15-f3d1-4412-bf06-ca2b6eb04845
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678567634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.2678567634
Directory	/workspace/33.clkmgr_regwen/latest

Test location	/workspace/coverage/default/33.clkmgr_smoke.89534481
Short name	T218
Test name
Test status
Simulation time	173645564 ps
CPU time	1.24 seconds
Started	Apr 18 01:32:38 PM PDT 24
Finished	Apr 18 01:32:41 PM PDT 24
Peak memory	200564 kb
Host	smart-8d7ac57b-8527-4862-9b4b-98248cac1852
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89534481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.89534481
Directory	/workspace/33.clkmgr_smoke/latest

Test location	/workspace/coverage/default/33.clkmgr_stress_all.4212560906
Short name	T821
Test name
Test status
Simulation time	2868263361 ps
CPU time	21.22 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:33:10 PM PDT 24
Peak memory	200976 kb
Host	smart-27c5ebe9-2cb8-4e76-b6c3-78e4cff13068
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212560906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all.4212560906
Directory	/workspace/33.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/33.clkmgr_stress_all_with_rand_reset.3388493647
Short name	T91
Test name
Test status
Simulation time	31560277244 ps
CPU time	457.61 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:40:22 PM PDT 24
Peak memory	209328 kb
Host	smart-a20b0710-447b-4ede-a3e6-eff3358f7871
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3388493647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.3388493647
Directory	/workspace/33.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.clkmgr_trans.2245730077
Short name	T743
Test name
Test status
Simulation time	16902505 ps
CPU time	0.78 seconds
Started	Apr 18 01:32:38 PM PDT 24
Finished	Apr 18 01:32:41 PM PDT 24
Peak memory	200340 kb
Host	smart-55bc3a1e-1a7c-4b15-abec-c82753446b07
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245730077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.2245730077
Directory	/workspace/33.clkmgr_trans/latest

Test location	/workspace/coverage/default/34.clkmgr_alert_test.2628793209
Short name	T401
Test name
Test status
Simulation time	34551467 ps
CPU time	0.83 seconds
Started	Apr 18 01:32:40 PM PDT 24
Finished	Apr 18 01:32:43 PM PDT 24
Peak memory	200488 kb
Host	smart-cb8ef0a1-d2b1-41e6-b8ea-b81d88507593
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628793209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk mgr_alert_test.2628793209
Directory	/workspace/34.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.3727249209
Short name	T89
Test name
Test status
Simulation time	28197572 ps
CPU time	0.88 seconds
Started	Apr 18 01:32:45 PM PDT 24
Finished	Apr 18 01:32:50 PM PDT 24
Peak memory	200576 kb
Host	smart-42df45a9-5a8e-4d3c-aa76-7159db588610
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727249209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_handshake_intersig_mubi.3727249209
Directory	/workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_clk_status.720240231
Short name	T633
Test name
Test status
Simulation time	60511476 ps
CPU time	0.83 seconds
Started	Apr 18 01:32:47 PM PDT 24
Finished	Apr 18 01:32:51 PM PDT 24
Peak memory	200192 kb
Host	smart-46cccf71-fb8a-423a-a105-c6577a275db9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720240231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.720240231
Directory	/workspace/34.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/34.clkmgr_div_intersig_mubi.1822364340
Short name	T634
Test name
Test status
Simulation time	46233362 ps
CPU time	0.91 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:49 PM PDT 24
Peak memory	200572 kb
Host	smart-4a83e1b7-2880-463b-a6f5-161971107045
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822364340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_div_intersig_mubi.1822364340
Directory	/workspace/34.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_extclk.209038571
Short name	T226
Test name
Test status
Simulation time	15272850 ps
CPU time	0.72 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:47 PM PDT 24
Peak memory	200556 kb
Host	smart-74dba5e8-9b73-4f14-b7aa-74a9c30e80c2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209038571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.209038571
Directory	/workspace/34.clkmgr_extclk/latest

Test location	/workspace/coverage/default/34.clkmgr_frequency.813828918
Short name	T640
Test name
Test status
Simulation time	1942083413 ps
CPU time	7.07 seconds
Started	Apr 18 01:32:45 PM PDT 24
Finished	Apr 18 01:32:56 PM PDT 24
Peak memory	200832 kb
Host	smart-dfc32298-31d1-4155-bee3-6929f65f51e9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813828918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.813828918
Directory	/workspace/34.clkmgr_frequency/latest

Test location	/workspace/coverage/default/34.clkmgr_frequency_timeout.3784251813
Short name	T29
Test name
Test status
Simulation time	2347560283 ps
CPU time	7.48 seconds
Started	Apr 18 01:32:45 PM PDT 24
Finished	Apr 18 01:32:57 PM PDT 24
Peak memory	200724 kb
Host	smart-6e989c21-3472-46b4-9aa4-b8b0449c8c54
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784251813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_t imeout.3784251813
Directory	/workspace/34.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/34.clkmgr_idle_intersig_mubi.1798072979
Short name	T564
Test name
Test status
Simulation time	91823852 ps
CPU time	1.09 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	200592 kb
Host	smart-8061698d-fd7d-4383-ae6b-08efd258360f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798072979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_idle_intersig_mubi.1798072979
Directory	/workspace/34.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.2948071503
Short name	T222
Test name
Test status
Simulation time	39014774 ps
CPU time	0.89 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:32:42 PM PDT 24
Peak memory	200548 kb
Host	smart-c5bdb30d-46b9-46c4-ab64-639bd5b56e28
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948071503 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 34.clkmgr_lc_clk_byp_req_intersig_mubi.2948071503
Directory	/workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.2291858655
Short name	T40
Test name
Test status
Simulation time	54842846 ps
CPU time	0.95 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:49 PM PDT 24
Peak memory	200556 kb
Host	smart-99eb5849-7804-4fd1-ab1b-a542ca360c76
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291858655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 34.clkmgr_lc_ctrl_intersig_mubi.2291858655
Directory	/workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_peri.2344926011
Short name	T456
Test name
Test status
Simulation time	11683728 ps
CPU time	0.72 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:45 PM PDT 24
Peak memory	200240 kb
Host	smart-ee09556c-f9f1-4197-a223-514cbd7baf96
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344926011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.2344926011
Directory	/workspace/34.clkmgr_peri/latest

Test location	/workspace/coverage/default/34.clkmgr_regwen.1428935698
Short name	T630
Test name
Test status
Simulation time	784968618 ps
CPU time	3.04 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:50 PM PDT 24
Peak memory	200668 kb
Host	smart-f4923bc8-a57e-46ac-a08c-05a9d802c110
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428935698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.1428935698
Directory	/workspace/34.clkmgr_regwen/latest

Test location	/workspace/coverage/default/34.clkmgr_smoke.1054230442
Short name	T684
Test name
Test status
Simulation time	37345412 ps
CPU time	0.89 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:32:49 PM PDT 24
Peak memory	200560 kb
Host	smart-107d9fb6-96b0-41ca-9f7d-594a7d00741d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054230442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.1054230442
Directory	/workspace/34.clkmgr_smoke/latest

Test location	/workspace/coverage/default/34.clkmgr_stress_all.15096790
Short name	T387
Test name
Test status
Simulation time	5121894593 ps
CPU time	38.15 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:33:29 PM PDT 24
Peak memory	200976 kb
Host	smart-92f33baf-646a-4483-be97-46b365e8a015
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15096790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_ TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.clkmgr_stress_all.15096790
Directory	/workspace/34.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.47193538
Short name	T293
Test name
Test status
Simulation time	25532617903 ps
CPU time	268.65 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:37:17 PM PDT 24
Peak memory	209204 kb
Host	smart-64698dfe-637e-4b83-ab98-ce349ed0f190
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=47193538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.47193538
Directory	/workspace/34.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.clkmgr_trans.475389037
Short name	T231
Test name
Test status
Simulation time	41754347 ps
CPU time	1 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:32:42 PM PDT 24
Peak memory	200548 kb
Host	smart-c2941372-635c-460f-8999-5f316e618c61
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475389037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.475389037
Directory	/workspace/34.clkmgr_trans/latest

Test location	/workspace/coverage/default/35.clkmgr_alert_test.3100149119
Short name	T748
Test name
Test status
Simulation time	36114461 ps
CPU time	0.79 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:46 PM PDT 24
Peak memory	200544 kb
Host	smart-0551a108-5a4d-412f-a60c-fc03bebebcf7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100149119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk mgr_alert_test.3100149119
Directory	/workspace/35.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.3061853753
Short name	T538
Test name
Test status
Simulation time	18028458 ps
CPU time	0.77 seconds
Started	Apr 18 01:32:40 PM PDT 24
Finished	Apr 18 01:32:44 PM PDT 24
Peak memory	200552 kb
Host	smart-2a9f5e70-c93f-4f6a-b074-8e643d54c5cd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061853753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_handshake_intersig_mubi.3061853753
Directory	/workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_clk_status.2253653482
Short name	T711
Test name
Test status
Simulation time	16886048 ps
CPU time	0.69 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:32:41 PM PDT 24
Peak memory	200240 kb
Host	smart-63b0b419-0ae8-4d9d-9bdf-60ab778b486a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253653482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.2253653482
Directory	/workspace/35.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/35.clkmgr_div_intersig_mubi.3961666658
Short name	T419
Test name
Test status
Simulation time	20312379 ps
CPU time	0.79 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:47 PM PDT 24
Peak memory	200556 kb
Host	smart-fb6417e0-3e5a-4c4b-bb36-abed451e104d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961666658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_div_intersig_mubi.3961666658
Directory	/workspace/35.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_extclk.1725669976
Short name	T323
Test name
Test status
Simulation time	37766529 ps
CPU time	0.87 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:32:42 PM PDT 24
Peak memory	200488 kb
Host	smart-4f53db24-8980-4e86-8b50-c965b836507b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725669976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.1725669976
Directory	/workspace/35.clkmgr_extclk/latest

Test location	/workspace/coverage/default/35.clkmgr_frequency.1451987565
Short name	T386
Test name
Test status
Simulation time	435944917 ps
CPU time	3.76 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:50 PM PDT 24
Peak memory	200592 kb
Host	smart-5726df67-a7b2-40a8-a527-5a51f3985f84
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451987565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.1451987565
Directory	/workspace/35.clkmgr_frequency/latest

Test location	/workspace/coverage/default/35.clkmgr_frequency_timeout.619883433
Short name	T543
Test name
Test status
Simulation time	626158420 ps
CPU time	3.39 seconds
Started	Apr 18 01:32:38 PM PDT 24
Finished	Apr 18 01:32:44 PM PDT 24
Peak memory	200696 kb
Host	smart-0e4f1cb2-b7bd-4c35-9a49-64c9b8a64e2c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619883433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_ti meout.619883433
Directory	/workspace/35.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/35.clkmgr_idle_intersig_mubi.344552488
Short name	T463
Test name
Test status
Simulation time	27855257 ps
CPU time	0.79 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:47 PM PDT 24
Peak memory	200464 kb
Host	smart-6f390cdd-042a-45ea-bf9a-f864888c699c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344552488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.clkmgr_idle_intersig_mubi.344552488
Directory	/workspace/35.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.727216310
Short name	T647
Test name
Test status
Simulation time	11380872 ps
CPU time	0.73 seconds
Started	Apr 18 01:32:40 PM PDT 24
Finished	Apr 18 01:32:43 PM PDT 24
Peak memory	200560 kb
Host	smart-033528a0-fa50-4100-8a13-daceaf9ea6f7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727216310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 35.clkmgr_lc_clk_byp_req_intersig_mubi.727216310
Directory	/workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.2176176720
Short name	T627
Test name
Test status
Simulation time	52569102 ps
CPU time	0.82 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:32:42 PM PDT 24
Peak memory	200528 kb
Host	smart-2c058fd4-3260-474d-9dc4-940e49376268
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176176720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 35.clkmgr_lc_ctrl_intersig_mubi.2176176720
Directory	/workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_peri.3673026166
Short name	T410
Test name
Test status
Simulation time	16390195 ps
CPU time	0.75 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:45 PM PDT 24
Peak memory	200292 kb
Host	smart-7ad46150-8bf1-4111-bd0a-78f420d13bb8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673026166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.3673026166
Directory	/workspace/35.clkmgr_peri/latest

Test location	/workspace/coverage/default/35.clkmgr_regwen.1540821274
Short name	T686
Test name
Test status
Simulation time	845428132 ps
CPU time	3.06 seconds
Started	Apr 18 01:32:38 PM PDT 24
Finished	Apr 18 01:32:43 PM PDT 24
Peak memory	200524 kb
Host	smart-fb6a3ad1-0ccb-4533-87e1-81111cc0bee4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540821274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.1540821274
Directory	/workspace/35.clkmgr_regwen/latest

Test location	/workspace/coverage/default/35.clkmgr_smoke.3279763721
Short name	T483
Test name
Test status
Simulation time	243210438 ps
CPU time	1.39 seconds
Started	Apr 18 01:32:38 PM PDT 24
Finished	Apr 18 01:32:41 PM PDT 24
Peak memory	200580 kb
Host	smart-b9ead8bf-2059-4ccc-ab2e-2b133f5b30db
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279763721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.3279763721
Directory	/workspace/35.clkmgr_smoke/latest

Test location	/workspace/coverage/default/35.clkmgr_stress_all.1995026200
Short name	T116
Test name
Test status
Simulation time	8185404479 ps
CPU time	31.59 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:33:20 PM PDT 24
Peak memory	200868 kb
Host	smart-243a9eeb-a645-4d66-b574-54b924c2a282
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995026200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all.1995026200
Directory	/workspace/35.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/35.clkmgr_stress_all_with_rand_reset.1628364867
Short name	T841
Test name
Test status
Simulation time	12606790690 ps
CPU time	187.28 seconds
Started	Apr 18 01:32:40 PM PDT 24
Finished	Apr 18 01:35:49 PM PDT 24
Peak memory	214496 kb
Host	smart-f2f8319f-c8ef-40d8-b411-f068fa61ea58
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1628364867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.1628364867
Directory	/workspace/35.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.clkmgr_trans.3727234556
Short name	T246
Test name
Test status
Simulation time	27404201 ps
CPU time	0.95 seconds
Started	Apr 18 01:32:40 PM PDT 24
Finished	Apr 18 01:32:43 PM PDT 24
Peak memory	200476 kb
Host	smart-c2a30b6b-2854-47f3-af46-291d78bf4027
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727234556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.3727234556
Directory	/workspace/35.clkmgr_trans/latest

Test location	/workspace/coverage/default/36.clkmgr_alert_test.1828382419
Short name	T652
Test name
Test status
Simulation time	55930142 ps
CPU time	0.83 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:47 PM PDT 24
Peak memory	200572 kb
Host	smart-49e1c454-f82a-47b7-b4aa-893d7e4505e7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828382419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk mgr_alert_test.1828382419
Directory	/workspace/36.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.2231434246
Short name	T659
Test name
Test status
Simulation time	40318845 ps
CPU time	0.89 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:32:49 PM PDT 24
Peak memory	200516 kb
Host	smart-e77edb50-105b-4c35-ba33-4bcca7cf7964
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231434246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_handshake_intersig_mubi.2231434246
Directory	/workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_clk_status.1638277118
Short name	T769
Test name
Test status
Simulation time	13152877 ps
CPU time	0.67 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:45 PM PDT 24
Peak memory	199464 kb
Host	smart-42527508-01f6-46fb-95b3-64a3ed8d3ae1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638277118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.1638277118
Directory	/workspace/36.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/36.clkmgr_div_intersig_mubi.4008926709
Short name	T210
Test name
Test status
Simulation time	30496326 ps
CPU time	0.96 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:52 PM PDT 24
Peak memory	200568 kb
Host	smart-22a93b5d-ff9a-4093-923b-8e6662c95521
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008926709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_div_intersig_mubi.4008926709
Directory	/workspace/36.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_extclk.1402383490
Short name	T775
Test name
Test status
Simulation time	54001239 ps
CPU time	0.94 seconds
Started	Apr 18 01:32:45 PM PDT 24
Finished	Apr 18 01:32:50 PM PDT 24
Peak memory	200484 kb
Host	smart-301ce417-32cf-4879-a993-67d8eac0395c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402383490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.1402383490
Directory	/workspace/36.clkmgr_extclk/latest

Test location	/workspace/coverage/default/36.clkmgr_frequency.1376582845
Short name	T69
Test name
Test status
Simulation time	449179889 ps
CPU time	2.41 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	200564 kb
Host	smart-899a449a-6b29-4a10-8aca-2f35a10579f1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376582845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.1376582845
Directory	/workspace/36.clkmgr_frequency/latest

Test location	/workspace/coverage/default/36.clkmgr_frequency_timeout.1860859190
Short name	T682
Test name
Test status
Simulation time	2300528178 ps
CPU time	16.56 seconds
Started	Apr 18 01:32:37 PM PDT 24
Finished	Apr 18 01:32:54 PM PDT 24
Peak memory	200900 kb
Host	smart-535b4c4c-a1ec-4033-bf2b-b48c52527eb5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860859190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t imeout.1860859190
Directory	/workspace/36.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/36.clkmgr_idle_intersig_mubi.3643919966
Short name	T725
Test name
Test status
Simulation time	19712002 ps
CPU time	0.8 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:32:49 PM PDT 24
Peak memory	200592 kb
Host	smart-050caad8-15be-4d92-bbe5-82481f751a0b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643919966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_idle_intersig_mubi.3643919966
Directory	/workspace/36.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.3855522372
Short name	T192
Test name
Test status
Simulation time	72161359 ps
CPU time	1.02 seconds
Started	Apr 18 01:32:45 PM PDT 24
Finished	Apr 18 01:32:50 PM PDT 24
Peak memory	200628 kb
Host	smart-7ab792de-5ccb-4412-a2e3-fbe4326d086e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855522372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 36.clkmgr_lc_clk_byp_req_intersig_mubi.3855522372
Directory	/workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.2124407363
Short name	T399
Test name
Test status
Simulation time	24966050 ps
CPU time	0.83 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:45 PM PDT 24
Peak memory	200572 kb
Host	smart-fc26a625-1e14-40d1-b514-ddb39a41e417
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124407363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 36.clkmgr_lc_ctrl_intersig_mubi.2124407363
Directory	/workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_peri.4135161327
Short name	T689
Test name
Test status
Simulation time	14551304 ps
CPU time	0.73 seconds
Started	Apr 18 01:32:40 PM PDT 24
Finished	Apr 18 01:32:44 PM PDT 24
Peak memory	200284 kb
Host	smart-d6865bee-2def-41e8-810a-6b23b3067afb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135161327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.4135161327
Directory	/workspace/36.clkmgr_peri/latest

Test location	/workspace/coverage/default/36.clkmgr_regwen.2139150565
Short name	T742
Test name
Test status
Simulation time	1242451569 ps
CPU time	4.66 seconds
Started	Apr 18 01:32:45 PM PDT 24
Finished	Apr 18 01:32:54 PM PDT 24
Peak memory	200716 kb
Host	smart-8bbdef0b-a63c-49e4-8505-542f55ce4463
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139150565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.2139150565
Directory	/workspace/36.clkmgr_regwen/latest

Test location	/workspace/coverage/default/36.clkmgr_smoke.3792617106
Short name	T608
Test name
Test status
Simulation time	51489439 ps
CPU time	0.95 seconds
Started	Apr 18 01:32:37 PM PDT 24
Finished	Apr 18 01:32:39 PM PDT 24
Peak memory	200532 kb
Host	smart-6b1a8eed-c9d9-4ce2-881f-66ae10f42e00
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792617106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.3792617106
Directory	/workspace/36.clkmgr_smoke/latest

Test location	/workspace/coverage/default/36.clkmgr_stress_all.1999433882
Short name	T598
Test name
Test status
Simulation time	13939162699 ps
CPU time	41.33 seconds
Started	Apr 18 01:32:45 PM PDT 24
Finished	Apr 18 01:33:31 PM PDT 24
Peak memory	200952 kb
Host	smart-91cbddab-e632-4932-9cb4-3c4a9ca62eeb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999433882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all.1999433882
Directory	/workspace/36.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.1387749337
Short name	T375
Test name
Test status
Simulation time	48459946882 ps
CPU time	530.1 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:41:35 PM PDT 24
Peak memory	209220 kb
Host	smart-7aa312ea-9d18-4268-963f-72b77159e81e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1387749337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.1387749337
Directory	/workspace/36.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.clkmgr_trans.3804163980
Short name	T766
Test name
Test status
Simulation time	85488131 ps
CPU time	1 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:47 PM PDT 24
Peak memory	200044 kb
Host	smart-cfdd28aa-e7bc-4eca-a123-4ae05d60cf13
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804163980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.3804163980
Directory	/workspace/36.clkmgr_trans/latest

Test location	/workspace/coverage/default/37.clkmgr_alert_test.3353673655
Short name	T573
Test name
Test status
Simulation time	38496463 ps
CPU time	0.76 seconds
Started	Apr 18 01:33:37 PM PDT 24
Finished	Apr 18 01:33:40 PM PDT 24
Peak memory	199212 kb
Host	smart-e27ca5da-0fa2-4e9e-8794-6c608967ba96
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353673655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk mgr_alert_test.3353673655
Directory	/workspace/37.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.2462044898
Short name	T93
Test name
Test status
Simulation time	79080027 ps
CPU time	1.12 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:49 PM PDT 24
Peak memory	200564 kb
Host	smart-051c3a87-a280-4e2c-a245-95079f271952
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462044898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_handshake_intersig_mubi.2462044898
Directory	/workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_clk_status.1802955922
Short name	T815
Test name
Test status
Simulation time	13165060 ps
CPU time	0.67 seconds
Started	Apr 18 01:32:40 PM PDT 24
Finished	Apr 18 01:32:43 PM PDT 24
Peak memory	199444 kb
Host	smart-633bec0d-6aa3-40cf-868b-a6e3c556ccc3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802955922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.1802955922
Directory	/workspace/37.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/37.clkmgr_div_intersig_mubi.1661257115
Short name	T245
Test name
Test status
Simulation time	25624182 ps
CPU time	0.85 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:45 PM PDT 24
Peak memory	200588 kb
Host	smart-7cd28197-8bdc-49e8-b826-a7d133565644
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661257115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_div_intersig_mubi.1661257115
Directory	/workspace/37.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_extclk.3675014414
Short name	T683
Test name
Test status
Simulation time	16687507 ps
CPU time	0.76 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	200476 kb
Host	smart-fdf66fc9-17db-4b74-af77-8333e8e99bbe
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675014414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.3675014414
Directory	/workspace/37.clkmgr_extclk/latest

Test location	/workspace/coverage/default/37.clkmgr_frequency.1435836354
Short name	T117
Test name
Test status
Simulation time	2617366169 ps
CPU time	11.17 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:33:01 PM PDT 24
Peak memory	200904 kb
Host	smart-13fec880-8673-434f-8a21-d1893b1873fc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435836354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.1435836354
Directory	/workspace/37.clkmgr_frequency/latest

Test location	/workspace/coverage/default/37.clkmgr_frequency_timeout.3666873073
Short name	T189
Test name
Test status
Simulation time	2298494824 ps
CPU time	16.35 seconds
Started	Apr 18 01:32:38 PM PDT 24
Finished	Apr 18 01:32:56 PM PDT 24
Peak memory	200876 kb
Host	smart-46882f49-6b34-4300-bd6e-9e5e87a3ba4d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666873073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t imeout.3666873073
Directory	/workspace/37.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/37.clkmgr_idle_intersig_mubi.3019797630
Short name	T97
Test name
Test status
Simulation time	19327484 ps
CPU time	0.78 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:32:55 PM PDT 24
Peak memory	200464 kb
Host	smart-5aed32f3-2f40-43ea-a381-46b38b8d414f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019797630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_idle_intersig_mubi.3019797630
Directory	/workspace/37.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.1786679142
Short name	T233
Test name
Test status
Simulation time	20992657 ps
CPU time	0.92 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:45 PM PDT 24
Peak memory	200588 kb
Host	smart-39bb7506-53ea-40c5-9f1d-facd8f9f8feb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786679142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 37.clkmgr_lc_clk_byp_req_intersig_mubi.1786679142
Directory	/workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.1080669488
Short name	T298
Test name
Test status
Simulation time	30809077 ps
CPU time	0.86 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	200556 kb
Host	smart-b6b13dbc-e1dd-4b10-8b40-766728bed6e3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080669488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 37.clkmgr_lc_ctrl_intersig_mubi.1080669488
Directory	/workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_peri.1193345962
Short name	T726
Test name
Test status
Simulation time	24309388 ps
CPU time	0.73 seconds
Started	Apr 18 01:32:46 PM PDT 24
Finished	Apr 18 01:32:51 PM PDT 24
Peak memory	200296 kb
Host	smart-79fd723f-0a63-40bd-a5e3-a78249968a94
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193345962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.1193345962
Directory	/workspace/37.clkmgr_peri/latest

Test location	/workspace/coverage/default/37.clkmgr_regwen.672989706
Short name	T141
Test name
Test status
Simulation time	998495215 ps
CPU time	5.55 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:54 PM PDT 24
Peak memory	200620 kb
Host	smart-c48f84f4-ed8e-467e-b14a-219c4d767d05
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672989706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.672989706
Directory	/workspace/37.clkmgr_regwen/latest

Test location	/workspace/coverage/default/37.clkmgr_smoke.3232868011
Short name	T768
Test name
Test status
Simulation time	32312101 ps
CPU time	0.86 seconds
Started	Apr 18 01:32:38 PM PDT 24
Finished	Apr 18 01:32:41 PM PDT 24
Peak memory	200524 kb
Host	smart-394c366d-4801-4175-b1f1-1d49b8dacdd3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232868011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.3232868011
Directory	/workspace/37.clkmgr_smoke/latest

Test location	/workspace/coverage/default/37.clkmgr_stress_all.291770909
Short name	T584
Test name
Test status
Simulation time	9960351925 ps
CPU time	38.57 seconds
Started	Apr 18 01:32:40 PM PDT 24
Finished	Apr 18 01:33:21 PM PDT 24
Peak memory	200948 kb
Host	smart-95ec2fb2-91cb-4bb3-aebf-0702d4777ef8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291770909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all.291770909
Directory	/workspace/37.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/37.clkmgr_stress_all_with_rand_reset.1087012868
Short name	T732
Test name
Test status
Simulation time	285732594994 ps
CPU time	1175.17 seconds
Started	Apr 18 01:32:50 PM PDT 24
Finished	Apr 18 01:52:27 PM PDT 24
Peak memory	209232 kb
Host	smart-076075a7-a491-4fce-9704-b05c73eb43d0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1087012868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.1087012868
Directory	/workspace/37.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.clkmgr_trans.2919539409
Short name	T730
Test name
Test status
Simulation time	85556727 ps
CPU time	1.04 seconds
Started	Apr 18 01:32:45 PM PDT 24
Finished	Apr 18 01:32:50 PM PDT 24
Peak memory	200520 kb
Host	smart-d1eb6851-f3fb-4f29-99be-4a9c05034e32
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919539409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.2919539409
Directory	/workspace/37.clkmgr_trans/latest

Test location	/workspace/coverage/default/38.clkmgr_alert_test.3480714162
Short name	T751
Test name
Test status
Simulation time	168601986 ps
CPU time	1.09 seconds
Started	Apr 18 01:32:48 PM PDT 24
Finished	Apr 18 01:32:53 PM PDT 24
Peak memory	200408 kb
Host	smart-d81890a1-f019-4bce-b959-dee9b880fd8a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480714162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk mgr_alert_test.3480714162
Directory	/workspace/38.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.3138351997
Short name	T86
Test name
Test status
Simulation time	105571939 ps
CPU time	0.98 seconds
Started	Apr 18 01:32:46 PM PDT 24
Finished	Apr 18 01:32:51 PM PDT 24
Peak memory	200580 kb
Host	smart-19fef9e8-c4e7-45ff-a807-fda1fdbc1e09
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138351997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_handshake_intersig_mubi.3138351997
Directory	/workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_clk_status.3321856420
Short name	T153
Test name
Test status
Simulation time	81389945 ps
CPU time	0.92 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:32:49 PM PDT 24
Peak memory	199512 kb
Host	smart-5cc6daf7-02d2-4844-a48b-6ff21107372f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321856420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.3321856420
Directory	/workspace/38.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/38.clkmgr_div_intersig_mubi.2481197039
Short name	T179
Test name
Test status
Simulation time	16182119 ps
CPU time	0.77 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:45 PM PDT 24
Peak memory	200756 kb
Host	smart-1edc5eae-2062-499c-9271-ecd88d5007e5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481197039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_div_intersig_mubi.2481197039
Directory	/workspace/38.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_extclk.2642234146
Short name	T211
Test name
Test status
Simulation time	19587512 ps
CPU time	0.77 seconds
Started	Apr 18 01:32:46 PM PDT 24
Finished	Apr 18 01:32:50 PM PDT 24
Peak memory	200548 kb
Host	smart-0f0164b5-7ebf-48a2-9974-52a1a78d9730
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642234146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.2642234146
Directory	/workspace/38.clkmgr_extclk/latest

Test location	/workspace/coverage/default/38.clkmgr_frequency.1982060565
Short name	T470
Test name
Test status
Simulation time	2362325828 ps
CPU time	12.4 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:59 PM PDT 24
Peak memory	200860 kb
Host	smart-50dcb96e-a9b6-4802-8091-f85acedb73e1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982060565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.1982060565
Directory	/workspace/38.clkmgr_frequency/latest

Test location	/workspace/coverage/default/38.clkmgr_frequency_timeout.604876928
Short name	T511
Test name
Test status
Simulation time	139126954 ps
CPU time	1.65 seconds
Started	Apr 18 01:32:40 PM PDT 24
Finished	Apr 18 01:32:44 PM PDT 24
Peak memory	200668 kb
Host	smart-d0791b29-2bf2-4537-843f-14f99568c032
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604876928 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_ti meout.604876928
Directory	/workspace/38.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/38.clkmgr_idle_intersig_mubi.2363395276
Short name	T719
Test name
Test status
Simulation time	15832121 ps
CPU time	0.74 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	200464 kb
Host	smart-02a80c5d-d20d-42f1-8c7c-72c1e8761a31
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363395276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_idle_intersig_mubi.2363395276
Directory	/workspace/38.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.2231929984
Short name	T542
Test name
Test status
Simulation time	22959494 ps
CPU time	0.83 seconds
Started	Apr 18 01:32:50 PM PDT 24
Finished	Apr 18 01:32:53 PM PDT 24
Peak memory	200556 kb
Host	smart-9251fd23-5560-4be1-a781-2f94c4c63c08
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231929984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 38.clkmgr_lc_clk_byp_req_intersig_mubi.2231929984
Directory	/workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.2070141209
Short name	T819
Test name
Test status
Simulation time	39769637 ps
CPU time	0.85 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	200580 kb
Host	smart-5adc5539-5784-46fc-9fd1-5e037d9ce210
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070141209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 38.clkmgr_lc_ctrl_intersig_mubi.2070141209
Directory	/workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_peri.2977507791
Short name	T461
Test name
Test status
Simulation time	14158942 ps
CPU time	0.71 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:32:42 PM PDT 24
Peak memory	200172 kb
Host	smart-0c974600-9f49-4140-87fa-5f216a643c04
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977507791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.2977507791
Directory	/workspace/38.clkmgr_peri/latest

Test location	/workspace/coverage/default/38.clkmgr_regwen.767745602
Short name	T690
Test name
Test status
Simulation time	472850011 ps
CPU time	2.98 seconds
Started	Apr 18 01:32:50 PM PDT 24
Finished	Apr 18 01:32:55 PM PDT 24
Peak memory	200560 kb
Host	smart-11ef92e7-55ca-4aee-be52-738662de2a6b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767745602 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.767745602
Directory	/workspace/38.clkmgr_regwen/latest

Test location	/workspace/coverage/default/38.clkmgr_smoke.1022698317
Short name	T595
Test name
Test status
Simulation time	18550057 ps
CPU time	0.83 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	200600 kb
Host	smart-dbdc5142-103b-41f8-bf97-8be901e3e119
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022698317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.1022698317
Directory	/workspace/38.clkmgr_smoke/latest

Test location	/workspace/coverage/default/38.clkmgr_stress_all.1760851745
Short name	T436
Test name
Test status
Simulation time	9844038873 ps
CPU time	39.1 seconds
Started	Apr 18 01:32:51 PM PDT 24
Finished	Apr 18 01:33:31 PM PDT 24
Peak memory	200964 kb
Host	smart-59523265-4e1a-4900-a517-19c527fcfde0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760851745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all.1760851745
Directory	/workspace/38.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/38.clkmgr_stress_all_with_rand_reset.2849377643
Short name	T817
Test name
Test status
Simulation time	493813546906 ps
CPU time	2211.17 seconds
Started	Apr 18 01:32:47 PM PDT 24
Finished	Apr 18 02:09:42 PM PDT 24
Peak memory	217436 kb
Host	smart-f14b6e1e-4c25-427f-954d-e368f1cda576
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2849377643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.2849377643
Directory	/workspace/38.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.clkmgr_trans.2165681434
Short name	T786
Test name
Test status
Simulation time	20661970 ps
CPU time	0.73 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	200468 kb
Host	smart-17aaa7e1-3914-446c-ad01-5179ef7129d4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165681434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.2165681434
Directory	/workspace/38.clkmgr_trans/latest

Test location	/workspace/coverage/default/39.clkmgr_alert_test.1859778512
Short name	T792
Test name
Test status
Simulation time	28067303 ps
CPU time	0.79 seconds
Started	Apr 18 01:32:48 PM PDT 24
Finished	Apr 18 01:32:51 PM PDT 24
Peak memory	200420 kb
Host	smart-63a967fb-1db2-449f-aabe-ce7357790040
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859778512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clk mgr_alert_test.1859778512
Directory	/workspace/39.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.1229300476
Short name	T450
Test name
Test status
Simulation time	58328025 ps
CPU time	0.95 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:32:49 PM PDT 24
Peak memory	200608 kb
Host	smart-2a57f3f0-fafb-4f45-affe-ef631a22fd94
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229300476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_handshake_intersig_mubi.1229300476
Directory	/workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_clk_status.3683711175
Short name	T148
Test name
Test status
Simulation time	79784622 ps
CPU time	0.83 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	200260 kb
Host	smart-4d2ea434-53bf-4b81-96be-82b6e659300e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683711175 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.3683711175
Directory	/workspace/39.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/39.clkmgr_div_intersig_mubi.2552139591
Short name	T335
Test name
Test status
Simulation time	22048144 ps
CPU time	0.78 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:46 PM PDT 24
Peak memory	200564 kb
Host	smart-5d8bd0a5-4f5e-4674-a3fc-6789507ae846
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552139591 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_div_intersig_mubi.2552139591
Directory	/workspace/39.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_extclk.1234001193
Short name	T681
Test name
Test status
Simulation time	35020138 ps
CPU time	0.78 seconds
Started	Apr 18 01:32:40 PM PDT 24
Finished	Apr 18 01:32:44 PM PDT 24
Peak memory	200536 kb
Host	smart-9fc4b4f1-e631-4eac-948d-b01cf2736fec
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234001193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.1234001193
Directory	/workspace/39.clkmgr_extclk/latest

Test location	/workspace/coverage/default/39.clkmgr_frequency.2869270938
Short name	T780
Test name
Test status
Simulation time	682832728 ps
CPU time	5.18 seconds
Started	Apr 18 01:32:45 PM PDT 24
Finished	Apr 18 01:32:54 PM PDT 24
Peak memory	200588 kb
Host	smart-e1e8b4f6-1e60-4713-9765-d522b0e2e7ea
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869270938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.2869270938
Directory	/workspace/39.clkmgr_frequency/latest

Test location	/workspace/coverage/default/39.clkmgr_frequency_timeout.4183280564
Short name	T66
Test name
Test status
Simulation time	1823206958 ps
CPU time	13.09 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:32:55 PM PDT 24
Peak memory	200688 kb
Host	smart-89fe5b87-07ad-4d6b-8796-844e2f664fc3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183280564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t imeout.4183280564
Directory	/workspace/39.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/39.clkmgr_idle_intersig_mubi.1202446545
Short name	T170
Test name
Test status
Simulation time	81499567 ps
CPU time	1 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:47 PM PDT 24
Peak memory	200556 kb
Host	smart-763e2247-5d08-4264-a5ef-e473bceda682
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202446545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_idle_intersig_mubi.1202446545
Directory	/workspace/39.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.1611508994
Short name	T452
Test name
Test status
Simulation time	27053569 ps
CPU time	0.85 seconds
Started	Apr 18 01:32:47 PM PDT 24
Finished	Apr 18 01:32:51 PM PDT 24
Peak memory	200636 kb
Host	smart-339f3177-8138-4a24-b7b6-d1f8052bb84b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611508994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 39.clkmgr_lc_clk_byp_req_intersig_mubi.1611508994
Directory	/workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.1096459788
Short name	T225
Test name
Test status
Simulation time	28755298 ps
CPU time	0.78 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:32:49 PM PDT 24
Peak memory	200592 kb
Host	smart-34f313f5-1472-48a6-bd5d-5933cb49e72f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096459788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 39.clkmgr_lc_ctrl_intersig_mubi.1096459788
Directory	/workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_peri.308836611
Short name	T591
Test name
Test status
Simulation time	16066793 ps
CPU time	0.73 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:47 PM PDT 24
Peak memory	200284 kb
Host	smart-d87d066e-133a-4082-948f-b87218b02f95
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308836611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.308836611
Directory	/workspace/39.clkmgr_peri/latest

Test location	/workspace/coverage/default/39.clkmgr_regwen.1572055432
Short name	T421
Test name
Test status
Simulation time	1253874158 ps
CPU time	4.74 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:32:53 PM PDT 24
Peak memory	200700 kb
Host	smart-67da267e-64fd-4beb-87b4-cf27f878ceb8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572055432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.1572055432
Directory	/workspace/39.clkmgr_regwen/latest

Test location	/workspace/coverage/default/39.clkmgr_smoke.477964967
Short name	T269
Test name
Test status
Simulation time	22936226 ps
CPU time	0.86 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	200524 kb
Host	smart-de0a1a3f-1a50-416d-a759-6514d2f3d946
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477964967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.477964967
Directory	/workspace/39.clkmgr_smoke/latest

Test location	/workspace/coverage/default/39.clkmgr_stress_all.3037850993
Short name	T704
Test name
Test status
Simulation time	5484001354 ps
CPU time	22.01 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:33:11 PM PDT 24
Peak memory	200976 kb
Host	smart-4d3ccfbb-2223-4838-8153-95c5921b12d3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037850993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all.3037850993
Directory	/workspace/39.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/39.clkmgr_stress_all_with_rand_reset.2376720735
Short name	T59
Test name
Test status
Simulation time	23301512695 ps
CPU time	201.78 seconds
Started	Apr 18 01:32:39 PM PDT 24
Finished	Apr 18 01:36:03 PM PDT 24
Peak memory	214488 kb
Host	smart-2c51572f-64e8-453b-aa3c-12645d5d4577
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2376720735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.2376720735
Directory	/workspace/39.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.clkmgr_trans.4235817012
Short name	T451
Test name
Test status
Simulation time	142934219 ps
CPU time	1.06 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	200452 kb
Host	smart-43363420-79f5-4a55-9102-f7e0498956d5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235817012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.4235817012
Directory	/workspace/39.clkmgr_trans/latest

Test location	/workspace/coverage/default/4.clkmgr_alert_test.1512386552
Short name	T23
Test name
Test status
Simulation time	19718265 ps
CPU time	0.72 seconds
Started	Apr 18 01:31:42 PM PDT 24
Finished	Apr 18 01:31:44 PM PDT 24
Peak memory	200464 kb
Host	smart-b411c753-98ad-4594-954a-a65260284fc5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512386552 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm gr_alert_test.1512386552
Directory	/workspace/4.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.1774565650
Short name	T242
Test name
Test status
Simulation time	92158516 ps
CPU time	1.09 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:54 PM PDT 24
Peak memory	200600 kb
Host	smart-85900a96-eb4c-4227-ba86-79b27348ddfe
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774565650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_handshake_intersig_mubi.1774565650
Directory	/workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_clk_status.1359427195
Short name	T154
Test name
Test status
Simulation time	173249311 ps
CPU time	1.07 seconds
Started	Apr 18 01:31:45 PM PDT 24
Finished	Apr 18 01:31:49 PM PDT 24
Peak memory	200260 kb
Host	smart-aae7d2fc-9bad-498a-a86b-2b4472eeb88c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359427195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.1359427195
Directory	/workspace/4.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/4.clkmgr_div_intersig_mubi.101790514
Short name	T382
Test name
Test status
Simulation time	24282388 ps
CPU time	0.89 seconds
Started	Apr 18 01:31:43 PM PDT 24
Finished	Apr 18 01:31:47 PM PDT 24
Peak memory	200540 kb
Host	smart-17dbbd1a-0815-47d4-b911-fd3a3ae84670
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101790514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .clkmgr_div_intersig_mubi.101790514
Directory	/workspace/4.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_extclk.3686771440
Short name	T177
Test name
Test status
Simulation time	33203119 ps
CPU time	0.96 seconds
Started	Apr 18 01:31:40 PM PDT 24
Finished	Apr 18 01:31:42 PM PDT 24
Peak memory	200628 kb
Host	smart-98ae165b-9482-47d1-a08f-071d37698549
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686771440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.3686771440
Directory	/workspace/4.clkmgr_extclk/latest

Test location	/workspace/coverage/default/4.clkmgr_frequency.596662716
Short name	T706
Test name
Test status
Simulation time	676191747 ps
CPU time	5.54 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:57 PM PDT 24
Peak memory	200596 kb
Host	smart-2780ab9d-4939-4216-a511-66ec74389a02
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596662716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.596662716
Directory	/workspace/4.clkmgr_frequency/latest

Test location	/workspace/coverage/default/4.clkmgr_frequency_timeout.1924980636
Short name	T251
Test name
Test status
Simulation time	1346131761 ps
CPU time	6.56 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:32:04 PM PDT 24
Peak memory	200740 kb
Host	smart-e1d4b298-fc73-4501-ba54-e970d9b3aae3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924980636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_ti meout.1924980636
Directory	/workspace/4.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/4.clkmgr_idle_intersig_mubi.91387173
Short name	T355
Test name
Test status
Simulation time	105810537 ps
CPU time	0.97 seconds
Started	Apr 18 01:31:43 PM PDT 24
Finished	Apr 18 01:31:46 PM PDT 24
Peak memory	200520 kb
Host	smart-c7b88611-510c-4fd5-bff9-73194ffd3f89
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91387173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4. clkmgr_idle_intersig_mubi.91387173
Directory	/workspace/4.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.2731042655
Short name	T274
Test name
Test status
Simulation time	17256637 ps
CPU time	0.84 seconds
Started	Apr 18 01:31:42 PM PDT 24
Finished	Apr 18 01:31:45 PM PDT 24
Peak memory	200536 kb
Host	smart-f1742577-5c32-406d-a29f-321380704f6e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731042655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 4.clkmgr_lc_clk_byp_req_intersig_mubi.2731042655
Directory	/workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.3934916565
Short name	T203
Test name
Test status
Simulation time	41440708 ps
CPU time	0.82 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200588 kb
Host	smart-34cafbd7-e224-41cf-8aaa-ed0aab3dba46
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934916565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 4.clkmgr_lc_ctrl_intersig_mubi.3934916565
Directory	/workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_peri.1575383510
Short name	T533
Test name
Test status
Simulation time	20634990 ps
CPU time	0.8 seconds
Started	Apr 18 01:31:43 PM PDT 24
Finished	Apr 18 01:31:46 PM PDT 24
Peak memory	200308 kb
Host	smart-d691fc43-bde4-49ca-b14f-4dac3a88a689
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575383510 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.1575383510
Directory	/workspace/4.clkmgr_peri/latest

Test location	/workspace/coverage/default/4.clkmgr_regwen.59794840
Short name	T613
Test name
Test status
Simulation time	943797021 ps
CPU time	3.59 seconds
Started	Apr 18 01:31:46 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200720 kb
Host	smart-36bd43f9-7a3f-44ad-b9b3-dfae2ffc7fb7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59794840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.59794840
Directory	/workspace/4.clkmgr_regwen/latest

Test location	/workspace/coverage/default/4.clkmgr_smoke.3715748913
Short name	T605
Test name
Test status
Simulation time	21543442 ps
CPU time	0.82 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200568 kb
Host	smart-07b4edc9-582e-42fc-8a27-1962b54c0bc0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715748913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.3715748913
Directory	/workspace/4.clkmgr_smoke/latest

Test location	/workspace/coverage/default/4.clkmgr_stress_all.1503114004
Short name	T758
Test name
Test status
Simulation time	5210926501 ps
CPU time	37.94 seconds
Started	Apr 18 01:31:39 PM PDT 24
Finished	Apr 18 01:32:18 PM PDT 24
Peak memory	200872 kb
Host	smart-1f9e98b9-7451-4fb7-b057-d4e75564b0bd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503114004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all.1503114004
Directory	/workspace/4.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/4.clkmgr_stress_all_with_rand_reset.377795110
Short name	T57
Test name
Test status
Simulation time	58255297308 ps
CPU time	791.32 seconds
Started	Apr 18 01:31:40 PM PDT 24
Finished	Apr 18 01:44:52 PM PDT 24
Peak memory	217488 kb
Host	smart-a857c743-30c3-4514-99ec-bda4b34efae2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=377795110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.377795110
Directory	/workspace/4.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.clkmgr_trans.248814677
Short name	T503
Test name
Test status
Simulation time	134069923 ps
CPU time	1.24 seconds
Started	Apr 18 01:31:45 PM PDT 24
Finished	Apr 18 01:31:49 PM PDT 24
Peak memory	200560 kb
Host	smart-619e1289-db90-4f34-9315-2e8cd42a1d5e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248814677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.248814677
Directory	/workspace/4.clkmgr_trans/latest

Test location	/workspace/coverage/default/40.clkmgr_alert_test.2746977514
Short name	T702
Test name
Test status
Simulation time	12043938 ps
CPU time	0.68 seconds
Started	Apr 18 01:32:48 PM PDT 24
Finished	Apr 18 01:32:52 PM PDT 24
Peak memory	200500 kb
Host	smart-828105d5-2282-4616-8064-4c3970971f50
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746977514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk mgr_alert_test.2746977514
Directory	/workspace/40.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.4238235899
Short name	T390
Test name
Test status
Simulation time	58594990 ps
CPU time	0.87 seconds
Started	Apr 18 01:32:47 PM PDT 24
Finished	Apr 18 01:32:51 PM PDT 24
Peak memory	200644 kb
Host	smart-3294b0ed-82f8-4e69-8241-c3195529c198
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238235899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_handshake_intersig_mubi.4238235899
Directory	/workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_clk_status.4257142097
Short name	T612
Test name
Test status
Simulation time	36618590 ps
CPU time	0.71 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:47 PM PDT 24
Peak memory	199504 kb
Host	smart-18537751-037f-466d-8645-757aa6dad2a7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257142097 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.4257142097
Directory	/workspace/40.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/40.clkmgr_div_intersig_mubi.3110254594
Short name	T228
Test name
Test status
Simulation time	17034207 ps
CPU time	0.71 seconds
Started	Apr 18 01:32:47 PM PDT 24
Finished	Apr 18 01:32:51 PM PDT 24
Peak memory	200548 kb
Host	smart-4e87d466-7bfb-4b02-a3fc-456379ebd56c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110254594 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_div_intersig_mubi.3110254594
Directory	/workspace/40.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_extclk.1568440916
Short name	T531
Test name
Test status
Simulation time	46093455 ps
CPU time	0.93 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:32:49 PM PDT 24
Peak memory	200488 kb
Host	smart-ad1a67b8-f992-4338-a6ad-a043d0600b4d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568440916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.1568440916
Directory	/workspace/40.clkmgr_extclk/latest

Test location	/workspace/coverage/default/40.clkmgr_frequency.4058562223
Short name	T367
Test name
Test status
Simulation time	1042755524 ps
CPU time	6.07 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:32:53 PM PDT 24
Peak memory	200604 kb
Host	smart-0929707f-dc58-44c5-bc67-5fedf18796b0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058562223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.4058562223
Directory	/workspace/40.clkmgr_frequency/latest

Test location	/workspace/coverage/default/40.clkmgr_frequency_timeout.1100165759
Short name	T424
Test name
Test status
Simulation time	620262244 ps
CPU time	4.9 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:52 PM PDT 24
Peak memory	200636 kb
Host	smart-6ffd4b9b-e8df-4022-a46b-64a68d5ed514
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100165759 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t imeout.1100165759
Directory	/workspace/40.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/40.clkmgr_idle_intersig_mubi.3415852463
Short name	T810
Test name
Test status
Simulation time	18471854 ps
CPU time	0.8 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:48 PM PDT 24
Peak memory	200496 kb
Host	smart-703b35a6-2258-4f31-b892-ecce89093f35
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415852463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_idle_intersig_mubi.3415852463
Directory	/workspace/40.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.1225356541
Short name	T25
Test name
Test status
Simulation time	65602377 ps
CPU time	0.9 seconds
Started	Apr 18 01:32:45 PM PDT 24
Finished	Apr 18 01:32:50 PM PDT 24
Peak memory	200460 kb
Host	smart-63ebb090-9fed-4df8-b3bd-f5a6b147cf83
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225356541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 40.clkmgr_lc_clk_byp_req_intersig_mubi.1225356541
Directory	/workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.2027051185
Short name	T229
Test name
Test status
Simulation time	250382567 ps
CPU time	1.55 seconds
Started	Apr 18 01:32:40 PM PDT 24
Finished	Apr 18 01:32:44 PM PDT 24
Peak memory	200520 kb
Host	smart-8b760c97-089b-4eb1-9dd2-6704aecbe4ee
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027051185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 40.clkmgr_lc_ctrl_intersig_mubi.2027051185
Directory	/workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_peri.4037934015
Short name	T299
Test name
Test status
Simulation time	16374060 ps
CPU time	0.77 seconds
Started	Apr 18 01:32:42 PM PDT 24
Finished	Apr 18 01:32:47 PM PDT 24
Peak memory	200300 kb
Host	smart-6e71096e-594a-4fd5-9fab-c6c55c72b4f8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037934015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.4037934015
Directory	/workspace/40.clkmgr_peri/latest

Test location	/workspace/coverage/default/40.clkmgr_regwen.2957398792
Short name	T455
Test name
Test status
Simulation time	717082163 ps
CPU time	4.36 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:32:53 PM PDT 24
Peak memory	200760 kb
Host	smart-a1fe24b2-573a-4bec-80c4-cfcb5467c3f4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957398792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.2957398792
Directory	/workspace/40.clkmgr_regwen/latest

Test location	/workspace/coverage/default/40.clkmgr_smoke.3318618715
Short name	T113
Test name
Test status
Simulation time	69713428 ps
CPU time	0.96 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:32:49 PM PDT 24
Peak memory	200212 kb
Host	smart-3658cf01-a772-486b-89de-20b68ee52b93
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318618715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.3318618715
Directory	/workspace/40.clkmgr_smoke/latest

Test location	/workspace/coverage/default/40.clkmgr_stress_all.465999756
Short name	T67
Test name
Test status
Simulation time	13093539330 ps
CPU time	58.34 seconds
Started	Apr 18 01:32:44 PM PDT 24
Finished	Apr 18 01:33:46 PM PDT 24
Peak memory	200588 kb
Host	smart-70d6a202-351e-464f-a2a8-6dc453c8998d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465999756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all.465999756
Directory	/workspace/40.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/40.clkmgr_stress_all_with_rand_reset.1315153223
Short name	T142
Test name
Test status
Simulation time	50865554999 ps
CPU time	414.44 seconds
Started	Apr 18 01:32:47 PM PDT 24
Finished	Apr 18 01:39:45 PM PDT 24
Peak memory	209128 kb
Host	smart-5d068663-5da6-4afc-99c8-eef0a470dc22
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1315153223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.1315153223
Directory	/workspace/40.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.clkmgr_trans.4261495341
Short name	T834
Test name
Test status
Simulation time	29843859 ps
CPU time	0.84 seconds
Started	Apr 18 01:32:41 PM PDT 24
Finished	Apr 18 01:32:45 PM PDT 24
Peak memory	200460 kb
Host	smart-ca2e8ce6-8cc5-4c58-8cd3-06a19d2df000
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261495341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.4261495341
Directory	/workspace/40.clkmgr_trans/latest

Test location	/workspace/coverage/default/41.clkmgr_alert_test.2514939655
Short name	T380
Test name
Test status
Simulation time	26173664 ps
CPU time	0.77 seconds
Started	Apr 18 01:32:50 PM PDT 24
Finished	Apr 18 01:32:53 PM PDT 24
Peak memory	200484 kb
Host	smart-890ba43c-c046-4fe6-b14a-2e7544214281
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514939655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk mgr_alert_test.2514939655
Directory	/workspace/41.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.1062112013
Short name	T259
Test name
Test status
Simulation time	15242563 ps
CPU time	0.73 seconds
Started	Apr 18 01:32:49 PM PDT 24
Finished	Apr 18 01:32:52 PM PDT 24
Peak memory	200552 kb
Host	smart-0a4cecf3-5e24-4593-8694-a95a0ff57227
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062112013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_handshake_intersig_mubi.1062112013
Directory	/workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_clk_status.2699451111
Short name	T342
Test name
Test status
Simulation time	37049048 ps
CPU time	0.79 seconds
Started	Apr 18 01:32:52 PM PDT 24
Finished	Apr 18 01:32:54 PM PDT 24
Peak memory	200212 kb
Host	smart-e38dd632-01bc-46f7-8727-34b3ae26bdbf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699451111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.2699451111
Directory	/workspace/41.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/41.clkmgr_div_intersig_mubi.3863005348
Short name	T313
Test name
Test status
Simulation time	19973725 ps
CPU time	0.81 seconds
Started	Apr 18 01:32:47 PM PDT 24
Finished	Apr 18 01:32:52 PM PDT 24
Peak memory	200552 kb
Host	smart-9d7b0ee0-8c06-4f5c-981f-84fc51ad129c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863005348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_div_intersig_mubi.3863005348
Directory	/workspace/41.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_extclk.1042169410
Short name	T504
Test name
Test status
Simulation time	59622282 ps
CPU time	0.9 seconds
Started	Apr 18 01:32:57 PM PDT 24
Finished	Apr 18 01:32:58 PM PDT 24
Peak memory	200560 kb
Host	smart-16576620-f3cb-40a0-9b92-bf027fa8eed1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042169410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.1042169410
Directory	/workspace/41.clkmgr_extclk/latest

Test location	/workspace/coverage/default/41.clkmgr_frequency.2792350055
Short name	T423
Test name
Test status
Simulation time	2122050195 ps
CPU time	16.85 seconds
Started	Apr 18 01:32:43 PM PDT 24
Finished	Apr 18 01:33:05 PM PDT 24
Peak memory	200788 kb
Host	smart-6fb02643-925b-456b-8a3d-5a8ac310a66e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792350055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.2792350055
Directory	/workspace/41.clkmgr_frequency/latest

Test location	/workspace/coverage/default/41.clkmgr_frequency_timeout.3523596075
Short name	T205
Test name
Test status
Simulation time	857348836 ps
CPU time	6.25 seconds
Started	Apr 18 01:32:47 PM PDT 24
Finished	Apr 18 01:32:57 PM PDT 24
Peak memory	200668 kb
Host	smart-4b74b416-3e1a-4ad6-a999-d29e6f944d49
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523596075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_t imeout.3523596075
Directory	/workspace/41.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/41.clkmgr_idle_intersig_mubi.1129532900
Short name	T178
Test name
Test status
Simulation time	154364698 ps
CPU time	1.29 seconds
Started	Apr 18 01:32:46 PM PDT 24
Finished	Apr 18 01:32:51 PM PDT 24
Peak memory	200492 kb
Host	smart-c312af0c-15a4-4972-894b-607eb9b6875e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129532900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_idle_intersig_mubi.1129532900
Directory	/workspace/41.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.1760149947
Short name	T674
Test name
Test status
Simulation time	26615287 ps
CPU time	0.8 seconds
Started	Apr 18 01:32:52 PM PDT 24
Finished	Apr 18 01:32:54 PM PDT 24
Peak memory	200568 kb
Host	smart-cccb78f0-983a-4655-9811-a9b5ddcfdc22
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760149947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 41.clkmgr_lc_clk_byp_req_intersig_mubi.1760149947
Directory	/workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.3034104208
Short name	T688
Test name
Test status
Simulation time	18376171 ps
CPU time	0.8 seconds
Started	Apr 18 01:32:50 PM PDT 24
Finished	Apr 18 01:32:53 PM PDT 24
Peak memory	200560 kb
Host	smart-e90e4246-9e5c-410b-b470-93e50f1ca3d8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034104208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 41.clkmgr_lc_ctrl_intersig_mubi.3034104208
Directory	/workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_peri.446878055
Short name	T224
Test name
Test status
Simulation time	18138686 ps
CPU time	0.76 seconds
Started	Apr 18 01:32:50 PM PDT 24
Finished	Apr 18 01:32:52 PM PDT 24
Peak memory	200332 kb
Host	smart-28a9720c-ea16-4ab4-9dec-7e894e7e3d48
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446878055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.446878055
Directory	/workspace/41.clkmgr_peri/latest

Test location	/workspace/coverage/default/41.clkmgr_regwen.3188605009
Short name	T648
Test name
Test status
Simulation time	1277657900 ps
CPU time	4.75 seconds
Started	Apr 18 01:32:47 PM PDT 24
Finished	Apr 18 01:32:55 PM PDT 24
Peak memory	200724 kb
Host	smart-d47894db-0ae8-47db-8f33-0fe1518390cb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188605009 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.3188605009
Directory	/workspace/41.clkmgr_regwen/latest

Test location	/workspace/coverage/default/41.clkmgr_smoke.3124012742
Short name	T191
Test name
Test status
Simulation time	48735655 ps
CPU time	0.87 seconds
Started	Apr 18 01:32:46 PM PDT 24
Finished	Apr 18 01:32:51 PM PDT 24
Peak memory	200564 kb
Host	smart-1a54c943-8f2f-4cb0-9da3-e0709168269f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124012742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.3124012742
Directory	/workspace/41.clkmgr_smoke/latest

Test location	/workspace/coverage/default/41.clkmgr_stress_all.1034153896
Short name	T839
Test name
Test status
Simulation time	2447677312 ps
CPU time	17.55 seconds
Started	Apr 18 01:33:02 PM PDT 24
Finished	Apr 18 01:33:20 PM PDT 24
Peak memory	200920 kb
Host	smart-38435494-c75d-4371-ab5e-8aa6dd5088e7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034153896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all.1034153896
Directory	/workspace/41.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/41.clkmgr_stress_all_with_rand_reset.1541694721
Short name	T734
Test name
Test status
Simulation time	121927827768 ps
CPU time	1086.86 seconds
Started	Apr 18 01:32:59 PM PDT 24
Finished	Apr 18 01:51:06 PM PDT 24
Peak memory	217380 kb
Host	smart-3ef7ba62-995c-4997-990a-4e62ee4ba1dd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1541694721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.1541694721
Directory	/workspace/41.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.clkmgr_trans.3983723891
Short name	T805
Test name
Test status
Simulation time	38081499 ps
CPU time	0.84 seconds
Started	Apr 18 01:32:49 PM PDT 24
Finished	Apr 18 01:32:52 PM PDT 24
Peak memory	200400 kb
Host	smart-69a20920-693f-407f-981d-c2ba5073cd72
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983723891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.3983723891
Directory	/workspace/41.clkmgr_trans/latest

Test location	/workspace/coverage/default/42.clkmgr_alert_test.3899962511
Short name	T303
Test name
Test status
Simulation time	14037656 ps
CPU time	0.71 seconds
Started	Apr 18 01:33:05 PM PDT 24
Finished	Apr 18 01:33:06 PM PDT 24
Peak memory	200460 kb
Host	smart-3c5e80a6-a1cd-4262-b32d-274f840362f4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899962511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk mgr_alert_test.3899962511
Directory	/workspace/42.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.853779237
Short name	T481
Test name
Test status
Simulation time	181614858 ps
CPU time	1.33 seconds
Started	Apr 18 01:33:09 PM PDT 24
Finished	Apr 18 01:33:11 PM PDT 24
Peak memory	200596 kb
Host	smart-0a868405-ad07-418c-91db-8ec5451c8363
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853779237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_handshake_intersig_mubi.853779237
Directory	/workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_clk_status.583960607
Short name	T636
Test name
Test status
Simulation time	17222145 ps
CPU time	0.72 seconds
Started	Apr 18 01:32:56 PM PDT 24
Finished	Apr 18 01:32:58 PM PDT 24
Peak memory	200260 kb
Host	smart-3388e347-de38-43e1-acda-5b3958db881c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583960607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.583960607
Directory	/workspace/42.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/42.clkmgr_div_intersig_mubi.4046463375
Short name	T182
Test name
Test status
Simulation time	19945991 ps
CPU time	0.88 seconds
Started	Apr 18 01:32:59 PM PDT 24
Finished	Apr 18 01:33:00 PM PDT 24
Peak memory	200488 kb
Host	smart-0db2e94e-2869-43cf-8a80-aaeed242913e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046463375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_div_intersig_mubi.4046463375
Directory	/workspace/42.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_extclk.2296485453
Short name	T668
Test name
Test status
Simulation time	26422563 ps
CPU time	0.76 seconds
Started	Apr 18 01:32:49 PM PDT 24
Finished	Apr 18 01:32:52 PM PDT 24
Peak memory	200572 kb
Host	smart-5e2adc7b-74fa-468e-bb3e-613ae6d1278d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296485453 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.2296485453
Directory	/workspace/42.clkmgr_extclk/latest

Test location	/workspace/coverage/default/42.clkmgr_frequency.2534714489
Short name	T466
Test name
Test status
Simulation time	563158470 ps
CPU time	4.76 seconds
Started	Apr 18 01:32:52 PM PDT 24
Finished	Apr 18 01:32:58 PM PDT 24
Peak memory	200544 kb
Host	smart-f5014c5d-924f-4431-9dfc-9c7c2dc083b2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534714489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.2534714489
Directory	/workspace/42.clkmgr_frequency/latest

Test location	/workspace/coverage/default/42.clkmgr_frequency_timeout.2983756504
Short name	T315
Test name
Test status
Simulation time	659458048 ps
CPU time	3 seconds
Started	Apr 18 01:32:48 PM PDT 24
Finished	Apr 18 01:32:55 PM PDT 24
Peak memory	200628 kb
Host	smart-ee0bd15d-9b57-4399-85a2-228345a11312
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983756504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t imeout.2983756504
Directory	/workspace/42.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/42.clkmgr_idle_intersig_mubi.1999751944
Short name	T237
Test name
Test status
Simulation time	88936115 ps
CPU time	1.07 seconds
Started	Apr 18 01:32:56 PM PDT 24
Finished	Apr 18 01:32:58 PM PDT 24
Peak memory	200572 kb
Host	smart-b052637d-8d7c-40f2-bcdf-e370cabd96e3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999751944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_idle_intersig_mubi.1999751944
Directory	/workspace/42.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.3364568824
Short name	T699
Test name
Test status
Simulation time	14287394 ps
CPU time	0.79 seconds
Started	Apr 18 01:33:09 PM PDT 24
Finished	Apr 18 01:33:10 PM PDT 24
Peak memory	200608 kb
Host	smart-88b3d857-2285-4e44-adc9-e7c41479aa42
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364568824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 42.clkmgr_lc_clk_byp_req_intersig_mubi.3364568824
Directory	/workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.605935837
Short name	T352
Test name
Test status
Simulation time	38264815 ps
CPU time	0.82 seconds
Started	Apr 18 01:33:15 PM PDT 24
Finished	Apr 18 01:33:16 PM PDT 24
Peak memory	200584 kb
Host	smart-aa9b0ba0-6f8c-49db-8bcd-d3d5ef8282d9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605935837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.clkmgr_lc_ctrl_intersig_mubi.605935837
Directory	/workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_peri.309914340
Short name	T492
Test name
Test status
Simulation time	19993467 ps
CPU time	0.79 seconds
Started	Apr 18 01:32:50 PM PDT 24
Finished	Apr 18 01:32:52 PM PDT 24
Peak memory	200232 kb
Host	smart-c7a4ffe3-cd2e-40c8-bcd3-ec9165e34566
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309914340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.309914340
Directory	/workspace/42.clkmgr_peri/latest

Test location	/workspace/coverage/default/42.clkmgr_regwen.3579978290
Short name	T230
Test name
Test status
Simulation time	424565501 ps
CPU time	2.71 seconds
Started	Apr 18 01:33:06 PM PDT 24
Finished	Apr 18 01:33:09 PM PDT 24
Peak memory	200564 kb
Host	smart-2ba2d47d-1547-4e58-a4ac-5285c14e2e27
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579978290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.3579978290
Directory	/workspace/42.clkmgr_regwen/latest

Test location	/workspace/coverage/default/42.clkmgr_smoke.1586769030
Short name	T797
Test name
Test status
Simulation time	15329748 ps
CPU time	0.81 seconds
Started	Apr 18 01:32:52 PM PDT 24
Finished	Apr 18 01:32:54 PM PDT 24
Peak memory	200572 kb
Host	smart-dbade336-e7a9-4f73-baa2-b1eda179149f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586769030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.1586769030
Directory	/workspace/42.clkmgr_smoke/latest

Test location	/workspace/coverage/default/42.clkmgr_stress_all.4261110645
Short name	T779
Test name
Test status
Simulation time	8180440843 ps
CPU time	31.52 seconds
Started	Apr 18 01:33:12 PM PDT 24
Finished	Apr 18 01:33:44 PM PDT 24
Peak memory	200964 kb
Host	smart-69f846e7-6ad5-4f65-a58a-4d269f20f61b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261110645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all.4261110645
Directory	/workspace/42.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.894978578
Short name	T409
Test name
Test status
Simulation time	33335432118 ps
CPU time	494.42 seconds
Started	Apr 18 01:32:55 PM PDT 24
Finished	Apr 18 01:41:10 PM PDT 24
Peak memory	217348 kb
Host	smart-19896773-25cc-446f-8d19-af46e891a915
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=894978578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.894978578
Directory	/workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.clkmgr_trans.3248194027
Short name	T317
Test name
Test status
Simulation time	32430571 ps
CPU time	0.87 seconds
Started	Apr 18 01:33:29 PM PDT 24
Finished	Apr 18 01:33:31 PM PDT 24
Peak memory	200576 kb
Host	smart-376b4162-1c35-4de9-ae02-8876342d45e4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248194027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.3248194027
Directory	/workspace/42.clkmgr_trans/latest

Test location	/workspace/coverage/default/43.clkmgr_alert_test.3404739729
Short name	T506
Test name
Test status
Simulation time	22651825 ps
CPU time	0.82 seconds
Started	Apr 18 01:33:14 PM PDT 24
Finished	Apr 18 01:33:15 PM PDT 24
Peak memory	200408 kb
Host	smart-6f21398b-28e4-4b41-968e-2da0139bbeed
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404739729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk mgr_alert_test.3404739729
Directory	/workspace/43.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.857690094
Short name	T414
Test name
Test status
Simulation time	13012824 ps
CPU time	0.71 seconds
Started	Apr 18 01:32:57 PM PDT 24
Finished	Apr 18 01:32:58 PM PDT 24
Peak memory	200544 kb
Host	smart-e49fcda7-6b03-490d-8336-888b88469de2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857690094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_handshake_intersig_mubi.857690094
Directory	/workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_clk_status.1422339628
Short name	T61
Test name
Test status
Simulation time	30064496 ps
CPU time	0.71 seconds
Started	Apr 18 01:33:20 PM PDT 24
Finished	Apr 18 01:33:22 PM PDT 24
Peak memory	199520 kb
Host	smart-ec2d6936-5729-4ba0-9085-5b5564e8d745
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422339628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.1422339628
Directory	/workspace/43.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/43.clkmgr_div_intersig_mubi.2077227372
Short name	T311
Test name
Test status
Simulation time	20142124 ps
CPU time	0.81 seconds
Started	Apr 18 01:33:10 PM PDT 24
Finished	Apr 18 01:33:11 PM PDT 24
Peak memory	200580 kb
Host	smart-30c5fd54-bb97-4ed2-8051-648b8079f8c8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077227372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_div_intersig_mubi.2077227372
Directory	/workspace/43.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_extclk.4139313921
Short name	T796
Test name
Test status
Simulation time	21791526 ps
CPU time	0.81 seconds
Started	Apr 18 01:32:53 PM PDT 24
Finished	Apr 18 01:32:54 PM PDT 24
Peak memory	200460 kb
Host	smart-347ede32-c1aa-4c70-98c6-3c9951c020df
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139313921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.4139313921
Directory	/workspace/43.clkmgr_extclk/latest

Test location	/workspace/coverage/default/43.clkmgr_frequency.4014925531
Short name	T625
Test name
Test status
Simulation time	1481945766 ps
CPU time	6.39 seconds
Started	Apr 18 01:33:05 PM PDT 24
Finished	Apr 18 01:33:12 PM PDT 24
Peak memory	200580 kb
Host	smart-ffa4963e-1b28-4390-9e79-79fc874abc66
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014925531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.4014925531
Directory	/workspace/43.clkmgr_frequency/latest

Test location	/workspace/coverage/default/43.clkmgr_frequency_timeout.1611111813
Short name	T318
Test name
Test status
Simulation time	268825207 ps
CPU time	1.93 seconds
Started	Apr 18 01:33:06 PM PDT 24
Finished	Apr 18 01:33:08 PM PDT 24
Peak memory	200620 kb
Host	smart-f3dbf406-73d4-4add-a616-1b87779d74bc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611111813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t imeout.1611111813
Directory	/workspace/43.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/43.clkmgr_idle_intersig_mubi.446358776
Short name	T577
Test name
Test status
Simulation time	27625558 ps
CPU time	0.95 seconds
Started	Apr 18 01:32:59 PM PDT 24
Finished	Apr 18 01:33:01 PM PDT 24
Peak memory	200476 kb
Host	smart-7899a740-572d-48cf-84a4-0a5639557bfb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446358776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.clkmgr_idle_intersig_mubi.446358776
Directory	/workspace/43.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.1532553798
Short name	T582
Test name
Test status
Simulation time	24580577 ps
CPU time	0.83 seconds
Started	Apr 18 01:33:12 PM PDT 24
Finished	Apr 18 01:33:13 PM PDT 24
Peak memory	200576 kb
Host	smart-0baff9a6-0fd0-42dd-9404-5121dfa4f23b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532553798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 43.clkmgr_lc_clk_byp_req_intersig_mubi.1532553798
Directory	/workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.2244687753
Short name	T741
Test name
Test status
Simulation time	106112500 ps
CPU time	1.11 seconds
Started	Apr 18 01:32:56 PM PDT 24
Finished	Apr 18 01:32:58 PM PDT 24
Peak memory	200560 kb
Host	smart-bacd6576-fb10-4017-82d3-9ea728e95570
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244687753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 43.clkmgr_lc_ctrl_intersig_mubi.2244687753
Directory	/workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_peri.3681413156
Short name	T844
Test name
Test status
Simulation time	89539823 ps
CPU time	0.92 seconds
Started	Apr 18 01:33:09 PM PDT 24
Finished	Apr 18 01:33:10 PM PDT 24
Peak memory	200272 kb
Host	smart-fe758056-32b1-4c9a-8c3a-a73d1cf7175c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681413156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.3681413156
Directory	/workspace/43.clkmgr_peri/latest

Test location	/workspace/coverage/default/43.clkmgr_regwen.2063534979
Short name	T138
Test name
Test status
Simulation time	322574270 ps
CPU time	1.88 seconds
Started	Apr 18 01:33:11 PM PDT 24
Finished	Apr 18 01:33:14 PM PDT 24
Peak memory	200504 kb
Host	smart-e876075f-3842-4f63-bcca-680c96bc8744
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063534979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.2063534979
Directory	/workspace/43.clkmgr_regwen/latest

Test location	/workspace/coverage/default/43.clkmgr_smoke.606276316
Short name	T227
Test name
Test status
Simulation time	21835645 ps
CPU time	0.87 seconds
Started	Apr 18 01:32:57 PM PDT 24
Finished	Apr 18 01:32:59 PM PDT 24
Peak memory	200572 kb
Host	smart-e324c5f4-9068-4d31-ad87-34e9946f256a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606276316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.606276316
Directory	/workspace/43.clkmgr_smoke/latest

Test location	/workspace/coverage/default/43.clkmgr_stress_all.625695706
Short name	T133
Test name
Test status
Simulation time	723394739 ps
CPU time	3.24 seconds
Started	Apr 18 01:33:04 PM PDT 24
Finished	Apr 18 01:33:08 PM PDT 24
Peak memory	200704 kb
Host	smart-167cc647-06f6-4a70-b271-37dc0080675e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625695706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all.625695706
Directory	/workspace/43.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/43.clkmgr_stress_all_with_rand_reset.488346476
Short name	T785
Test name
Test status
Simulation time	33273617880 ps
CPU time	469.61 seconds
Started	Apr 18 01:33:12 PM PDT 24
Finished	Apr 18 01:41:02 PM PDT 24
Peak memory	209228 kb
Host	smart-06017eba-c754-40ac-88bc-97c261eeb3d4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=488346476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.488346476
Directory	/workspace/43.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.clkmgr_trans.4064062471
Short name	T691
Test name
Test status
Simulation time	99590014 ps
CPU time	1.11 seconds
Started	Apr 18 01:32:56 PM PDT 24
Finished	Apr 18 01:32:58 PM PDT 24
Peak memory	200752 kb
Host	smart-b3da3873-0531-4e6e-bcb3-2df66411e0a7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064062471 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.4064062471
Directory	/workspace/43.clkmgr_trans/latest

Test location	/workspace/coverage/default/44.clkmgr_alert_test.1170352320
Short name	T475
Test name
Test status
Simulation time	28626467 ps
CPU time	0.93 seconds
Started	Apr 18 01:33:28 PM PDT 24
Finished	Apr 18 01:33:29 PM PDT 24
Peak memory	200632 kb
Host	smart-78f496ef-b4db-414d-afdd-7a4ea7610765
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170352320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clk mgr_alert_test.1170352320
Directory	/workspace/44.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.537816974
Short name	T260
Test name
Test status
Simulation time	81931453 ps
CPU time	1.1 seconds
Started	Apr 18 01:33:21 PM PDT 24
Finished	Apr 18 01:33:23 PM PDT 24
Peak memory	200528 kb
Host	smart-3fb3309d-54b7-4f76-ad38-62049a6354d8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537816974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_handshake_intersig_mubi.537816974
Directory	/workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_clk_status.3149714643
Short name	T398
Test name
Test status
Simulation time	46474354 ps
CPU time	0.79 seconds
Started	Apr 18 01:33:11 PM PDT 24
Finished	Apr 18 01:33:12 PM PDT 24
Peak memory	199448 kb
Host	smart-a33ce0ed-ca53-44a7-8656-994f51e34a5e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149714643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.3149714643
Directory	/workspace/44.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/44.clkmgr_div_intersig_mubi.869912157
Short name	T82
Test name
Test status
Simulation time	26590184 ps
CPU time	0.81 seconds
Started	Apr 18 01:33:12 PM PDT 24
Finished	Apr 18 01:33:13 PM PDT 24
Peak memory	200568 kb
Host	smart-33925d60-1e2d-4d9d-b0c7-1fbcf281d959
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869912157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.clkmgr_div_intersig_mubi.869912157
Directory	/workspace/44.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_extclk.3013554794
Short name	T457
Test name
Test status
Simulation time	24905530 ps
CPU time	0.88 seconds
Started	Apr 18 01:33:00 PM PDT 24
Finished	Apr 18 01:33:02 PM PDT 24
Peak memory	200572 kb
Host	smart-3cc969e6-ccf6-4963-a74f-ab59d619791e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013554794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.3013554794
Directory	/workspace/44.clkmgr_extclk/latest

Test location	/workspace/coverage/default/44.clkmgr_frequency.795535807
Short name	T462
Test name
Test status
Simulation time	808894903 ps
CPU time	5.23 seconds
Started	Apr 18 01:33:06 PM PDT 24
Finished	Apr 18 01:33:12 PM PDT 24
Peak memory	200592 kb
Host	smart-7351a3dc-a3d0-4e64-939d-114ce858095a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795535807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.795535807
Directory	/workspace/44.clkmgr_frequency/latest

Test location	/workspace/coverage/default/44.clkmgr_frequency_timeout.1836419267
Short name	T490
Test name
Test status
Simulation time	380904945 ps
CPU time	2.93 seconds
Started	Apr 18 01:33:13 PM PDT 24
Finished	Apr 18 01:33:16 PM PDT 24
Peak memory	200600 kb
Host	smart-2d8f8006-c835-4d09-9c5a-b10421adab30
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836419267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t imeout.1836419267
Directory	/workspace/44.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/44.clkmgr_idle_intersig_mubi.3789155065
Short name	T365
Test name
Test status
Simulation time	30304793 ps
CPU time	1.02 seconds
Started	Apr 18 01:33:08 PM PDT 24
Finished	Apr 18 01:33:10 PM PDT 24
Peak memory	200712 kb
Host	smart-676218d8-260c-4d8c-931e-694ebef5c480
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789155065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_idle_intersig_mubi.3789155065
Directory	/workspace/44.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.1637612487
Short name	T646
Test name
Test status
Simulation time	22794154 ps
CPU time	0.87 seconds
Started	Apr 18 01:33:19 PM PDT 24
Finished	Apr 18 01:33:21 PM PDT 24
Peak memory	200576 kb
Host	smart-6a58cd21-8f12-4632-aa4b-7a1d3e7561c9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637612487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 44.clkmgr_lc_clk_byp_req_intersig_mubi.1637612487
Directory	/workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.2427716609
Short name	T136
Test name
Test status
Simulation time	99889318 ps
CPU time	1.14 seconds
Started	Apr 18 01:33:16 PM PDT 24
Finished	Apr 18 01:33:17 PM PDT 24
Peak memory	200588 kb
Host	smart-68c2dbfc-3d3a-4099-ac49-e128f66f71a8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427716609 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 44.clkmgr_lc_ctrl_intersig_mubi.2427716609
Directory	/workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_peri.508179094
Short name	T347
Test name
Test status
Simulation time	33427333 ps
CPU time	0.81 seconds
Started	Apr 18 01:33:09 PM PDT 24
Finished	Apr 18 01:33:10 PM PDT 24
Peak memory	200216 kb
Host	smart-635d9180-7928-495c-8f34-412f11974b2a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508179094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.508179094
Directory	/workspace/44.clkmgr_peri/latest

Test location	/workspace/coverage/default/44.clkmgr_regwen.507379179
Short name	T354
Test name
Test status
Simulation time	768759729 ps
CPU time	4.4 seconds
Started	Apr 18 01:33:17 PM PDT 24
Finished	Apr 18 01:33:22 PM PDT 24
Peak memory	200776 kb
Host	smart-fc9bfd01-e57a-482a-a67f-00320220ed51
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507379179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.507379179
Directory	/workspace/44.clkmgr_regwen/latest

Test location	/workspace/coverage/default/44.clkmgr_smoke.1869329590
Short name	T700
Test name
Test status
Simulation time	26613687 ps
CPU time	0.82 seconds
Started	Apr 18 01:33:06 PM PDT 24
Finished	Apr 18 01:33:07 PM PDT 24
Peak memory	200552 kb
Host	smart-11451e82-40c9-4050-bbb1-e741dfa98699
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869329590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.1869329590
Directory	/workspace/44.clkmgr_smoke/latest

Test location	/workspace/coverage/default/44.clkmgr_stress_all.4112169924
Short name	T31
Test name
Test status
Simulation time	2323216968 ps
CPU time	15.42 seconds
Started	Apr 18 01:33:16 PM PDT 24
Finished	Apr 18 01:33:32 PM PDT 24
Peak memory	200944 kb
Host	smart-ad36a959-4e3b-49f2-82ea-153c405e6fa2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112169924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all.4112169924
Directory	/workspace/44.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/44.clkmgr_stress_all_with_rand_reset.939804672
Short name	T806
Test name
Test status
Simulation time	122831179064 ps
CPU time	837.53 seconds
Started	Apr 18 01:33:05 PM PDT 24
Finished	Apr 18 01:47:03 PM PDT 24
Peak memory	214264 kb
Host	smart-ec892ec5-01a5-4046-a83a-a1b23ce9da6c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=939804672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.939804672
Directory	/workspace/44.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.clkmgr_trans.1004981998
Short name	T474
Test name
Test status
Simulation time	124339238 ps
CPU time	1.14 seconds
Started	Apr 18 01:33:10 PM PDT 24
Finished	Apr 18 01:33:11 PM PDT 24
Peak memory	200576 kb
Host	smart-814e6b45-4ec4-4555-8c7c-a4b6f808d993
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004981998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.1004981998
Directory	/workspace/44.clkmgr_trans/latest

Test location	/workspace/coverage/default/45.clkmgr_alert_test.554377916
Short name	T43
Test name
Test status
Simulation time	139982463 ps
CPU time	1.08 seconds
Started	Apr 18 01:33:13 PM PDT 24
Finished	Apr 18 01:33:15 PM PDT 24
Peak memory	200428 kb
Host	smart-f06bf495-eec7-4da9-91fa-1686376f1336
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554377916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkm gr_alert_test.554377916
Directory	/workspace/45.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.2148958687
Short name	T331
Test name
Test status
Simulation time	16867111 ps
CPU time	0.75 seconds
Started	Apr 18 01:33:12 PM PDT 24
Finished	Apr 18 01:33:13 PM PDT 24
Peak memory	200544 kb
Host	smart-b170d28b-689a-434f-82a3-44b23b3a86e9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148958687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_handshake_intersig_mubi.2148958687
Directory	/workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_clk_status.1887155027
Short name	T770
Test name
Test status
Simulation time	23780671 ps
CPU time	0.68 seconds
Started	Apr 18 01:33:10 PM PDT 24
Finished	Apr 18 01:33:11 PM PDT 24
Peak memory	199496 kb
Host	smart-97213028-bbad-403f-85e3-e8ae34b50a34
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887155027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.1887155027
Directory	/workspace/45.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/45.clkmgr_div_intersig_mubi.3727718388
Short name	T275
Test name
Test status
Simulation time	20575746 ps
CPU time	0.79 seconds
Started	Apr 18 01:33:26 PM PDT 24
Finished	Apr 18 01:33:27 PM PDT 24
Peak memory	200624 kb
Host	smart-ee400f9c-28a3-4598-9877-2e8242467f4b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727718388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_div_intersig_mubi.3727718388
Directory	/workspace/45.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_extclk.1142630867
Short name	T548
Test name
Test status
Simulation time	18785842 ps
CPU time	0.79 seconds
Started	Apr 18 01:33:10 PM PDT 24
Finished	Apr 18 01:33:11 PM PDT 24
Peak memory	200572 kb
Host	smart-2afd194c-7f39-40a0-a810-b57060f1634f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142630867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.1142630867
Directory	/workspace/45.clkmgr_extclk/latest

Test location	/workspace/coverage/default/45.clkmgr_frequency.3849573434
Short name	T420
Test name
Test status
Simulation time	2117312250 ps
CPU time	16.47 seconds
Started	Apr 18 01:33:10 PM PDT 24
Finished	Apr 18 01:33:27 PM PDT 24
Peak memory	200720 kb
Host	smart-310aa65a-91c9-4e3e-87c6-22a62fd36d5e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849573434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.3849573434
Directory	/workspace/45.clkmgr_frequency/latest

Test location	/workspace/coverage/default/45.clkmgr_frequency_timeout.3304723785
Short name	T351
Test name
Test status
Simulation time	2335658713 ps
CPU time	8.13 seconds
Started	Apr 18 01:33:25 PM PDT 24
Finished	Apr 18 01:33:34 PM PDT 24
Peak memory	200836 kb
Host	smart-d9ae4723-588b-4bce-b8a4-12bdce801ca6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304723785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t imeout.3304723785
Directory	/workspace/45.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/45.clkmgr_idle_intersig_mubi.3412240397
Short name	T439
Test name
Test status
Simulation time	205726332 ps
CPU time	1.38 seconds
Started	Apr 18 01:33:10 PM PDT 24
Finished	Apr 18 01:33:11 PM PDT 24
Peak memory	200584 kb
Host	smart-d8051159-6e3d-410c-a67f-7503385e34cf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412240397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_idle_intersig_mubi.3412240397
Directory	/workspace/45.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.3504279823
Short name	T344
Test name
Test status
Simulation time	52373145 ps
CPU time	0.9 seconds
Started	Apr 18 01:33:30 PM PDT 24
Finished	Apr 18 01:33:32 PM PDT 24
Peak memory	200460 kb
Host	smart-138c305e-2e15-4f47-af98-b582563e3748
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504279823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 45.clkmgr_lc_clk_byp_req_intersig_mubi.3504279823
Directory	/workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.3154837709
Short name	T429
Test name
Test status
Simulation time	24163524 ps
CPU time	0.83 seconds
Started	Apr 18 01:33:16 PM PDT 24
Finished	Apr 18 01:33:17 PM PDT 24
Peak memory	200560 kb
Host	smart-c6fe9d00-5378-4fee-bf93-99a22d9bdf4c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154837709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 45.clkmgr_lc_ctrl_intersig_mubi.3154837709
Directory	/workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_peri.2825492078
Short name	T45
Test name
Test status
Simulation time	57100679 ps
CPU time	0.87 seconds
Started	Apr 18 01:33:13 PM PDT 24
Finished	Apr 18 01:33:15 PM PDT 24
Peak memory	200216 kb
Host	smart-08ba8bfe-5591-4882-8028-d52c63c93eac
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825492078 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.2825492078
Directory	/workspace/45.clkmgr_peri/latest

Test location	/workspace/coverage/default/45.clkmgr_regwen.4277971468
Short name	T498
Test name
Test status
Simulation time	958934109 ps
CPU time	5.48 seconds
Started	Apr 18 01:33:18 PM PDT 24
Finished	Apr 18 01:33:24 PM PDT 24
Peak memory	200720 kb
Host	smart-16d1c9c6-9d8f-4fee-ab77-5f7255e264e9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277971468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.4277971468
Directory	/workspace/45.clkmgr_regwen/latest

Test location	/workspace/coverage/default/45.clkmgr_smoke.1886850440
Short name	T175
Test name
Test status
Simulation time	16221272 ps
CPU time	0.79 seconds
Started	Apr 18 01:33:27 PM PDT 24
Finished	Apr 18 01:33:28 PM PDT 24
Peak memory	200592 kb
Host	smart-b0e610e2-2248-4b62-a302-28e77b0fa8f5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886850440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.1886850440
Directory	/workspace/45.clkmgr_smoke/latest

Test location	/workspace/coverage/default/45.clkmgr_stress_all.3117832670
Short name	T724
Test name
Test status
Simulation time	1229817951 ps
CPU time	8.83 seconds
Started	Apr 18 01:33:21 PM PDT 24
Finished	Apr 18 01:33:30 PM PDT 24
Peak memory	200632 kb
Host	smart-cd27d957-a96c-4d31-a3e5-d2dd865b7838
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117832670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all.3117832670
Directory	/workspace/45.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/45.clkmgr_stress_all_with_rand_reset.3860074233
Short name	T385
Test name
Test status
Simulation time	32738373037 ps
CPU time	325.43 seconds
Started	Apr 18 01:33:12 PM PDT 24
Finished	Apr 18 01:38:38 PM PDT 24
Peak memory	209244 kb
Host	smart-4619ec99-0c6e-4912-92d2-e5e1648c982b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3860074233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.3860074233
Directory	/workspace/45.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.clkmgr_trans.3024208653
Short name	T286
Test name
Test status
Simulation time	35291750 ps
CPU time	0.84 seconds
Started	Apr 18 01:33:11 PM PDT 24
Finished	Apr 18 01:33:12 PM PDT 24
Peak memory	200568 kb
Host	smart-aab99d2c-16bd-4dda-99f0-ca1a2cd2ea8a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024208653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.3024208653
Directory	/workspace/45.clkmgr_trans/latest

Test location	/workspace/coverage/default/46.clkmgr_alert_test.467852562
Short name	T735
Test name
Test status
Simulation time	26527104 ps
CPU time	0.77 seconds
Started	Apr 18 01:33:36 PM PDT 24
Finished	Apr 18 01:33:38 PM PDT 24
Peak memory	200440 kb
Host	smart-09dea34b-1399-41df-82eb-37e05533256f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467852562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkm gr_alert_test.467852562
Directory	/workspace/46.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.672238697
Short name	T341
Test name
Test status
Simulation time	19310567 ps
CPU time	0.8 seconds
Started	Apr 18 01:33:14 PM PDT 24
Finished	Apr 18 01:33:16 PM PDT 24
Peak memory	200568 kb
Host	smart-31fcd335-9a80-41de-90a3-2ab5368501d3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672238697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_handshake_intersig_mubi.672238697
Directory	/workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_clk_status.2260933959
Short name	T782
Test name
Test status
Simulation time	30007875 ps
CPU time	0.77 seconds
Started	Apr 18 01:33:33 PM PDT 24
Finished	Apr 18 01:33:34 PM PDT 24
Peak memory	199472 kb
Host	smart-b943230f-189e-4dde-bdd4-f11fade4f5ca
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260933959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.2260933959
Directory	/workspace/46.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/46.clkmgr_div_intersig_mubi.380538097
Short name	T594
Test name
Test status
Simulation time	20982438 ps
CPU time	0.89 seconds
Started	Apr 18 01:33:28 PM PDT 24
Finished	Apr 18 01:33:30 PM PDT 24
Peak memory	200568 kb
Host	smart-9e63071c-41f3-4cec-aa74-359d6edc3828
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380538097 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.clkmgr_div_intersig_mubi.380538097
Directory	/workspace/46.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_extclk.2920121208
Short name	T84
Test name
Test status
Simulation time	18610890 ps
CPU time	0.76 seconds
Started	Apr 18 01:33:23 PM PDT 24
Finished	Apr 18 01:33:25 PM PDT 24
Peak memory	200508 kb
Host	smart-0233ab28-8197-43a8-81d8-6c91d17bc302
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920121208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.2920121208
Directory	/workspace/46.clkmgr_extclk/latest

Test location	/workspace/coverage/default/46.clkmgr_frequency.2799367644
Short name	T655
Test name
Test status
Simulation time	1897705131 ps
CPU time	8.41 seconds
Started	Apr 18 01:33:13 PM PDT 24
Finished	Apr 18 01:33:22 PM PDT 24
Peak memory	200820 kb
Host	smart-3a5468e7-080b-4c9a-b27b-40d883bcba24
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799367644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.2799367644
Directory	/workspace/46.clkmgr_frequency/latest

Test location	/workspace/coverage/default/46.clkmgr_frequency_timeout.1458189982
Short name	T847
Test name
Test status
Simulation time	1567671015 ps
CPU time	4.93 seconds
Started	Apr 18 01:33:19 PM PDT 24
Finished	Apr 18 01:33:25 PM PDT 24
Peak memory	200596 kb
Host	smart-8d7bf4f1-4c49-4e67-9a73-c3e761c2c402
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458189982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t imeout.1458189982
Directory	/workspace/46.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/46.clkmgr_idle_intersig_mubi.1882707558
Short name	T710
Test name
Test status
Simulation time	36029971 ps
CPU time	0.76 seconds
Started	Apr 18 01:33:25 PM PDT 24
Finished	Apr 18 01:33:26 PM PDT 24
Peak memory	200360 kb
Host	smart-cc915f5f-910d-4257-881a-07251ad667c4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882707558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_idle_intersig_mubi.1882707558
Directory	/workspace/46.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.1217944391
Short name	T494
Test name
Test status
Simulation time	52605003 ps
CPU time	0.89 seconds
Started	Apr 18 01:33:18 PM PDT 24
Finished	Apr 18 01:33:20 PM PDT 24
Peak memory	200580 kb
Host	smart-f86db2ba-8216-4e22-b608-bc91286dc11e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217944391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 46.clkmgr_lc_clk_byp_req_intersig_mubi.1217944391
Directory	/workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.1859135979
Short name	T623
Test name
Test status
Simulation time	15988850 ps
CPU time	0.81 seconds
Started	Apr 18 01:33:15 PM PDT 24
Finished	Apr 18 01:33:17 PM PDT 24
Peak memory	200496 kb
Host	smart-3aecb04d-5a90-4934-b6bf-d301c6035c15
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859135979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 46.clkmgr_lc_ctrl_intersig_mubi.1859135979
Directory	/workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_peri.774623096
Short name	T781
Test name
Test status
Simulation time	41596102 ps
CPU time	0.76 seconds
Started	Apr 18 01:33:35 PM PDT 24
Finished	Apr 18 01:33:37 PM PDT 24
Peak memory	200236 kb
Host	smart-dfcd3372-3e98-4c41-932b-ef4a74b0dad1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774623096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.774623096
Directory	/workspace/46.clkmgr_peri/latest

Test location	/workspace/coverage/default/46.clkmgr_regwen.2722939039
Short name	T369
Test name
Test status
Simulation time	1575164008 ps
CPU time	5.24 seconds
Started	Apr 18 01:33:19 PM PDT 24
Finished	Apr 18 01:33:25 PM PDT 24
Peak memory	200724 kb
Host	smart-3884b92d-5697-43d0-878e-b0db323c6a92
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722939039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.2722939039
Directory	/workspace/46.clkmgr_regwen/latest

Test location	/workspace/coverage/default/46.clkmgr_smoke.3119820427
Short name	T326
Test name
Test status
Simulation time	22208950 ps
CPU time	0.84 seconds
Started	Apr 18 01:33:10 PM PDT 24
Finished	Apr 18 01:33:11 PM PDT 24
Peak memory	200540 kb
Host	smart-c4528702-9128-4325-bbc6-2ac2ec1ff8d3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119820427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.3119820427
Directory	/workspace/46.clkmgr_smoke/latest

Test location	/workspace/coverage/default/46.clkmgr_stress_all.717730911
Short name	T783
Test name
Test status
Simulation time	4506771837 ps
CPU time	18.15 seconds
Started	Apr 18 01:33:27 PM PDT 24
Finished	Apr 18 01:33:46 PM PDT 24
Peak memory	201012 kb
Host	smart-27ca74d3-8ff4-4fb0-86dd-a47036c177cd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717730911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all.717730911
Directory	/workspace/46.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/46.clkmgr_trans.1906839194
Short name	T629
Test name
Test status
Simulation time	26443580 ps
CPU time	0.89 seconds
Started	Apr 18 01:33:14 PM PDT 24
Finished	Apr 18 01:33:16 PM PDT 24
Peak memory	200512 kb
Host	smart-1d11f47b-5f4a-4d99-86d1-566841ac441a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906839194 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.1906839194
Directory	/workspace/46.clkmgr_trans/latest

Test location	/workspace/coverage/default/47.clkmgr_alert_test.1287555002
Short name	T44
Test name
Test status
Simulation time	17218329 ps
CPU time	0.78 seconds
Started	Apr 18 01:33:17 PM PDT 24
Finished	Apr 18 01:33:18 PM PDT 24
Peak memory	200548 kb
Host	smart-5751c3ce-42b1-45b7-a11d-1419cc9a652c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287555002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk mgr_alert_test.1287555002
Directory	/workspace/47.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.344165819
Short name	T88
Test name
Test status
Simulation time	20458274 ps
CPU time	0.81 seconds
Started	Apr 18 01:33:28 PM PDT 24
Finished	Apr 18 01:33:29 PM PDT 24
Peak memory	200528 kb
Host	smart-7e5e32ae-d9e9-4883-92ea-3715c03307c5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344165819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_handshake_intersig_mubi.344165819
Directory	/workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_clk_status.2976566126
Short name	T278
Test name
Test status
Simulation time	14574525 ps
CPU time	0.71 seconds
Started	Apr 18 01:33:15 PM PDT 24
Finished	Apr 18 01:33:16 PM PDT 24
Peak memory	199420 kb
Host	smart-4e7ec2b3-8107-4c1e-aec5-0e8012b2791b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976566126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.2976566126
Directory	/workspace/47.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/47.clkmgr_div_intersig_mubi.818114757
Short name	T337
Test name
Test status
Simulation time	24901696 ps
CPU time	0.91 seconds
Started	Apr 18 01:33:26 PM PDT 24
Finished	Apr 18 01:33:28 PM PDT 24
Peak memory	200496 kb
Host	smart-18c75d50-9e52-41a8-bab1-501e6c38921e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818114757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.clkmgr_div_intersig_mubi.818114757
Directory	/workspace/47.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_extclk.1536121417
Short name	T665
Test name
Test status
Simulation time	85412842 ps
CPU time	1.01 seconds
Started	Apr 18 01:33:35 PM PDT 24
Finished	Apr 18 01:33:37 PM PDT 24
Peak memory	200568 kb
Host	smart-924d0d63-3596-477a-b73c-66e7397fcc2b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536121417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.1536121417
Directory	/workspace/47.clkmgr_extclk/latest

Test location	/workspace/coverage/default/47.clkmgr_frequency.3333666695
Short name	T541
Test name
Test status
Simulation time	1524657570 ps
CPU time	8.39 seconds
Started	Apr 18 01:33:33 PM PDT 24
Finished	Apr 18 01:33:42 PM PDT 24
Peak memory	200520 kb
Host	smart-04823fb3-2ba3-446f-9e5b-c22d71e4ba35
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333666695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.3333666695
Directory	/workspace/47.clkmgr_frequency/latest

Test location	/workspace/coverage/default/47.clkmgr_frequency_timeout.3430689842
Short name	T720
Test name
Test status
Simulation time	1478643594 ps
CPU time	6.35 seconds
Started	Apr 18 01:33:25 PM PDT 24
Finished	Apr 18 01:33:32 PM PDT 24
Peak memory	200684 kb
Host	smart-1eae5221-72d2-46e3-909f-862c88160012
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430689842 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_t imeout.3430689842
Directory	/workspace/47.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/47.clkmgr_idle_intersig_mubi.3106334894
Short name	T115
Test name
Test status
Simulation time	32000896 ps
CPU time	0.91 seconds
Started	Apr 18 01:33:37 PM PDT 24
Finished	Apr 18 01:33:39 PM PDT 24
Peak memory	200568 kb
Host	smart-26d3f949-c11f-42aa-8bc1-ecd65e6a78e8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106334894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_idle_intersig_mubi.3106334894
Directory	/workspace/47.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.2018970837
Short name	T794
Test name
Test status
Simulation time	43382632 ps
CPU time	0.76 seconds
Started	Apr 18 01:33:36 PM PDT 24
Finished	Apr 18 01:33:38 PM PDT 24
Peak memory	200560 kb
Host	smart-024cac9d-ba50-4c4e-b748-1ae742f655d5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018970837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 47.clkmgr_lc_clk_byp_req_intersig_mubi.2018970837
Directory	/workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.1287053643
Short name	T361
Test name
Test status
Simulation time	36672711 ps
CPU time	0.94 seconds
Started	Apr 18 01:33:16 PM PDT 24
Finished	Apr 18 01:33:17 PM PDT 24
Peak memory	200480 kb
Host	smart-e90f59c8-e19d-44af-a402-371235bd3f9b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287053643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 47.clkmgr_lc_ctrl_intersig_mubi.1287053643
Directory	/workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_peri.722707537
Short name	T244
Test name
Test status
Simulation time	37471863 ps
CPU time	0.8 seconds
Started	Apr 18 01:33:28 PM PDT 24
Finished	Apr 18 01:33:30 PM PDT 24
Peak memory	200224 kb
Host	smart-0932b404-7598-43b9-8dfc-f122b1a2f05b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722707537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.722707537
Directory	/workspace/47.clkmgr_peri/latest

Test location	/workspace/coverage/default/47.clkmgr_regwen.3725047456
Short name	T161
Test name
Test status
Simulation time	1480230566 ps
CPU time	5.4 seconds
Started	Apr 18 01:33:28 PM PDT 24
Finished	Apr 18 01:33:34 PM PDT 24
Peak memory	200676 kb
Host	smart-8a118203-71d7-4a55-b890-5da857576ae2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725047456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.3725047456
Directory	/workspace/47.clkmgr_regwen/latest

Test location	/workspace/coverage/default/47.clkmgr_smoke.3172269421
Short name	T827
Test name
Test status
Simulation time	18317314 ps
CPU time	0.79 seconds
Started	Apr 18 01:33:35 PM PDT 24
Finished	Apr 18 01:33:36 PM PDT 24
Peak memory	200572 kb
Host	smart-074326bb-1e6d-444a-a3f6-f8274deecc79
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172269421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.3172269421
Directory	/workspace/47.clkmgr_smoke/latest

Test location	/workspace/coverage/default/47.clkmgr_stress_all.891613439
Short name	T731
Test name
Test status
Simulation time	6001226965 ps
CPU time	31.12 seconds
Started	Apr 18 01:33:16 PM PDT 24
Finished	Apr 18 01:33:48 PM PDT 24
Peak memory	200940 kb
Host	smart-55409ab7-0f8a-4e8d-95b9-c029818e19d2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891613439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all.891613439
Directory	/workspace/47.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/47.clkmgr_stress_all_with_rand_reset.3243321573
Short name	T590
Test name
Test status
Simulation time	11379282376 ps
CPU time	200.4 seconds
Started	Apr 18 01:33:27 PM PDT 24
Finished	Apr 18 01:36:48 PM PDT 24
Peak memory	209276 kb
Host	smart-1de7be27-71f6-4fcf-b1fc-63b9468bec8d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3243321573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.3243321573
Directory	/workspace/47.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.clkmgr_trans.529043394
Short name	T465
Test name
Test status
Simulation time	27181574 ps
CPU time	0.92 seconds
Started	Apr 18 01:33:30 PM PDT 24
Finished	Apr 18 01:33:32 PM PDT 24
Peak memory	200516 kb
Host	smart-e42b8e63-3731-4243-95fe-d04d2266e23f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529043394 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.529043394
Directory	/workspace/47.clkmgr_trans/latest

Test location	/workspace/coverage/default/48.clkmgr_alert_test.3470989319
Short name	T282
Test name
Test status
Simulation time	57406294 ps
CPU time	0.89 seconds
Started	Apr 18 01:33:28 PM PDT 24
Finished	Apr 18 01:33:29 PM PDT 24
Peak memory	200572 kb
Host	smart-684a8273-26d8-4ee8-9627-4e335cf2e489
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470989319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clk mgr_alert_test.3470989319
Directory	/workspace/48.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.945979271
Short name	T92
Test name
Test status
Simulation time	24434631 ps
CPU time	0.85 seconds
Started	Apr 18 01:33:26 PM PDT 24
Finished	Apr 18 01:33:27 PM PDT 24
Peak memory	200552 kb
Host	smart-d7d77ae5-fcb2-4e17-a55a-a05c5819088e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945979271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_handshake_intersig_mubi.945979271
Directory	/workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_clk_status.902908431
Short name	T581
Test name
Test status
Simulation time	40907687 ps
CPU time	0.77 seconds
Started	Apr 18 01:33:29 PM PDT 24
Finished	Apr 18 01:33:30 PM PDT 24
Peak memory	199512 kb
Host	smart-c9741f39-62a5-4083-b34a-44f7d78913a2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902908431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.902908431
Directory	/workspace/48.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/48.clkmgr_div_intersig_mubi.1927635191
Short name	T642
Test name
Test status
Simulation time	70482363 ps
CPU time	0.98 seconds
Started	Apr 18 01:33:14 PM PDT 24
Finished	Apr 18 01:33:16 PM PDT 24
Peak memory	200584 kb
Host	smart-e65d8cf8-0b90-4a29-976a-ed058713d9b8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927635191 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_div_intersig_mubi.1927635191
Directory	/workspace/48.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_extclk.4047224940
Short name	T624
Test name
Test status
Simulation time	63804772 ps
CPU time	0.9 seconds
Started	Apr 18 01:33:17 PM PDT 24
Finished	Apr 18 01:33:19 PM PDT 24
Peak memory	200488 kb
Host	smart-9d49014c-7abf-4f45-97b7-c8dcc5a671ea
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047224940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.4047224940
Directory	/workspace/48.clkmgr_extclk/latest

Test location	/workspace/coverage/default/48.clkmgr_frequency.3428924580
Short name	T300
Test name
Test status
Simulation time	1155521303 ps
CPU time	8.99 seconds
Started	Apr 18 01:33:31 PM PDT 24
Finished	Apr 18 01:33:41 PM PDT 24
Peak memory	200544 kb
Host	smart-f370d725-374f-469c-af49-ce3e47fb11c6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428924580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.3428924580
Directory	/workspace/48.clkmgr_frequency/latest

Test location	/workspace/coverage/default/48.clkmgr_frequency_timeout.1995145322
Short name	T232
Test name
Test status
Simulation time	1095122062 ps
CPU time	7.97 seconds
Started	Apr 18 01:33:29 PM PDT 24
Finished	Apr 18 01:33:38 PM PDT 24
Peak memory	200684 kb
Host	smart-3de90a30-52d5-44dc-9bf6-c6e71e43342b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995145322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t imeout.1995145322
Directory	/workspace/48.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/48.clkmgr_idle_intersig_mubi.1984074607
Short name	T364
Test name
Test status
Simulation time	64589777 ps
CPU time	0.92 seconds
Started	Apr 18 01:33:30 PM PDT 24
Finished	Apr 18 01:33:32 PM PDT 24
Peak memory	200508 kb
Host	smart-2f64f547-4b45-409d-9a9f-0725a2e2514f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984074607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_idle_intersig_mubi.1984074607
Directory	/workspace/48.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.1973555426
Short name	T811
Test name
Test status
Simulation time	54948360 ps
CPU time	0.82 seconds
Started	Apr 18 01:33:15 PM PDT 24
Finished	Apr 18 01:33:17 PM PDT 24
Peak memory	200584 kb
Host	smart-333c302a-0177-4ba6-932d-25ead1a1a419
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973555426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 48.clkmgr_lc_clk_byp_req_intersig_mubi.1973555426
Directory	/workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.1849847760
Short name	T536
Test name
Test status
Simulation time	32970233 ps
CPU time	0.75 seconds
Started	Apr 18 01:33:37 PM PDT 24
Finished	Apr 18 01:33:39 PM PDT 24
Peak memory	200564 kb
Host	smart-44ef03db-fb78-4da7-aa71-6a113a80255d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849847760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 48.clkmgr_lc_ctrl_intersig_mubi.1849847760
Directory	/workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_peri.1334451488
Short name	T561
Test name
Test status
Simulation time	26517183 ps
CPU time	0.83 seconds
Started	Apr 18 01:33:28 PM PDT 24
Finished	Apr 18 01:33:30 PM PDT 24
Peak memory	200284 kb
Host	smart-f58a086d-55ea-4646-a5b4-2d0da270da4d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334451488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.1334451488
Directory	/workspace/48.clkmgr_peri/latest

Test location	/workspace/coverage/default/48.clkmgr_regwen.3099437644
Short name	T567
Test name
Test status
Simulation time	565389277 ps
CPU time	3.53 seconds
Started	Apr 18 01:33:28 PM PDT 24
Finished	Apr 18 01:33:32 PM PDT 24
Peak memory	200704 kb
Host	smart-8c2cf3cb-5107-4224-9e14-24b2870f6466
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099437644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.3099437644
Directory	/workspace/48.clkmgr_regwen/latest

Test location	/workspace/coverage/default/48.clkmgr_smoke.2018044790
Short name	T553
Test name
Test status
Simulation time	121544018 ps
CPU time	1.07 seconds
Started	Apr 18 01:33:14 PM PDT 24
Finished	Apr 18 01:33:16 PM PDT 24
Peak memory	200572 kb
Host	smart-e4e8f32a-841f-4766-b114-35ed8c1dd78c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018044790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.2018044790
Directory	/workspace/48.clkmgr_smoke/latest

Test location	/workspace/coverage/default/48.clkmgr_stress_all.4104621631
Short name	T19
Test name
Test status
Simulation time	2190594643 ps
CPU time	9.26 seconds
Started	Apr 18 01:33:30 PM PDT 24
Finished	Apr 18 01:33:40 PM PDT 24
Peak memory	200992 kb
Host	smart-162eaef1-3b9f-4dee-a358-5d89274d0936
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104621631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all.4104621631
Directory	/workspace/48.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/48.clkmgr_stress_all_with_rand_reset.2513132619
Short name	T10
Test name
Test status
Simulation time	132808009470 ps
CPU time	912.68 seconds
Started	Apr 18 01:33:30 PM PDT 24
Finished	Apr 18 01:48:43 PM PDT 24
Peak memory	209284 kb
Host	smart-fcec00c3-d3d8-48e8-b077-aa344e6ce13e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2513132619 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.2513132619
Directory	/workspace/48.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.clkmgr_trans.4062361154
Short name	T638
Test name
Test status
Simulation time	132181516 ps
CPU time	1.23 seconds
Started	Apr 18 01:33:31 PM PDT 24
Finished	Apr 18 01:33:33 PM PDT 24
Peak memory	200512 kb
Host	smart-0f7e345f-aa7c-45f4-aa82-6529ccae93bb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062361154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.4062361154
Directory	/workspace/48.clkmgr_trans/latest

Test location	/workspace/coverage/default/49.clkmgr_alert_test.3991782021
Short name	T727
Test name
Test status
Simulation time	43689853 ps
CPU time	0.8 seconds
Started	Apr 18 01:33:33 PM PDT 24
Finished	Apr 18 01:33:34 PM PDT 24
Peak memory	200644 kb
Host	smart-10560962-589c-42e4-af5d-8dc635a8d9cd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991782021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clk mgr_alert_test.3991782021
Directory	/workspace/49.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.3785563228
Short name	T639
Test name
Test status
Simulation time	28888781 ps
CPU time	0.91 seconds
Started	Apr 18 01:33:23 PM PDT 24
Finished	Apr 18 01:33:24 PM PDT 24
Peak memory	200584 kb
Host	smart-1ad2d727-259f-41b0-9494-f8faa66cc869
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785563228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_handshake_intersig_mubi.3785563228
Directory	/workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_clk_status.3109098286
Short name	T808
Test name
Test status
Simulation time	47873660 ps
CPU time	0.76 seconds
Started	Apr 18 01:33:34 PM PDT 24
Finished	Apr 18 01:33:36 PM PDT 24
Peak memory	199472 kb
Host	smart-646ec03b-82d6-4fa1-ad44-e40052e37cb4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109098286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.3109098286
Directory	/workspace/49.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/49.clkmgr_div_intersig_mubi.4289472192
Short name	T194
Test name
Test status
Simulation time	55435776 ps
CPU time	0.85 seconds
Started	Apr 18 01:33:22 PM PDT 24
Finished	Apr 18 01:33:24 PM PDT 24
Peak memory	200564 kb
Host	smart-71c2e804-5bea-4640-90b7-7aefe873a411
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289472192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_div_intersig_mubi.4289472192
Directory	/workspace/49.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_extclk.3963181311
Short name	T407
Test name
Test status
Simulation time	21011153 ps
CPU time	0.8 seconds
Started	Apr 18 01:33:18 PM PDT 24
Finished	Apr 18 01:33:19 PM PDT 24
Peak memory	200572 kb
Host	smart-631ad368-8a03-4172-bd09-65bb293bb12a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963181311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.3963181311
Directory	/workspace/49.clkmgr_extclk/latest

Test location	/workspace/coverage/default/49.clkmgr_frequency.2845540121
Short name	T377
Test name
Test status
Simulation time	914675885 ps
CPU time	7.26 seconds
Started	Apr 18 01:33:25 PM PDT 24
Finished	Apr 18 01:33:33 PM PDT 24
Peak memory	200556 kb
Host	smart-86280f3e-19da-43df-938e-f2294d55b9d7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845540121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.2845540121
Directory	/workspace/49.clkmgr_frequency/latest

Test location	/workspace/coverage/default/49.clkmgr_frequency_timeout.800668107
Short name	T813
Test name
Test status
Simulation time	742111323 ps
CPU time	5.62 seconds
Started	Apr 18 01:33:13 PM PDT 24
Finished	Apr 18 01:33:20 PM PDT 24
Peak memory	200700 kb
Host	smart-c8db9765-2d43-452d-8a97-97bd621d7878
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800668107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_ti meout.800668107
Directory	/workspace/49.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/49.clkmgr_idle_intersig_mubi.2135725903
Short name	T198
Test name
Test status
Simulation time	98682188 ps
CPU time	1.07 seconds
Started	Apr 18 01:33:18 PM PDT 24
Finished	Apr 18 01:33:20 PM PDT 24
Peak memory	200572 kb
Host	smart-a481c842-bd22-41be-899d-49e2de202a3e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135725903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_idle_intersig_mubi.2135725903
Directory	/workspace/49.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.879614333
Short name	T526
Test name
Test status
Simulation time	34116032 ps
CPU time	0.89 seconds
Started	Apr 18 01:33:29 PM PDT 24
Finished	Apr 18 01:33:31 PM PDT 24
Peak memory	200580 kb
Host	smart-a5a3048d-732d-4bfe-b386-c75a0667c7f6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879614333 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 49.clkmgr_lc_clk_byp_req_intersig_mubi.879614333
Directory	/workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.2666303727
Short name	T551
Test name
Test status
Simulation time	62991014 ps
CPU time	0.94 seconds
Started	Apr 18 01:33:19 PM PDT 24
Finished	Apr 18 01:33:21 PM PDT 24
Peak memory	200572 kb
Host	smart-babb6a53-1868-4469-9c38-7e86129df2c1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666303727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 49.clkmgr_lc_ctrl_intersig_mubi.2666303727
Directory	/workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_peri.3836235892
Short name	T309
Test name
Test status
Simulation time	22877601 ps
CPU time	0.73 seconds
Started	Apr 18 01:33:13 PM PDT 24
Finished	Apr 18 01:33:14 PM PDT 24
Peak memory	200344 kb
Host	smart-f5a11130-616f-4ddc-807f-572b341bcc31
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836235892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.3836235892
Directory	/workspace/49.clkmgr_peri/latest

Test location	/workspace/coverage/default/49.clkmgr_regwen.3913001558
Short name	T234
Test name
Test status
Simulation time	687610114 ps
CPU time	4.28 seconds
Started	Apr 18 01:33:27 PM PDT 24
Finished	Apr 18 01:33:32 PM PDT 24
Peak memory	200700 kb
Host	smart-cc9b95a3-51a6-4667-9dcb-a793c3ca9f30
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913001558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.3913001558
Directory	/workspace/49.clkmgr_regwen/latest

Test location	/workspace/coverage/default/49.clkmgr_smoke.75465462
Short name	T172
Test name
Test status
Simulation time	19122980 ps
CPU time	0.82 seconds
Started	Apr 18 01:33:16 PM PDT 24
Finished	Apr 18 01:33:17 PM PDT 24
Peak memory	200532 kb
Host	smart-55f4ed38-a855-4dbe-8b59-74af511e7071
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75465462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.75465462
Directory	/workspace/49.clkmgr_smoke/latest

Test location	/workspace/coverage/default/49.clkmgr_stress_all.2045715414
Short name	T12
Test name
Test status
Simulation time	9625150346 ps
CPU time	69.35 seconds
Started	Apr 18 01:33:35 PM PDT 24
Finished	Apr 18 01:34:45 PM PDT 24
Peak memory	201020 kb
Host	smart-9c5e03f7-ed9b-45fd-80d9-2a857593cade
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045715414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all.2045715414
Directory	/workspace/49.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/49.clkmgr_stress_all_with_rand_reset.111510889
Short name	T145
Test name
Test status
Simulation time	128096541782 ps
CPU time	714.02 seconds
Started	Apr 18 01:33:31 PM PDT 24
Finished	Apr 18 01:45:26 PM PDT 24
Peak memory	209196 kb
Host	smart-3e86a939-2a04-478b-a985-9954dadd3b1d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=111510889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.111510889
Directory	/workspace/49.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.clkmgr_trans.418110473
Short name	T459
Test name
Test status
Simulation time	42715327 ps
CPU time	0.99 seconds
Started	Apr 18 01:33:33 PM PDT 24
Finished	Apr 18 01:33:34 PM PDT 24
Peak memory	200480 kb
Host	smart-1b3e1b0a-550a-4ebf-8492-0fb77f34b07a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418110473 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.418110473
Directory	/workspace/49.clkmgr_trans/latest

Test location	/workspace/coverage/default/5.clkmgr_alert_test.1023263131
Short name	T692
Test name
Test status
Simulation time	21428569 ps
CPU time	0.85 seconds
Started	Apr 18 01:31:44 PM PDT 24
Finished	Apr 18 01:31:48 PM PDT 24
Peak memory	200588 kb
Host	smart-ea0e95d1-fcd5-40c4-b825-c219f6af729a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023263131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm gr_alert_test.1023263131
Directory	/workspace/5.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.2665143711
Short name	T687
Test name
Test status
Simulation time	20700778 ps
CPU time	0.83 seconds
Started	Apr 18 01:31:41 PM PDT 24
Finished	Apr 18 01:31:43 PM PDT 24
Peak memory	200484 kb
Host	smart-d70e4e75-e23e-40db-aa4c-9d3edcbfc201
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665143711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_handshake_intersig_mubi.2665143711
Directory	/workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_clk_status.2834148076
Short name	T441
Test name
Test status
Simulation time	12897888 ps
CPU time	0.7 seconds
Started	Apr 18 01:31:41 PM PDT 24
Finished	Apr 18 01:31:43 PM PDT 24
Peak memory	199456 kb
Host	smart-e65a7448-738b-4dcb-8caf-abaa312c897b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834148076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.2834148076
Directory	/workspace/5.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/5.clkmgr_div_intersig_mubi.2725067705
Short name	T454
Test name
Test status
Simulation time	34440819 ps
CPU time	0.79 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:54 PM PDT 24
Peak memory	200572 kb
Host	smart-f31b3779-2f23-4a6b-a142-e34235a1fd3e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725067705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_div_intersig_mubi.2725067705
Directory	/workspace/5.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_extclk.1308815651
Short name	T832
Test name
Test status
Simulation time	16399794 ps
CPU time	0.72 seconds
Started	Apr 18 01:31:41 PM PDT 24
Finished	Apr 18 01:31:44 PM PDT 24
Peak memory	200556 kb
Host	smart-8a9cec20-611d-49ff-85cc-693118f71ba2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308815651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.1308815651
Directory	/workspace/5.clkmgr_extclk/latest

Test location	/workspace/coverage/default/5.clkmgr_frequency.3019321915
Short name	T312
Test name
Test status
Simulation time	1280968532 ps
CPU time	9.92 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:32:03 PM PDT 24
Peak memory	200668 kb
Host	smart-4b82180c-36a6-4e0b-98c3-d5cc41948ac1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019321915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.3019321915
Directory	/workspace/5.clkmgr_frequency/latest

Test location	/workspace/coverage/default/5.clkmgr_frequency_timeout.371307614
Short name	T426
Test name
Test status
Simulation time	735694441 ps
CPU time	5.37 seconds
Started	Apr 18 01:31:44 PM PDT 24
Finished	Apr 18 01:31:52 PM PDT 24
Peak memory	200688 kb
Host	smart-815d087c-0dc0-4abc-9636-9e113ba7e4a5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371307614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_tim eout.371307614
Directory	/workspace/5.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/5.clkmgr_idle_intersig_mubi.3059186545
Short name	T680
Test name
Test status
Simulation time	31665705 ps
CPU time	0.8 seconds
Started	Apr 18 01:31:44 PM PDT 24
Finished	Apr 18 01:31:47 PM PDT 24
Peak memory	200568 kb
Host	smart-f5322b7e-ea09-4851-a2ce-8f8f1a0e847d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059186545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_idle_intersig_mubi.3059186545
Directory	/workspace/5.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.1782901237
Short name	T112
Test name
Test status
Simulation time	34363422 ps
CPU time	0.82 seconds
Started	Apr 18 01:31:42 PM PDT 24
Finished	Apr 18 01:31:45 PM PDT 24
Peak memory	200492 kb
Host	smart-37329964-4547-42e9-a100-0146ebbb86bb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782901237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 5.clkmgr_lc_clk_byp_req_intersig_mubi.1782901237
Directory	/workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.3947800249
Short name	T616
Test name
Test status
Simulation time	33706278 ps
CPU time	0.74 seconds
Started	Apr 18 01:31:45 PM PDT 24
Finished	Apr 18 01:31:49 PM PDT 24
Peak memory	200568 kb
Host	smart-04faca23-c163-401d-9c22-23127e24c820
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947800249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 5.clkmgr_lc_ctrl_intersig_mubi.3947800249
Directory	/workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_peri.869573633
Short name	T370
Test name
Test status
Simulation time	121754951 ps
CPU time	0.97 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:32:01 PM PDT 24
Peak memory	200348 kb
Host	smart-b9e858b8-45e3-4411-b781-55953d56df83
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869573633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.869573633
Directory	/workspace/5.clkmgr_peri/latest

Test location	/workspace/coverage/default/5.clkmgr_regwen.1452349554
Short name	T522
Test name
Test status
Simulation time	857838285 ps
CPU time	4.56 seconds
Started	Apr 18 01:31:50 PM PDT 24
Finished	Apr 18 01:31:59 PM PDT 24
Peak memory	200760 kb
Host	smart-9ff98dff-2a4a-4d57-972a-bc0dcfc7bee2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452349554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.1452349554
Directory	/workspace/5.clkmgr_regwen/latest

Test location	/workspace/coverage/default/5.clkmgr_smoke.2564033911
Short name	T18
Test name
Test status
Simulation time	193912345 ps
CPU time	1.35 seconds
Started	Apr 18 01:31:38 PM PDT 24
Finished	Apr 18 01:31:40 PM PDT 24
Peak memory	200588 kb
Host	smart-891600c9-c7c2-45d2-8952-f6d4ccd4351a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564033911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.2564033911
Directory	/workspace/5.clkmgr_smoke/latest

Test location	/workspace/coverage/default/5.clkmgr_stress_all.1497466461
Short name	T707
Test name
Test status
Simulation time	4204053849 ps
CPU time	28.68 seconds
Started	Apr 18 01:31:50 PM PDT 24
Finished	Apr 18 01:32:23 PM PDT 24
Peak memory	201016 kb
Host	smart-c98ad887-545e-4c46-9d3c-4b076e31a391
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497466461 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all.1497466461
Directory	/workspace/5.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.1916463666
Short name	T144
Test name
Test status
Simulation time	41011547377 ps
CPU time	240.22 seconds
Started	Apr 18 01:31:54 PM PDT 24
Finished	Apr 18 01:35:57 PM PDT 24
Peak memory	217460 kb
Host	smart-95286ad1-780c-47e4-af10-f439f7b67533
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1916463666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.1916463666
Directory	/workspace/5.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.clkmgr_trans.4122327679
Short name	T835
Test name
Test status
Simulation time	15076790 ps
CPU time	0.74 seconds
Started	Apr 18 01:31:43 PM PDT 24
Finished	Apr 18 01:31:47 PM PDT 24
Peak memory	200420 kb
Host	smart-ac250904-3926-4361-9fad-60ef091a8c1a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122327679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.4122327679
Directory	/workspace/5.clkmgr_trans/latest

Test location	/workspace/coverage/default/6.clkmgr_alert_test.1021211723
Short name	T356
Test name
Test status
Simulation time	27685520 ps
CPU time	0.79 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:52 PM PDT 24
Peak memory	200404 kb
Host	smart-0240ef41-e22f-475f-aeed-c763ff7c6768
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021211723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkm gr_alert_test.1021211723
Directory	/workspace/6.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.479219115
Short name	T396
Test name
Test status
Simulation time	44918046 ps
CPU time	0.8 seconds
Started	Apr 18 01:31:45 PM PDT 24
Finished	Apr 18 01:31:48 PM PDT 24
Peak memory	200556 kb
Host	smart-e19e6781-8de0-40d6-b6bd-3ab381ac498a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479219115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_handshake_intersig_mubi.479219115
Directory	/workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_clk_status.795539750
Short name	T34
Test name
Test status
Simulation time	119620575 ps
CPU time	0.9 seconds
Started	Apr 18 01:32:30 PM PDT 24
Finished	Apr 18 01:32:31 PM PDT 24
Peak memory	199488 kb
Host	smart-4894a8b8-29c3-44ba-a416-d08dd94da1de
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795539750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.795539750
Directory	/workspace/6.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/6.clkmgr_div_intersig_mubi.4011851595
Short name	T290
Test name
Test status
Simulation time	84326082 ps
CPU time	1.05 seconds
Started	Apr 18 01:31:46 PM PDT 24
Finished	Apr 18 01:31:51 PM PDT 24
Peak memory	200576 kb
Host	smart-15158a19-6118-4f94-a82f-4bd52823b57c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011851595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_div_intersig_mubi.4011851595
Directory	/workspace/6.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_extclk.3243342650
Short name	T547
Test name
Test status
Simulation time	98383860 ps
CPU time	1.05 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:54 PM PDT 24
Peak memory	200560 kb
Host	smart-1edd7acd-b91e-4485-87e5-1adda3e8068b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243342650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.3243342650
Directory	/workspace/6.clkmgr_extclk/latest

Test location	/workspace/coverage/default/6.clkmgr_frequency.2802971805
Short name	T693
Test name
Test status
Simulation time	1169299612 ps
CPU time	6.49 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:57 PM PDT 24
Peak memory	200652 kb
Host	smart-28bdfcd3-9bd7-4791-96f4-dd390b0c5e28
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802971805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.2802971805
Directory	/workspace/6.clkmgr_frequency/latest

Test location	/workspace/coverage/default/6.clkmgr_frequency_timeout.2486619790
Short name	T297
Test name
Test status
Simulation time	134954991 ps
CPU time	1.65 seconds
Started	Apr 18 01:31:46 PM PDT 24
Finished	Apr 18 01:31:50 PM PDT 24
Peak memory	200540 kb
Host	smart-263e9aa8-6a37-4384-9c36-7912f0e1ad91
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486619790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_ti meout.2486619790
Directory	/workspace/6.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/6.clkmgr_idle_intersig_mubi.1174084613
Short name	T507
Test name
Test status
Simulation time	65082900 ps
CPU time	1.06 seconds
Started	Apr 18 01:31:45 PM PDT 24
Finished	Apr 18 01:31:50 PM PDT 24
Peak memory	200524 kb
Host	smart-d7195da1-c828-4505-a369-7249f2fe4ac4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174084613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_idle_intersig_mubi.1174084613
Directory	/workspace/6.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.3577402852
Short name	T565
Test name
Test status
Simulation time	150519009 ps
CPU time	1.17 seconds
Started	Apr 18 01:31:45 PM PDT 24
Finished	Apr 18 01:31:50 PM PDT 24
Peak memory	200568 kb
Host	smart-13b5fba8-289f-452a-a417-b231bca4062a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577402852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 6.clkmgr_lc_clk_byp_req_intersig_mubi.3577402852
Directory	/workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.2946672572
Short name	T413
Test name
Test status
Simulation time	24578377 ps
CPU time	0.85 seconds
Started	Apr 18 01:31:43 PM PDT 24
Finished	Apr 18 01:31:46 PM PDT 24
Peak memory	200464 kb
Host	smart-11a21daf-67df-45e3-966a-b93ad7906497
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946672572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 6.clkmgr_lc_ctrl_intersig_mubi.2946672572
Directory	/workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_peri.1953908057
Short name	T814
Test name
Test status
Simulation time	76416848 ps
CPU time	0.86 seconds
Started	Apr 18 01:31:46 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200344 kb
Host	smart-d798d46c-e5ef-4334-ad54-412f17d68582
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953908057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.1953908057
Directory	/workspace/6.clkmgr_peri/latest

Test location	/workspace/coverage/default/6.clkmgr_smoke.1387886624
Short name	T622
Test name
Test status
Simulation time	184471676 ps
CPU time	1.23 seconds
Started	Apr 18 01:32:35 PM PDT 24
Finished	Apr 18 01:32:37 PM PDT 24
Peak memory	200576 kb
Host	smart-dd971709-0678-46d7-8c40-70874853b8f5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387886624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.1387886624
Directory	/workspace/6.clkmgr_smoke/latest

Test location	/workspace/coverage/default/6.clkmgr_stress_all.2024681836
Short name	T33
Test name
Test status
Simulation time	9704792199 ps
CPU time	37.64 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:32:30 PM PDT 24
Peak memory	200916 kb
Host	smart-e9d4e656-d397-4c46-bb90-ecf8bd702fe1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024681836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all.2024681836
Directory	/workspace/6.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/6.clkmgr_stress_all_with_rand_reset.3831842114
Short name	T749
Test name
Test status
Simulation time	152641755245 ps
CPU time	746.21 seconds
Started	Apr 18 01:31:41 PM PDT 24
Finished	Apr 18 01:44:10 PM PDT 24
Peak memory	217412 kb
Host	smart-8dcb4083-1042-4193-9ec0-cc4f3f78c81d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3831842114 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.3831842114
Directory	/workspace/6.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.clkmgr_trans.938149265
Short name	T247
Test name
Test status
Simulation time	44348358 ps
CPU time	0.93 seconds
Started	Apr 18 01:31:40 PM PDT 24
Finished	Apr 18 01:31:43 PM PDT 24
Peak memory	200504 kb
Host	smart-9ed02907-6b56-4a93-b996-21601d0ec7e9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938149265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.938149265
Directory	/workspace/6.clkmgr_trans/latest

Test location	/workspace/coverage/default/7.clkmgr_alert_test.1855898646
Short name	T165
Test name
Test status
Simulation time	16078761 ps
CPU time	0.8 seconds
Started	Apr 18 01:31:44 PM PDT 24
Finished	Apr 18 01:31:47 PM PDT 24
Peak memory	200672 kb
Host	smart-a80a71ac-469f-4efa-8047-6ccdd73348c0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855898646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkm gr_alert_test.1855898646
Directory	/workspace/7.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.2239218372
Short name	T607
Test name
Test status
Simulation time	30834037 ps
CPU time	0.95 seconds
Started	Apr 18 01:31:52 PM PDT 24
Finished	Apr 18 01:31:56 PM PDT 24
Peak memory	200588 kb
Host	smart-c9fba4d1-c90f-4ee1-8f7f-c65c6d515604
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239218372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_handshake_intersig_mubi.2239218372
Directory	/workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_clk_status.1540708458
Short name	T350
Test name
Test status
Simulation time	27474947 ps
CPU time	0.75 seconds
Started	Apr 18 01:31:46 PM PDT 24
Finished	Apr 18 01:31:50 PM PDT 24
Peak memory	200260 kb
Host	smart-7b20783a-5264-4371-9f74-ac8491335f1e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540708458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.1540708458
Directory	/workspace/7.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/7.clkmgr_div_intersig_mubi.1460704455
Short name	T761
Test name
Test status
Simulation time	14628044 ps
CPU time	0.74 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200604 kb
Host	smart-3eb2bdd7-8238-4d31-b39f-4274b8d297f1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460704455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_div_intersig_mubi.1460704455
Directory	/workspace/7.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_extclk.4036673534
Short name	T524
Test name
Test status
Simulation time	21084945 ps
CPU time	0.77 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:54 PM PDT 24
Peak memory	200564 kb
Host	smart-b16c3881-9ec1-4556-89aa-afdb5cfc73ba
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036673534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.4036673534
Directory	/workspace/7.clkmgr_extclk/latest

Test location	/workspace/coverage/default/7.clkmgr_frequency.2907463215
Short name	T11
Test name
Test status
Simulation time	1038418758 ps
CPU time	8.17 seconds
Started	Apr 18 01:31:52 PM PDT 24
Finished	Apr 18 01:32:04 PM PDT 24
Peak memory	200596 kb
Host	smart-3d2a22d8-5aba-4990-9220-635b7adcf05b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907463215 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.2907463215
Directory	/workspace/7.clkmgr_frequency/latest

Test location	/workspace/coverage/default/7.clkmgr_frequency_timeout.3908668986
Short name	T729
Test name
Test status
Simulation time	1938666782 ps
CPU time	13.93 seconds
Started	Apr 18 01:31:45 PM PDT 24
Finished	Apr 18 01:32:02 PM PDT 24
Peak memory	200628 kb
Host	smart-eb26c07d-2fe5-4014-a43f-5abc1ad4a566
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908668986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_ti meout.3908668986
Directory	/workspace/7.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/7.clkmgr_idle_intersig_mubi.3019759886
Short name	T301
Test name
Test status
Simulation time	30745445 ps
CPU time	0.95 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200500 kb
Host	smart-6053663c-13cb-4503-a224-d6d8ae5a15b0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019759886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_idle_intersig_mubi.3019759886
Directory	/workspace/7.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.3258651724
Short name	T334
Test name
Test status
Simulation time	80580996 ps
CPU time	0.98 seconds
Started	Apr 18 01:31:46 PM PDT 24
Finished	Apr 18 01:31:50 PM PDT 24
Peak memory	200484 kb
Host	smart-fa79a693-8e32-4808-be93-a5200271384b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258651724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 7.clkmgr_lc_clk_byp_req_intersig_mubi.3258651724
Directory	/workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.3868949482
Short name	T270
Test name
Test status
Simulation time	68534359 ps
CPU time	0.92 seconds
Started	Apr 18 01:31:46 PM PDT 24
Finished	Apr 18 01:31:50 PM PDT 24
Peak memory	200516 kb
Host	smart-29c79eb7-25c3-4747-aa25-7f49d20826be
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868949482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 7.clkmgr_lc_ctrl_intersig_mubi.3868949482
Directory	/workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_peri.3492705520
Short name	T184
Test name
Test status
Simulation time	16521809 ps
CPU time	0.79 seconds
Started	Apr 18 01:31:45 PM PDT 24
Finished	Apr 18 01:31:49 PM PDT 24
Peak memory	200296 kb
Host	smart-f759e50f-a26d-430b-846e-3b43b2767375
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492705520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.3492705520
Directory	/workspace/7.clkmgr_peri/latest

Test location	/workspace/coverage/default/7.clkmgr_regwen.3182534232
Short name	T836
Test name
Test status
Simulation time	793467754 ps
CPU time	4.85 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:56 PM PDT 24
Peak memory	200728 kb
Host	smart-b3151175-139c-44cf-a0eb-853314749201
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182534232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.3182534232
Directory	/workspace/7.clkmgr_regwen/latest

Test location	/workspace/coverage/default/7.clkmgr_smoke.1907766855
Short name	T438
Test name
Test status
Simulation time	19637448 ps
CPU time	0.81 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200588 kb
Host	smart-51f61d2e-2500-4ed7-9526-437073b1b097
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907766855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.1907766855
Directory	/workspace/7.clkmgr_smoke/latest

Test location	/workspace/coverage/default/7.clkmgr_stress_all.1783012502
Short name	T412
Test name
Test status
Simulation time	5061697048 ps
CPU time	36.4 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:32:28 PM PDT 24
Peak memory	200944 kb
Host	smart-c20e189d-6c90-45c7-a75c-db02aad89c2f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783012502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all.1783012502
Directory	/workspace/7.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/7.clkmgr_stress_all_with_rand_reset.1294839830
Short name	T843
Test name
Test status
Simulation time	90062977426 ps
CPU time	767.57 seconds
Started	Apr 18 01:31:42 PM PDT 24
Finished	Apr 18 01:44:31 PM PDT 24
Peak memory	213652 kb
Host	smart-29403a48-c98d-4ae8-a6c1-e92e379ae773
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1294839830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.1294839830
Directory	/workspace/7.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.clkmgr_trans.2242506640
Short name	T795
Test name
Test status
Simulation time	99471250 ps
CPU time	1.1 seconds
Started	Apr 18 01:31:46 PM PDT 24
Finished	Apr 18 01:31:50 PM PDT 24
Peak memory	200568 kb
Host	smart-65d0514c-669d-4570-b3b3-f93936f7e6ee
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242506640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.2242506640
Directory	/workspace/7.clkmgr_trans/latest

Test location	/workspace/coverage/default/8.clkmgr_alert_test.576642287
Short name	T63
Test name
Test status
Simulation time	21701273 ps
CPU time	0.73 seconds
Started	Apr 18 01:31:46 PM PDT 24
Finished	Apr 18 01:31:50 PM PDT 24
Peak memory	200496 kb
Host	smart-651401b1-f286-4027-960d-de882950537b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576642287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmg r_alert_test.576642287
Directory	/workspace/8.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.1839321277
Short name	T803
Test name
Test status
Simulation time	18515249 ps
CPU time	0.78 seconds
Started	Apr 18 01:31:45 PM PDT 24
Finished	Apr 18 01:31:49 PM PDT 24
Peak memory	200516 kb
Host	smart-02c92b13-da4b-4f00-a48d-e30183ce0f7e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839321277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_handshake_intersig_mubi.1839321277
Directory	/workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_clk_status.2412306169
Short name	T776
Test name
Test status
Simulation time	24110078 ps
CPU time	0.69 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:52 PM PDT 24
Peak memory	199516 kb
Host	smart-b6e79eda-36f3-4139-bec0-00325428b250
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412306169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.2412306169
Directory	/workspace/8.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/8.clkmgr_div_intersig_mubi.4123540961
Short name	T339
Test name
Test status
Simulation time	184148359 ps
CPU time	1.28 seconds
Started	Apr 18 01:31:42 PM PDT 24
Finished	Apr 18 01:31:46 PM PDT 24
Peak memory	200496 kb
Host	smart-0966ef9b-aa27-438e-bab9-6d33b4563096
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123540961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_div_intersig_mubi.4123540961
Directory	/workspace/8.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_extclk.1792460029
Short name	T809
Test name
Test status
Simulation time	65288619 ps
CPU time	0.92 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:54 PM PDT 24
Peak memory	200508 kb
Host	smart-bfa98412-54b4-4c9a-9804-1c6208264e6d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792460029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.1792460029
Directory	/workspace/8.clkmgr_extclk/latest

Test location	/workspace/coverage/default/8.clkmgr_frequency.2689308921
Short name	T830
Test name
Test status
Simulation time	2481055293 ps
CPU time	10.55 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:32:04 PM PDT 24
Peak memory	200896 kb
Host	smart-52a5a6c3-5cde-4b84-9f9c-607dcc9b051e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689308921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.2689308921
Directory	/workspace/8.clkmgr_frequency/latest

Test location	/workspace/coverage/default/8.clkmgr_frequency_timeout.908253788
Short name	T295
Test name
Test status
Simulation time	380769082 ps
CPU time	3.22 seconds
Started	Apr 18 01:32:11 PM PDT 24
Finished	Apr 18 01:32:14 PM PDT 24
Peak memory	200708 kb
Host	smart-a719398e-92d1-4fe9-9969-368b5c8f5a22
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908253788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_tim eout.908253788
Directory	/workspace/8.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/8.clkmgr_idle_intersig_mubi.1439692473
Short name	T762
Test name
Test status
Simulation time	93872486 ps
CPU time	1.11 seconds
Started	Apr 18 01:32:25 PM PDT 24
Finished	Apr 18 01:32:26 PM PDT 24
Peak memory	200580 kb
Host	smart-9bf53901-f6b2-43cd-a271-621e0cce56df
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439692473 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_idle_intersig_mubi.1439692473
Directory	/workspace/8.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.2598769148
Short name	T678
Test name
Test status
Simulation time	21915872 ps
CPU time	0.82 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:54 PM PDT 24
Peak memory	200544 kb
Host	smart-635c6448-180f-4fc5-a654-7e23abb9fb42
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598769148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 8.clkmgr_lc_clk_byp_req_intersig_mubi.2598769148
Directory	/workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.2347819735
Short name	T314
Test name
Test status
Simulation time	74188160 ps
CPU time	0.95 seconds
Started	Apr 18 01:31:51 PM PDT 24
Finished	Apr 18 01:31:56 PM PDT 24
Peak memory	200564 kb
Host	smart-bcf5ecbc-4b0e-44d3-a4d4-0b5a5083f5e6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347819735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 8.clkmgr_lc_ctrl_intersig_mubi.2347819735
Directory	/workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_peri.243199505
Short name	T176
Test name
Test status
Simulation time	26594018 ps
CPU time	0.75 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200288 kb
Host	smart-1c2d1b85-b7e2-4d92-9b22-648623d3803c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243199505 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.243199505
Directory	/workspace/8.clkmgr_peri/latest

Test location	/workspace/coverage/default/8.clkmgr_regwen.2359989957
Short name	T610
Test name
Test status
Simulation time	81598157 ps
CPU time	0.99 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:52 PM PDT 24
Peak memory	200452 kb
Host	smart-06edbdb2-4f06-4359-bec7-a676a6087aca
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359989957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.2359989957
Directory	/workspace/8.clkmgr_regwen/latest

Test location	/workspace/coverage/default/8.clkmgr_smoke.2510957052
Short name	T488
Test name
Test status
Simulation time	17958421 ps
CPU time	0.84 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:54 PM PDT 24
Peak memory	200556 kb
Host	smart-8b0f1bc4-ede4-4a7c-892e-927f6ff56138
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510957052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.2510957052
Directory	/workspace/8.clkmgr_smoke/latest

Test location	/workspace/coverage/default/8.clkmgr_stress_all.886935029
Short name	T733
Test name
Test status
Simulation time	2711504658 ps
CPU time	20.79 seconds
Started	Apr 18 01:31:50 PM PDT 24
Finished	Apr 18 01:32:15 PM PDT 24
Peak memory	200848 kb
Host	smart-4f8da96d-037f-431a-b086-138f16f4e62b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886935029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all.886935029
Directory	/workspace/8.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/8.clkmgr_stress_all_with_rand_reset.28456650
Short name	T406
Test name
Test status
Simulation time	20237892866 ps
CPU time	364.78 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:37:58 PM PDT 24
Peak memory	217300 kb
Host	smart-6dd745e5-8307-4858-ab29-6a990223aa8d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=28456650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.28456650
Directory	/workspace/8.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.clkmgr_trans.3336862990
Short name	T471
Test name
Test status
Simulation time	124336728 ps
CPU time	1.22 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:52 PM PDT 24
Peak memory	200468 kb
Host	smart-5d3c0dc0-d52b-47ab-86d5-09ed8ab669d6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336862990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.3336862990
Directory	/workspace/8.clkmgr_trans/latest

Test location	/workspace/coverage/default/9.clkmgr_alert_test.2921566978
Short name	T280
Test name
Test status
Simulation time	48462905 ps
CPU time	0.84 seconds
Started	Apr 18 01:31:50 PM PDT 24
Finished	Apr 18 01:31:55 PM PDT 24
Peak memory	200500 kb
Host	smart-6eb0f64e-f654-497c-9d46-afbf9682789c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921566978 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm gr_alert_test.2921566978
Directory	/workspace/9.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.3955901906
Short name	T340
Test name
Test status
Simulation time	36376943 ps
CPU time	0.76 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200544 kb
Host	smart-721d8045-f617-4e9b-bc86-6fdd956f8da7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955901906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_handshake_intersig_mubi.3955901906
Directory	/workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_clk_status.1743929030
Short name	T329
Test name
Test status
Simulation time	39852185 ps
CPU time	0.74 seconds
Started	Apr 18 01:31:46 PM PDT 24
Finished	Apr 18 01:31:51 PM PDT 24
Peak memory	199460 kb
Host	smart-66b450e7-0b99-459f-8cea-350c931eeabc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743929030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.1743929030
Directory	/workspace/9.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/9.clkmgr_div_intersig_mubi.3741873134
Short name	T677
Test name
Test status
Simulation time	13760057 ps
CPU time	0.72 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:54 PM PDT 24
Peak memory	200484 kb
Host	smart-7d2c5183-3465-4dec-8e28-96ec13b69c00
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741873134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_div_intersig_mubi.3741873134
Directory	/workspace/9.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_extclk.3262376666
Short name	T24
Test name
Test status
Simulation time	83652830 ps
CPU time	1.05 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:52 PM PDT 24
Peak memory	200516 kb
Host	smart-333e87ed-dbe4-43dd-9fd1-7cc8aa07f16b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262376666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.3262376666
Directory	/workspace/9.clkmgr_extclk/latest

Test location	/workspace/coverage/default/9.clkmgr_frequency.531007420
Short name	T20
Test name
Test status
Simulation time	1047200946 ps
CPU time	5.91 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:57 PM PDT 24
Peak memory	200508 kb
Host	smart-d704eb7f-da37-4f09-836a-85f50b095255
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531007420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.531007420
Directory	/workspace/9.clkmgr_frequency/latest

Test location	/workspace/coverage/default/9.clkmgr_frequency_timeout.4197544161
Short name	T427
Test name
Test status
Simulation time	2068542484 ps
CPU time	10.04 seconds
Started	Apr 18 01:31:45 PM PDT 24
Finished	Apr 18 01:31:58 PM PDT 24
Peak memory	200832 kb
Host	smart-ec542dd6-17b8-4f9f-9376-206ebb2a766c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197544161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_ti meout.4197544161
Directory	/workspace/9.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/9.clkmgr_idle_intersig_mubi.723134842
Short name	T701
Test name
Test status
Simulation time	82052159 ps
CPU time	0.93 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:54 PM PDT 24
Peak memory	200572 kb
Host	smart-ad04360e-304a-49c7-862a-d0c2f2e3a549
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723134842 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .clkmgr_idle_intersig_mubi.723134842
Directory	/workspace/9.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.3279209397
Short name	T603
Test name
Test status
Simulation time	26228562 ps
CPU time	0.92 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:31:55 PM PDT 24
Peak memory	200580 kb
Host	smart-49a41965-5a58-415e-a4b7-6a355bd20074
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279209397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 9.clkmgr_lc_clk_byp_req_intersig_mubi.3279209397
Directory	/workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.2595736340
Short name	T360
Test name
Test status
Simulation time	28711780 ps
CPU time	0.9 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:31:52 PM PDT 24
Peak memory	200568 kb
Host	smart-85f2e294-d307-4177-8d5c-07b1e707cf65
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595736340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 9.clkmgr_lc_ctrl_intersig_mubi.2595736340
Directory	/workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_peri.3298411389
Short name	T155
Test name
Test status
Simulation time	18754587 ps
CPU time	0.77 seconds
Started	Apr 18 01:31:48 PM PDT 24
Finished	Apr 18 01:31:53 PM PDT 24
Peak memory	200252 kb
Host	smart-dd8d22d2-22b9-425b-9573-ea6c2f78ddba
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298411389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.3298411389
Directory	/workspace/9.clkmgr_peri/latest

Test location	/workspace/coverage/default/9.clkmgr_regwen.1996005698
Short name	T661
Test name
Test status
Simulation time	1269482812 ps
CPU time	7.04 seconds
Started	Apr 18 01:31:46 PM PDT 24
Finished	Apr 18 01:31:57 PM PDT 24
Peak memory	200656 kb
Host	smart-f7badf66-e29b-4338-a198-d8ebaf12eb5e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996005698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.1996005698
Directory	/workspace/9.clkmgr_regwen/latest

Test location	/workspace/coverage/default/9.clkmgr_smoke.2795567732
Short name	T601
Test name
Test status
Simulation time	22709471 ps
CPU time	0.87 seconds
Started	Apr 18 01:31:50 PM PDT 24
Finished	Apr 18 01:31:55 PM PDT 24
Peak memory	200556 kb
Host	smart-8663240a-adb4-46d8-b517-5218ef00c595
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795567732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.2795567732
Directory	/workspace/9.clkmgr_smoke/latest

Test location	/workspace/coverage/default/9.clkmgr_stress_all.1449832996
Short name	T679
Test name
Test status
Simulation time	2007246176 ps
CPU time	14.79 seconds
Started	Apr 18 01:31:47 PM PDT 24
Finished	Apr 18 01:32:07 PM PDT 24
Peak memory	200920 kb
Host	smart-e7466788-96c2-486c-9cd2-e2c1e66f8083
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449832996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all.1449832996
Directory	/workspace/9.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.1844960458
Short name	T635
Test name
Test status
Simulation time	2061159373 ps
CPU time	15.17 seconds
Started	Apr 18 01:31:49 PM PDT 24
Finished	Apr 18 01:32:08 PM PDT 24
Peak memory	211904 kb
Host	smart-788980a5-5930-4fbc-a9fc-56cfa16b1e71
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1844960458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.1844960458
Directory	/workspace/9.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.clkmgr_trans.1430388252
Short name	T472
Test name
Test status
Simulation time	118277329 ps
CPU time	1.15 seconds
Started	Apr 18 01:31:57 PM PDT 24
Finished	Apr 18 01:32:00 PM PDT 24
Peak memory	200520 kb
Host	smart-71400f39-bfa1-442e-9b94-b6b559fa69b7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430388252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.1430388252
Directory	/workspace/9.clkmgr_trans/latest

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