Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	591344	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3456790

1

T4

465

T6

13

T7

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	995624	1			T4	456		T6	24		T7	16
values[0x0]	1403524	1			T4	230		T6	11		T7	15
values[0x1]	1648986	1			T4	207		T6	7		T7	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	325270	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3722864

1

T4

584

T6

15

T7

19

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15090	1			T4	6		T17	1		T5	3
valid_sources[0x01]	17074	1			T4	13		T5	8		T2	369
valid_sources[0x02]	16342	1			T4	5		T5	2		T2	392
valid_sources[0x03]	15082	1			T5	2		T22	1		T2	382
valid_sources[0x04]	14817	1			T4	11		T5	4		T2	371
valid_sources[0x05]	17174	1			T5	1		T21	1		T22	1
valid_sources[0x06]	15741	1			T4	13		T6	1		T5	2
valid_sources[0x07]	14740	1			T5	3		T2	393		T3	254
valid_sources[0x08]	15465	1			T25	1		T17	1		T5	2
valid_sources[0x09]	17072	1			T17	1		T5	7		T22	1
valid_sources[0x0a]	16646	1			T5	2		T2	389		T84	1
valid_sources[0x0b]	15641	1			T5	2		T2	398		T79	3
valid_sources[0x0c]	15084	1			T4	18		T5	5		T2	383
valid_sources[0x0d]	16888	1			T5	1		T2	419		T30	5
valid_sources[0x0e]	15360	1			T4	7		T22	1		T2	388
valid_sources[0x0f]	16674	1			T2	384		T82	1		T84	1
valid_sources[0x10]	16931	1			T4	7		T5	2		T2	362
valid_sources[0x11]	13806	1			T4	14		T5	4		T20	2
valid_sources[0x12]	14478	1			T4	1		T6	1		T5	3
valid_sources[0x13]	15849	1			T6	1		T5	3		T2	373
valid_sources[0x14]	15065	1			T4	9		T5	3		T2	439
valid_sources[0x15]	14771	1			T2	401		T30	5		T3	819
valid_sources[0x16]	17638	1			T5	2		T2	379		T82	2
valid_sources[0x17]	16725	1			T5	3		T2	397		T78	1
valid_sources[0x18]	15065	1			T4	10		T5	2		T22	1
valid_sources[0x19]	15437	1			T5	2		T2	392		T84	1
valid_sources[0x1a]	15746	1			T4	4		T17	3		T5	1
valid_sources[0x1b]	16901	1			T17	1		T5	3		T2	390
valid_sources[0x1c]	15642	1			T4	11		T5	2		T2	392
valid_sources[0x1d]	15625	1			T5	2		T22	1		T2	396
valid_sources[0x1e]	16598	1			T4	28		T6	1		T5	5
valid_sources[0x1f]	14690	1			T4	16		T5	2		T2	368
valid_sources[0x20]	15320	1			T6	1		T5	3		T2	397
valid_sources[0x21]	16001	1			T6	1		T5	3		T22	1
valid_sources[0x22]	16190	1			T4	11		T5	6		T22	1
valid_sources[0x23]	17301	1			T17	1		T5	4		T2	357
valid_sources[0x24]	16323	1			T5	3		T21	1		T2	387
valid_sources[0x25]	14780	1			T4	2		T5	4		T22	1
valid_sources[0x26]	14596	1			T5	2		T2	393		T84	2
valid_sources[0x27]	15676	1			T4	11		T17	1		T5	3
valid_sources[0x28]	15119	1			T4	4		T5	2		T21	1
valid_sources[0x29]	15994	1			T4	3		T5	2		T2	388
valid_sources[0x2a]	15056	1			T4	10		T17	1		T5	3
valid_sources[0x2b]	16917	1			T17	1		T5	3		T22	1
valid_sources[0x2c]	15519	1			T6	1		T17	1		T5	4
valid_sources[0x2d]	14090	1			T17	1		T5	1		T2	385
valid_sources[0x2e]	17275	1			T5	2		T21	2		T2	403
valid_sources[0x2f]	14104	1			T5	2		T2	386		T84	5
valid_sources[0x30]	15739	1			T5	2		T22	1		T2	432
valid_sources[0x31]	15260	1			T4	1		T5	4		T2	390
valid_sources[0x32]	14498	1			T4	6		T5	2		T2	364
valid_sources[0x33]	15553	1			T5	1		T2	379		T33	2
valid_sources[0x34]	15633	1			T6	1		T5	4		T2	408
valid_sources[0x35]	16160	1			T5	1		T2	416		T193	1
valid_sources[0x36]	15976	1			T17	1		T5	6		T2	405
valid_sources[0x37]	14970	1			T4	5		T5	1		T21	1
valid_sources[0x38]	16036	1			T4	9		T5	1		T2	416
valid_sources[0x39]	15375	1			T6	1		T17	1		T5	3
valid_sources[0x3a]	15622	1			T4	15		T5	4		T2	384
valid_sources[0x3b]	14958	1			T4	2		T5	1		T2	411
valid_sources[0x3c]	16263	1			T5	2		T21	1		T22	1
valid_sources[0x3d]	15571	1			T4	8		T5	3		T2	385
valid_sources[0x3e]	16113	1			T17	1		T5	2		T22	1
valid_sources[0x3f]	15934	1			T4	6		T5	3		T22	1
valid_sources[0x40]	16509	1			T17	2		T5	3		T21	3
valid_sources[0x41]	15364	1			T5	3		T21	1		T2	380
valid_sources[0x42]	17081	1			T5	8		T2	389		T79	1
valid_sources[0x43]	16568	1			T5	3		T2	392		T79	2
valid_sources[0x44]	16160	1			T4	22		T5	1		T2	374
valid_sources[0x45]	18427	1			T5	1		T2	393		T82	3
valid_sources[0x46]	15774	1			T5	4		T21	1		T2	399
valid_sources[0x47]	15849	1			T5	2		T2	357		T79	1
valid_sources[0x48]	17360	1			T4	7		T5	5		T21	2
valid_sources[0x49]	15990	1			T6	1		T5	1		T21	1
valid_sources[0x4a]	16855	1			T5	2		T2	387		T84	1
valid_sources[0x4b]	14974	1			T4	1		T5	2		T21	1
valid_sources[0x4c]	15232	1			T5	3		T22	1		T2	366
valid_sources[0x4d]	17532	1			T1	2013		T17	1		T5	1
valid_sources[0x4e]	16402	1			T5	6		T2	410		T3	1616
valid_sources[0x4f]	15675	1			T6	1		T5	3		T21	1
valid_sources[0x50]	15871	1			T4	9		T5	3		T21	2
valid_sources[0x51]	14932	1			T5	4		T2	389		T78	2
valid_sources[0x52]	15323	1			T5	4		T21	1		T2	393
valid_sources[0x53]	14973	1			T6	1		T5	7		T2	383
valid_sources[0x54]	15318	1			T4	4		T6	1		T17	1
valid_sources[0x55]	15951	1			T6	1		T5	3		T2	407
valid_sources[0x56]	15660	1			T5	6		T2	378		T79	1
valid_sources[0x57]	14902	1			T4	7		T5	3		T21	1
valid_sources[0x58]	15266	1			T5	4		T21	1		T2	395
valid_sources[0x59]	17613	1			T4	2		T2	409		T3	1289
valid_sources[0x5a]	14773	1			T4	13		T17	1		T5	4
valid_sources[0x5b]	16131	1			T4	11		T5	4		T2	371
valid_sources[0x5c]	17780	1			T4	3		T17	2		T5	6
valid_sources[0x5d]	15949	1			T4	3		T5	2		T22	1
valid_sources[0x5e]	16019	1			T5	2		T22	1		T2	403
valid_sources[0x5f]	16968	1			T5	4		T2	413		T30	6
valid_sources[0x60]	14425	1			T6	2		T5	1		T2	354
valid_sources[0x61]	15930	1			T22	1		T2	437		T84	2
valid_sources[0x62]	17782	1			T4	8		T5	4		T22	2
valid_sources[0x63]	17300	1			T17	1		T5	3		T22	1
valid_sources[0x64]	16144	1			T4	14		T5	4		T2	426
valid_sources[0x65]	15208	1			T5	7		T21	1		T22	1
valid_sources[0x66]	16485	1			T4	3		T17	1		T5	9
valid_sources[0x67]	15390	1			T5	2		T21	3		T2	369
valid_sources[0x68]	15428	1			T17	1		T5	2		T21	1
valid_sources[0x69]	17328	1			T4	9		T5	2		T2	390
valid_sources[0x6a]	14516	1			T4	3		T5	2		T20	8
valid_sources[0x6b]	16324	1			T5	3		T21	1		T2	417
valid_sources[0x6c]	15462	1			T4	14		T5	5		T2	411
valid_sources[0x6d]	15600	1			T6	1		T5	1		T2	375
valid_sources[0x6e]	15111	1			T5	1		T22	1		T2	392
valid_sources[0x6f]	17033	1			T6	1		T5	5		T22	1
valid_sources[0x70]	15123	1			T5	3		T21	1		T2	377
valid_sources[0x71]	14215	1			T17	1		T5	4		T2	361
valid_sources[0x72]	16425	1			T4	8		T5	5		T22	2
valid_sources[0x73]	14505	1			T4	2		T17	1		T5	4
valid_sources[0x74]	16584	1			T5	4		T21	1		T2	378
valid_sources[0x75]	15941	1			T4	4		T5	5		T21	1
valid_sources[0x76]	14324	1			T4	5		T5	3		T21	1
valid_sources[0x77]	16190	1			T5	4		T2	421		T78	1
valid_sources[0x78]	17757	1			T4	2		T5	4		T2	412
valid_sources[0x79]	16780	1			T17	1		T5	7		T22	1
valid_sources[0x7a]	15394	1			T6	1		T5	1		T2	390
valid_sources[0x7b]	16332	1			T4	8		T2	377		T84	2
valid_sources[0x7c]	16106	1			T5	4		T2	406		T78	1
valid_sources[0x7d]	15111	1			T5	5		T2	446		T79	3
valid_sources[0x7e]	17538	1			T5	4		T2	402		T82	1
valid_sources[0x7f]	16083	1			T4	5		T5	5		T22	1
valid_sources[0x80]	16003	1			T4	7		T5	4		T21	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

872925

1

T4

241

T6

11

T7

6

values[0x0]

all_enables

biggest_size

1314091

1

T4

155

T6

2

T7

8

values[0x1]

all_enables

biggest_size

1269774

1

T4

69

T7

1

T24

2