Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	756978200	71182	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756978200	71182	0	0
T1	861350	226	0	0
T2	1902065	1881	0	0
T3	0	2069	0	0
T5	161915	0	0	0
T10	0	2557	0	0
T11	0	555	0	0
T12	0	735	0	0
T13	0	570	0	0
T14	0	130	0	0
T15	0	119	0	0
T16	0	888	0	0
T17	7970	0	0	0
T18	7565	0	0	0
T19	17600	0	0	0
T20	6925	0	0	0
T21	13345	0	0	0
T22	8895	0	0	0
T23	7530	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151395640	10509	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151395640	10509	0	0
T1	172270	37	0	0
T2	380413	276	0	0
T3	0	274	0	0
T5	32383	0	0	0
T10	0	378	0	0
T11	0	71	0	0
T12	0	99	0	0
T13	0	73	0	0
T14	0	23	0	0
T15	0	15	0	0
T16	0	130	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T20	1385	0	0	0
T21	2669	0	0	0
T22	1779	0	0	0
T23	1506	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151395640	14286	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151395640	14286	0	0
T1	172270	46	0	0
T2	380413	376	0	0
T3	0	416	0	0
T5	32383	0	0	0
T10	0	516	0	0
T11	0	110	0	0
T12	0	146	0	0
T13	0	116	0	0
T14	0	25	0	0
T15	0	24	0	0
T16	0	182	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T20	1385	0	0	0
T21	2669	0	0	0
T22	1779	0	0	0
T23	1506	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151395640	21741	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151395640	21741	0	0
T1	172270	60	0	0
T2	380413	582	0	0
T3	0	692	0	0
T5	32383	0	0	0
T10	0	837	0	0
T11	0	183	0	0
T12	0	245	0	0
T13	0	193	0	0
T14	0	32	0	0
T15	0	39	0	0
T16	0	292	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T20	1385	0	0	0
T21	2669	0	0	0
T22	1779	0	0	0
T23	1506	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151395640	10324	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151395640	10324	0	0
T1	172270	37	0	0
T2	380413	271	0	0
T3	0	267	0	0
T5	32383	0	0	0
T10	0	323	0	0
T11	0	79	0	0
T12	0	97	0	0
T13	0	72	0	0
T14	0	23	0	0
T15	0	17	0	0
T16	0	109	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T20	1385	0	0	0
T21	2669	0	0	0
T22	1779	0	0	0
T23	1506	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151395640	14322	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151395640	14322	0	0
T1	172270	46	0	0
T2	380413	376	0	0
T3	0	420	0	0
T5	32383	0	0	0
T10	0	503	0	0
T11	0	112	0	0
T12	0	148	0	0
T13	0	116	0	0
T14	0	27	0	0
T15	0	24	0	0
T16	0	175	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T20	1385	0	0	0
T21	2669	0	0	0
T22	1779	0	0	0
T23	1506	0	0	0