Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	151395640	148591501	0	0
AllClkBypReqTrue_A	151395640	131873	0	0
IoClkBypReqFalse_A	151395640	148510811	0	2415
IoClkBypReqTrue_A	151395640	207885	0	0
LcClkBypAckFalse_A	151395640	148602339	0	0
LcClkBypAckTrue_A	151395640	121035	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151395640	148591501	0	0
T1	172270	171707	0	0
T4	30276	3663	0	0
T5	32383	8819	0	0
T6	1705	1569	0	0
T7	2008	1783	0	0
T17	1594	1348	0	0
T18	1513	1474	0	0
T19	3520	3395	0	0
T24	2151	2069	0	0
T25	1187	1161	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151395640	131873	0	0
T1	172270	364	0	0
T2	0	2998	0	0
T3	0	3020	0	0
T5	32383	0	0	0
T7	2008	65	0	0
T17	1594	222	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T20	1385	139	0	0
T21	2669	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T81	0	30	0	0
T120	0	136	0	0
T121	0	33	0	0
T122	0	35	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151395640	148510811	0	2415
T1	172270	171516	0	3
T4	30276	3623	0	3
T5	32383	8785	0	3
T6	1705	1567	0	3
T7	2008	1801	0	3
T17	1594	1261	0	3
T18	1513	1269	0	3
T19	3520	3393	0	3
T24	2151	2067	0	3
T25	1187	1159	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151395640	207885	0	0
T1	172270	543	0	0
T2	0	4512	0	0
T3	0	4259	0	0
T5	32383	0	0	0
T7	2008	45	0	0
T17	1594	307	0	0
T18	1513	203	0	0
T19	3520	0	0	0
T20	1385	194	0	0
T21	2669	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T81	0	358	0	0
T120	0	245	0	0
T123	0	355	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151395640	148602339	0	0
T1	172270	171668	0	0
T4	30276	3663	0	0
T5	32383	8819	0	0
T6	1705	1569	0	0
T7	2008	1807	0	0
T17	1594	1359	0	0
T18	1513	1453	0	0
T19	3520	3395	0	0
T24	2151	2069	0	0
T25	1187	1161	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151395640	121035	0	0
T1	172270	403	0	0
T2	0	2634	0	0
T3	0	2563	0	0
T5	32383	0	0	0
T7	2008	41	0	0
T17	1594	211	0	0
T18	1513	21	0	0
T19	3520	0	0	0
T20	1385	117	0	0
T21	2669	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T81	0	140	0	0
T120	0	130	0	0
T123	0	142	0	0