Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1748069740	15039	0	0
TransStop_A	1748069740	7873	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1748069740	15039	0	0
T1	3933464	42	0	0
T2	0	493	0	0
T5	539744	0	0	0
T6	13648	15	0	0
T7	8548	0	0	0
T17	49056	0	0	0
T18	26312	0	0	0
T19	14368	28	0	0
T20	42604	0	0	0
T21	0	23	0	0
T22	0	4	0	0
T24	17920	15	0	0
T25	21596	0	0	0
T79	0	4	0	0
T82	0	4	0	0
T83	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1748069740	7873	0	0
T1	3933464	26	0	0
T2	0	268	0	0
T5	539744	0	0	0
T6	13648	11	0	0
T7	8548	0	0	0
T17	49056	0	0	0
T18	26312	0	0	0
T19	14368	11	0	0
T20	42604	0	0	0
T21	0	11	0	0
T22	0	4	0	0
T24	17920	5	0	0
T25	21596	0	0	0
T79	0	4	0	0
T82	0	4	0	0
T83	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	437017435	3714	0	0
TransStop_A	437017435	1974	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437017435	3714	0	0
T1	983366	10	0	0
T2	0	126	0	0
T5	134936	0	0	0
T6	3412	3	0	0
T7	2137	0	0	0
T17	12264	0	0	0
T18	6578	0	0	0
T19	3592	9	0	0
T20	10651	0	0	0
T21	0	6	0	0
T22	0	1	0	0
T24	4480	6	0	0
T25	5399	0	0	0
T79	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437017435	1974	0	0
T1	983366	6	0	0
T2	0	69	0	0
T5	134936	0	0	0
T6	3412	2	0	0
T7	2137	0	0	0
T17	12264	0	0	0
T18	6578	0	0	0
T19	3592	5	0	0
T20	10651	0	0	0
T21	0	3	0	0
T22	0	1	0	0
T24	4480	2	0	0
T25	5399	0	0	0
T79	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	437017435	3819	0	0
TransStop_A	437017435	1961	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437017435	3819	0	0
T1	983366	11	0	0
T2	0	119	0	0
T5	134936	0	0	0
T6	3412	5	0	0
T7	2137	0	0	0
T17	12264	0	0	0
T18	6578	0	0	0
T19	3592	6	0	0
T20	10651	0	0	0
T21	0	8	0	0
T22	0	1	0	0
T24	4480	1	0	0
T25	5399	0	0	0
T79	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437017435	1961	0	0
T1	983366	7	0	0
T2	0	66	0	0
T5	134936	0	0	0
T6	3412	3	0	0
T7	2137	0	0	0
T17	12264	0	0	0
T18	6578	0	0	0
T19	3592	2	0	0
T20	10651	0	0	0
T21	0	3	0	0
T22	0	1	0	0
T24	4480	1	0	0
T25	5399	0	0	0
T79	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	437017435	3733	0	0
TransStop_A	437017435	1947	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437017435	3733	0	0
T1	983366	11	0	0
T2	0	114	0	0
T5	134936	0	0	0
T6	3412	4	0	0
T7	2137	0	0	0
T17	12264	0	0	0
T18	6578	0	0	0
T19	3592	6	0	0
T20	10651	0	0	0
T21	0	6	0	0
T22	0	1	0	0
T24	4480	4	0	0
T25	5399	0	0	0
T79	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437017435	1947	0	0
T1	983366	7	0	0
T2	0	60	0	0
T5	134936	0	0	0
T6	3412	3	0	0
T7	2137	0	0	0
T17	12264	0	0	0
T18	6578	0	0	0
T19	3592	1	0	0
T20	10651	0	0	0
T21	0	4	0	0
T22	0	1	0	0
T24	4480	1	0	0
T25	5399	0	0	0
T79	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	437017435	3773	0	0
TransStop_A	437017435	1991	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437017435	3773	0	0
T1	983366	10	0	0
T2	0	134	0	0
T5	134936	0	0	0
T6	3412	3	0	0
T7	2137	0	0	0
T17	12264	0	0	0
T18	6578	0	0	0
T19	3592	7	0	0
T20	10651	0	0	0
T21	0	3	0	0
T22	0	1	0	0
T24	4480	4	0	0
T25	5399	0	0	0
T79	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437017435	1991	0	0
T1	983366	6	0	0
T2	0	73	0	0
T5	134936	0	0	0
T6	3412	3	0	0
T7	2137	0	0	0
T17	12264	0	0	0
T18	6578	0	0	0
T19	3592	3	0	0
T20	10651	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T24	4480	1	0	0
T25	5399	0	0	0
T79	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0