Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	151395640	20525662	0	56

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151395640	20525662	0	56
T1	172270	12617	0	0
T2	380413	185920	0	0
T3	0	113201	0	0
T5	32383	0	0	0
T10	0	465194	0	0
T11	0	61055	0	1
T12	0	79591	0	0
T13	0	73194	0	0
T14	0	5815	0	1
T15	0	12628	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T20	1385	0	0	0
T21	2669	0	0	0
T22	1779	0	0	0
T23	1506	0	0	0
T26	0	750	0	1
T124	0	0	0	1
T125	0	0	0	1
T126	0	0	0	1
T127	0	0	0	1
T128	0	0	0	1
T129	0	0	0	1
T130	0	0	0	1