Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	152251160	5042875	0	0
clk_enables_rd_A	152251160	43456	0	0
clk_hints_rd_A	152251160	38241	0	0
extclk_ctrl_rd_A	152251160	47803	0	0
extclk_ctrl_regwen_rd_A	152251160	37025	0	0
jitter_enable_rd_A	152251160	53300	0	0
jitter_regwen_rd_A	152251160	41622	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	5042875	0	0
T2	380413	128999	0	0
T3	0	214706	0	0
T10	0	78474	0	0
T12	0	49465	0	0
T16	0	26820	0	0
T23	1506	0	0	0
T33	1433	0	0	0
T73	0	150291	0	0
T74	0	58392	0	0
T75	0	264436	0	0
T76	0	63652	0	0
T77	0	254129	0	0
T78	1615	0	0	0
T79	1640	0	0	0
T80	1526	0	0	0
T81	1871	0	0	0
T82	1769	0	0	0
T83	1050	0	0	0
T84	3268	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	43456	0	0
T16	0	1064	0	0
T27	0	9	0	0
T28	95567	0	0	0
T29	125804	0	0	0
T30	112921	0	0	0
T36	1025	0	0	0
T82	1769	2	0	0
T83	1050	0	0	0
T84	3268	0	0	0
T147	0	2	0	0
T148	0	2	0	0
T149	0	4	0	0
T150	0	1017	0	0
T151	0	9	0	0
T152	0	10	0	0
T153	0	9	0	0
T154	1230	0	0	0
T155	1511	0	0	0
T156	1467	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	38241	0	0
T16	0	922	0	0
T27	0	13	0	0
T28	95567	0	0	0
T29	125804	0	0	0
T30	112921	0	0	0
T36	1025	0	0	0
T82	1769	7	0	0
T83	1050	0	0	0
T84	3268	0	0	0
T147	0	5	0	0
T150	0	846	0	0
T151	0	15	0	0
T152	0	10	0	0
T153	0	8	0	0
T154	1230	0	0	0
T155	1511	0	0	0
T156	1467	0	0	0
T157	0	5	0	0
T158	0	4	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	47803	0	0
T2	380413	0	0	0
T5	32383	118	0	0
T18	1513	25	0	0
T19	3520	0	0	0
T20	1385	0	0	0
T21	2669	0	0	0
T22	1779	0	0	0
T23	1506	0	0	0
T78	1615	0	0	0
T79	1640	0	0	0
T88	0	22	0	0
T98	0	61	0	0
T159	0	17	0	0
T160	0	15	0	0
T161	0	26	0	0
T162	0	35	0	0
T163	0	47	0	0
T164	0	9	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	37025	0	0
T2	380413	0	0	0
T5	32383	56	0	0
T16	0	941	0	0
T19	3520	0	0	0
T20	1385	0	0	0
T21	2669	0	0	0
T22	1779	0	0	0
T23	1506	0	0	0
T33	1433	0	0	0
T78	1615	0	0	0
T79	1640	0	0	0
T150	0	775	0	0
T165	0	5	0	0
T166	0	19	0	0
T167	0	3	0	0
T168	0	20	0	0
T169	0	75	0	0
T170	0	50	0	0
T171	0	4785	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	53300	0	0
T16	0	1014	0	0
T27	0	221	0	0
T28	95567	0	0	0
T29	125804	0	0	0
T30	112921	0	0	0
T36	1025	0	0	0
T82	1769	147	0	0
T83	1050	0	0	0
T84	3268	0	0	0
T147	0	115	0	0
T148	0	103	0	0
T149	0	105	0	0
T150	0	1152	0	0
T154	1230	0	0	0
T155	1511	0	0	0
T156	1467	0	0	0
T157	0	31	0	0
T158	0	70	0	0
T172	0	81	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	41622	0	0
T16	938770	1238	0	0
T27	714158	0	0	0
T35	0	1922	0	0
T150	0	985	0	0
T165	12282	0	0	0
T171	0	5753	0	0
T173	0	1663	0	0
T174	0	2563	0	0
T175	0	1586	0	0
T176	0	1870	0	0
T177	0	1077	0	0
T178	0	605	0	0
T179	1579	0	0	0
T180	1545	0	0	0
T181	1033	0	0	0
T182	1223	0	0	0
T183	1085	0	0	0
T184	78192	0	0	0
T185	1316	0	0	0