Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	45072	0	0
CgEnOn_A	2147483647	35726	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	45072	0	0
T1	2445739	57	0	0
T3	1361106	0	0	0
T4	180811	60	0	0
T5	321273	51	0	0
T6	9040	6	0	0
T7	5740	3	0	0
T10	0	5	0	0
T17	34776	3	0	0
T18	17638	3	0	0
T19	9585	12	0	0
T20	10650	0	0	0
T21	0	6	0	0
T24	11986	9	0	0
T25	14417	3	0	0
T29	340975	0	0	0
T30	184467	0	0	0
T36	8217	15	0	0
T37	0	5	0	0
T38	0	25	0	0
T75	0	5	0	0
T120	4694	0	0	0
T123	5781	0	0	0
T155	6250	0	0	0
T156	6539	0	0	0
T157	4696	0	0	0
T186	0	15	0	0
T187	0	15	0	0
T188	0	20	0	0
T189	0	10	0	0
T190	0	20	0	0
T193	5141	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35726	0	0
T1	2445739	39	0	0
T2	1261536	551	0	0
T3	1361106	0	0	0
T5	321273	0	0	0
T6	3411	3	0	0
T10	0	4	0	0
T17	34776	0	0	0
T18	17638	0	0	0
T19	9585	0	0	0
T20	29138	0	0	0
T21	4881	0	0	0
T22	5911	4	0	0
T23	2473	0	0	0
T29	340975	0	0	0
T30	184467	0	0	0
T36	8217	24	0	0
T37	0	5	0	0
T38	0	25	0	0
T75	0	5	0	0
T78	0	43	0	0
T79	0	4	0	0
T80	0	38	0	0
T82	0	4	0	0
T83	0	4	0	0
T120	4694	0	0	0
T123	5781	0	0	0
T155	6250	0	0	0
T156	6539	0	0	0
T157	4696	3	0	0
T186	0	15	0	0
T187	0	15	0	0
T188	0	20	0	0
T189	0	10	0	0
T190	0	20	0	0
T191	0	2	0	0
T193	5141	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	205447380	160	0	0
CgEnOn_A	205447380	160	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205447380	160	0	0
T3	302105	0	0	0
T10	0	1	0	0
T29	75745	0	0	0
T30	40984	0	0	0
T36	1796	3	0	0
T37	0	1	0	0
T38	0	5	0	0
T75	0	1	0	0
T120	1070	0	0	0
T123	1312	0	0	0
T155	1362	0	0	0
T156	1441	0	0	0
T157	1032	0	0	0
T186	0	3	0	0
T187	0	3	0	0
T188	0	4	0	0
T189	0	2	0	0
T190	0	4	0	0
T193	1119	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205447380	160	0	0
T3	302105	0	0	0
T10	0	1	0	0
T29	75745	0	0	0
T30	40984	0	0	0
T36	1796	3	0	0
T37	0	1	0	0
T38	0	5	0	0
T75	0	1	0	0
T120	1070	0	0	0
T123	1312	0	0	0
T155	1362	0	0	0
T156	1441	0	0	0
T157	1032	0	0	0
T186	0	3	0	0
T187	0	3	0	0
T188	0	4	0	0
T189	0	2	0	0
T190	0	4	0	0
T193	1119	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	102723095	160	0	0
CgEnOn_A	102723095	160	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102723095	160	0	0
T3	151051	0	0	0
T10	0	1	0	0
T29	37873	0	0	0
T30	20492	0	0	0
T36	898	3	0	0
T37	0	1	0	0
T38	0	5	0	0
T75	0	1	0	0
T120	533	0	0	0
T123	655	0	0	0
T155	681	0	0	0
T156	721	0	0	0
T157	516	0	0	0
T186	0	3	0	0
T187	0	3	0	0
T188	0	4	0	0
T189	0	2	0	0
T190	0	4	0	0
T193	559	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102723095	160	0	0
T3	151051	0	0	0
T10	0	1	0	0
T29	37873	0	0	0
T30	20492	0	0	0
T36	898	3	0	0
T37	0	1	0	0
T38	0	5	0	0
T75	0	1	0	0
T120	533	0	0	0
T123	655	0	0	0
T155	681	0	0	0
T156	721	0	0	0
T157	516	0	0	0
T186	0	3	0	0
T187	0	3	0	0
T188	0	4	0	0
T189	0	2	0	0
T190	0	4	0	0
T193	559	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	409801198	160	0	0
CgEnOn_A	409801198	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409801198	160	0	0
T3	605848	0	0	0
T10	0	1	0	0
T29	151611	0	0	0
T30	82007	0	0	0
T36	3727	3	0	0
T37	0	1	0	0
T38	0	5	0	0
T75	0	1	0	0
T120	2025	0	0	0
T123	2504	0	0	0
T155	2845	0	0	0
T156	2935	0	0	0
T157	2116	0	0	0
T186	0	3	0	0
T187	0	3	0	0
T188	0	4	0	0
T189	0	2	0	0
T190	0	4	0	0
T193	2345	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409801198	154	0	0
T3	605848	0	0	0
T29	151611	0	0	0
T30	82007	0	0	0
T36	3727	3	0	0
T37	0	1	0	0
T38	0	5	0	0
T75	0	1	0	0
T120	2025	0	0	0
T123	2504	0	0	0
T155	2845	0	0	0
T156	2935	0	0	0
T157	2116	0	0	0
T186	0	3	0	0
T187	0	3	0	0
T188	0	4	0	0
T189	0	2	0	0
T190	0	4	0	0
T191	0	2	0	0
T193	2345	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	437016983	154	0	0
CgEnOn_A	437016983	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437016983	154	0	0
T3	652712	0	0	0
T29	235935	0	0	0
T30	121424	0	0	0
T36	3626	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T120	2108	0	0	0
T123	2609	0	0	0
T155	2964	0	0	0
T156	3056	0	0	0
T157	2204	0	0	0
T186	0	2	0	0
T187	0	4	0	0
T188	0	4	0	0
T189	0	3	0	0
T190	0	3	0	0
T191	0	2	0	0
T192	0	6	0	0
T193	2442	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437016983	154	0	0
T3	652712	0	0	0
T29	235935	0	0	0
T30	121424	0	0	0
T36	3626	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T120	2108	0	0	0
T123	2609	0	0	0
T155	2964	0	0	0
T156	3056	0	0	0
T157	2204	0	0	0
T186	0	2	0	0
T187	0	4	0	0
T188	0	4	0	0
T189	0	3	0	0
T190	0	3	0	0
T191	0	2	0	0
T192	0	6	0	0
T193	2442	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	102723095	160	0	0
CgEnOn_A	102723095	160	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102723095	160	0	0
T3	151051	0	0	0
T10	0	1	0	0
T29	37873	0	0	0
T30	20492	0	0	0
T36	898	3	0	0
T37	0	1	0	0
T38	0	5	0	0
T75	0	1	0	0
T120	533	0	0	0
T123	655	0	0	0
T155	681	0	0	0
T156	721	0	0	0
T157	516	0	0	0
T186	0	3	0	0
T187	0	3	0	0
T188	0	4	0	0
T189	0	2	0	0
T190	0	4	0	0
T193	559	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102723095	160	0	0
T3	151051	0	0	0
T10	0	1	0	0
T29	37873	0	0	0
T30	20492	0	0	0
T36	898	3	0	0
T37	0	1	0	0
T38	0	5	0	0
T75	0	1	0	0
T120	533	0	0	0
T123	655	0	0	0
T155	681	0	0	0
T156	721	0	0	0
T157	516	0	0	0
T186	0	3	0	0
T187	0	3	0	0
T188	0	4	0	0
T189	0	2	0	0
T190	0	4	0	0
T193	559	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	437016983	154	0	0
CgEnOn_A	437016983	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437016983	154	0	0
T3	652712	0	0	0
T29	235935	0	0	0
T30	121424	0	0	0
T36	3626	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T120	2108	0	0	0
T123	2609	0	0	0
T155	2964	0	0	0
T156	3056	0	0	0
T157	2204	0	0	0
T186	0	2	0	0
T187	0	4	0	0
T188	0	4	0	0
T189	0	3	0	0
T190	0	3	0	0
T191	0	2	0	0
T192	0	6	0	0
T193	2442	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437016983	154	0	0
T3	652712	0	0	0
T29	235935	0	0	0
T30	121424	0	0	0
T36	3626	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T120	2108	0	0	0
T123	2609	0	0	0
T155	2964	0	0	0
T156	3056	0	0	0
T157	2204	0	0	0
T186	0	2	0	0
T187	0	4	0	0
T188	0	4	0	0
T189	0	3	0	0
T190	0	3	0	0
T191	0	2	0	0
T192	0	6	0	0
T193	2442	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	102723095	160	0	0
CgEnOn_A	102723095	160	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102723095	160	0	0
T3	151051	0	0	0
T10	0	1	0	0
T29	37873	0	0	0
T30	20492	0	0	0
T36	898	3	0	0
T37	0	1	0	0
T38	0	5	0	0
T75	0	1	0	0
T120	533	0	0	0
T123	655	0	0	0
T155	681	0	0	0
T156	721	0	0	0
T157	516	0	0	0
T186	0	3	0	0
T187	0	3	0	0
T188	0	4	0	0
T189	0	2	0	0
T190	0	4	0	0
T193	559	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102723095	160	0	0
T3	151051	0	0	0
T10	0	1	0	0
T29	37873	0	0	0
T30	20492	0	0	0
T36	898	3	0	0
T37	0	1	0	0
T38	0	5	0	0
T75	0	1	0	0
T120	533	0	0	0
T123	655	0	0	0
T155	681	0	0	0
T156	721	0	0	0
T157	516	0	0	0
T186	0	3	0	0
T187	0	3	0	0
T188	0	4	0	0
T189	0	2	0	0
T190	0	4	0	0
T193	559	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	205447380	7086	0	0
CgEnOn_A	205447380	4754	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205447380	7086	0	0
T1	418541	17	0	0
T4	36295	20	0	0
T5	37869	17	0	0
T6	1570	1	0	0
T7	1037	1	0	0
T17	7160	1	0	0
T18	3164	1	0	0
T19	1698	1	0	0
T24	2138	1	0	0
T25	2558	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205447380	4754	0	0
T1	418541	11	0	0
T2	360307	146	0	0
T5	37869	0	0	0
T17	7160	0	0	0
T18	3164	0	0	0
T19	1698	0	0	0
T20	5510	0	0	0
T21	1356	0	0	0
T22	1662	1	0	0
T23	684	0	0	0
T36	0	3	0	0
T78	0	14	0	0
T79	0	1	0	0
T80	0	13	0	0
T82	0	1	0	0
T83	0	1	0	0
T157	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	102723095	7030	0	0
CgEnOn_A	102723095	4698	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102723095	7030	0	0
T1	209268	16	0	0
T4	18150	20	0	0
T5	18935	17	0	0
T6	785	1	0	0
T7	517	1	0	0
T17	3580	1	0	0
T18	1582	1	0	0
T19	849	1	0	0
T24	1069	1	0	0
T25	1279	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102723095	4698	0	0
T1	209268	10	0	0
T2	180152	139	0	0
T5	18935	0	0	0
T17	3580	0	0	0
T18	1582	0	0	0
T19	849	0	0	0
T20	2754	0	0	0
T21	678	0	0	0
T22	831	1	0	0
T23	342	0	0	0
T36	0	3	0	0
T78	0	15	0	0
T79	0	1	0	0
T80	0	12	0	0
T82	0	1	0	0
T83	0	1	0	0
T157	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	409801198	7123	0	0
CgEnOn_A	409801198	4785	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409801198	7123	0	0
T1	834565	14	0	0
T4	126366	20	0	0
T5	129534	17	0	0
T6	3274	1	0	0
T7	2050	1	0	0
T17	11773	1	0	0
T18	6315	1	0	0
T19	3447	1	0	0
T24	4300	1	0	0
T25	5182	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409801198	4785	0	0
T1	834565	8	0	0
T2	721077	140	0	0
T5	129534	0	0	0
T17	11773	0	0	0
T18	6315	0	0	0
T19	3447	0	0	0
T20	10224	0	0	0
T21	2847	0	0	0
T22	3418	1	0	0
T23	1447	0	0	0
T36	0	3	0	0
T78	0	14	0	0
T79	0	1	0	0
T80	0	13	0	0
T82	0	1	0	0
T83	0	1	0	0
T157	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	209733488	7070	0	0
CgEnOn_A	209733488	4732	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209733488	7070	0	0
T1	463382	15	0	0
T4	63186	20	0	0
T5	64770	17	0	0
T6	1637	1	0	0
T7	1025	1	0	0
T17	5886	1	0	0
T18	3157	1	0	0
T19	1724	1	0	0
T24	2151	1	0	0
T25	2590	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209733488	4732	0	0
T1	463382	9	0	0
T2	369772	142	0	0
T5	64770	0	0	0
T17	5886	0	0	0
T18	3157	0	0	0
T19	1724	0	0	0
T20	5112	0	0	0
T21	1423	0	0	0
T22	1708	1	0	0
T23	723	0	0	0
T36	0	1	0	0
T78	0	16	0	0
T79	0	1	0	0
T80	0	11	0	0
T82	0	1	0	0
T83	0	1	0	0
T157	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T6,T24,T1
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	437016983	3868	0	0
CgEnOn_A	437016983	3868	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437016983	3868	0	0
T1	983365	10	0	0
T2	0	126	0	0
T5	134935	0	0	0
T6	3411	3	0	0
T7	2136	0	0	0
T17	12263	0	0	0
T18	6577	0	0	0
T19	3591	9	0	0
T20	10650	0	0	0
T21	0	6	0	0
T22	0	1	0	0
T24	4479	6	0	0
T25	5398	0	0	0
T79	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437016983	3868	0	0
T1	983365	10	0	0
T2	0	126	0	0
T5	134935	0	0	0
T6	3411	3	0	0
T7	2136	0	0	0
T17	12263	0	0	0
T18	6577	0	0	0
T19	3591	9	0	0
T20	10650	0	0	0
T21	0	6	0	0
T22	0	1	0	0
T24	4479	6	0	0
T25	5398	0	0	0
T79	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T6,T24,T1
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	437016983	3973	0	0
CgEnOn_A	437016983	3973	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437016983	3973	0	0
T1	983365	11	0	0
T2	0	119	0	0
T5	134935	0	0	0
T6	3411	5	0	0
T7	2136	0	0	0
T17	12263	0	0	0
T18	6577	0	0	0
T19	3591	6	0	0
T20	10650	0	0	0
T21	0	8	0	0
T22	0	1	0	0
T24	4479	1	0	0
T25	5398	0	0	0
T79	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437016983	3973	0	0
T1	983365	11	0	0
T2	0	119	0	0
T5	134935	0	0	0
T6	3411	5	0	0
T7	2136	0	0	0
T17	12263	0	0	0
T18	6577	0	0	0
T19	3591	6	0	0
T20	10650	0	0	0
T21	0	8	0	0
T22	0	1	0	0
T24	4479	1	0	0
T25	5398	0	0	0
T79	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T6,T24,T1
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	437016983	3887	0	0
CgEnOn_A	437016983	3887	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437016983	3887	0	0
T1	983365	11	0	0
T2	0	114	0	0
T5	134935	0	0	0
T6	3411	4	0	0
T7	2136	0	0	0
T17	12263	0	0	0
T18	6577	0	0	0
T19	3591	6	0	0
T20	10650	0	0	0
T21	0	6	0	0
T22	0	1	0	0
T24	4479	4	0	0
T25	5398	0	0	0
T79	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437016983	3887	0	0
T1	983365	11	0	0
T2	0	114	0	0
T5	134935	0	0	0
T6	3411	4	0	0
T7	2136	0	0	0
T17	12263	0	0	0
T18	6577	0	0	0
T19	3591	6	0	0
T20	10650	0	0	0
T21	0	6	0	0
T22	0	1	0	0
T24	4479	4	0	0
T25	5398	0	0	0
T79	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T6,T24,T1
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	437016983	3927	0	0
CgEnOn_A	437016983	3927	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437016983	3927	0	0
T1	983365	10	0	0
T2	0	134	0	0
T5	134935	0	0	0
T6	3411	3	0	0
T7	2136	0	0	0
T17	12263	0	0	0
T18	6577	0	0	0
T19	3591	7	0	0
T20	10650	0	0	0
T21	0	3	0	0
T22	0	1	0	0
T24	4479	4	0	0
T25	5398	0	0	0
T79	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437016983	3927	0	0
T1	983365	10	0	0
T2	0	134	0	0
T5	134935	0	0	0
T6	3411	3	0	0
T7	2136	0	0	0
T17	12263	0	0	0
T18	6577	0	0	0
T19	3591	7	0	0
T20	10650	0	0	0
T21	0	3	0	0
T22	0	1	0	0
T24	4479	4	0	0
T25	5398	0	0	0
T79	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0