Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T2
0	1	Covered	T1,T2,T78
1	0	Covered	T4,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T2
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	927706772	12244	0	0
GateOpen_A	927706772	12244	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	927706772	12244	0	0
T1	1925759	27	0	0
T2	1631308	367	0	0
T5	251110	0	0	0
T17	28401	0	0	0
T18	14219	0	0	0
T19	7719	0	0	0
T20	23602	0	0	0
T21	6306	0	0	0
T22	7622	4	0	0
T23	3197	0	0	0
T36	0	10	0	0
T78	0	35	0	0
T79	0	4	0	0
T80	0	24	0	0
T82	0	4	0	0
T83	0	4	0	0
T157	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	927706772	12244	0	0
T1	1925759	27	0	0
T2	1631308	367	0	0
T5	251110	0	0	0
T17	28401	0	0	0
T18	14219	0	0	0
T19	7719	0	0	0
T20	23602	0	0	0
T21	6306	0	0	0
T22	7622	4	0	0
T23	3197	0	0	0
T36	0	10	0	0
T78	0	35	0	0
T79	0	4	0	0
T80	0	24	0	0
T82	0	4	0	0
T83	0	4	0	0
T157	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T2
0	1	Covered	T1,T2,T78
1	0	Covered	T4,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T2
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	102723484	3031	0	0
GateOpen_A	102723484	3031	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102723484	3031	0	0
T1	209269	7	0	0
T2	180152	91	0	0
T5	18936	0	0	0
T17	3580	0	0	0
T18	1582	0	0	0
T19	849	0	0	0
T20	2754	0	0	0
T21	679	0	0	0
T22	832	1	0	0
T23	342	0	0	0
T36	0	3	0	0
T78	0	9	0	0
T79	0	1	0	0
T80	0	4	0	0
T82	0	1	0	0
T83	0	1	0	0
T157	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102723484	3031	0	0
T1	209269	7	0	0
T2	180152	91	0	0
T5	18936	0	0	0
T17	3580	0	0	0
T18	1582	0	0	0
T19	849	0	0	0
T20	2754	0	0	0
T21	679	0	0	0
T22	832	1	0	0
T23	342	0	0	0
T36	0	3	0	0
T78	0	9	0	0
T79	0	1	0	0
T80	0	4	0	0
T82	0	1	0	0
T83	0	1	0	0
T157	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T2
0	1	Covered	T1,T2,T78
1	0	Covered	T4,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T2
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	205447756	3063	0	0
GateOpen_A	205447756	3063	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205447756	3063	0	0
T1	418542	9	0	0
T2	360307	94	0	0
T5	37870	0	0	0
T17	7161	0	0	0
T18	3165	0	0	0
T19	1698	0	0	0
T20	5510	0	0	0
T21	1357	0	0	0
T22	1663	1	0	0
T23	684	0	0	0
T36	0	3	0	0
T78	0	9	0	0
T79	0	1	0	0
T80	0	7	0	0
T82	0	1	0	0
T83	0	1	0	0
T157	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205447756	3063	0	0
T1	418542	9	0	0
T2	360307	94	0	0
T5	37870	0	0	0
T17	7161	0	0	0
T18	3165	0	0	0
T19	1698	0	0	0
T20	5510	0	0	0
T21	1357	0	0	0
T22	1663	1	0	0
T23	684	0	0	0
T36	0	3	0	0
T78	0	9	0	0
T79	0	1	0	0
T80	0	7	0	0
T82	0	1	0	0
T83	0	1	0	0
T157	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T2
0	1	Covered	T1,T2,T78
1	0	Covered	T4,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T2
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	409801623	3089	0	0
GateOpen_A	409801623	3089	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409801623	3089	0	0
T1	834566	5	0	0
T2	721077	92	0	0
T5	129534	0	0	0
T17	11773	0	0	0
T18	6315	0	0	0
T19	3448	0	0	0
T20	10225	0	0	0
T21	2847	0	0	0
T22	3418	1	0	0
T23	1447	0	0	0
T36	0	3	0	0
T78	0	9	0	0
T79	0	1	0	0
T80	0	7	0	0
T82	0	1	0	0
T83	0	1	0	0
T157	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409801623	3089	0	0
T1	834566	5	0	0
T2	721077	92	0	0
T5	129534	0	0	0
T17	11773	0	0	0
T18	6315	0	0	0
T19	3448	0	0	0
T20	10225	0	0	0
T21	2847	0	0	0
T22	3418	1	0	0
T23	1447	0	0	0
T36	0	3	0	0
T78	0	9	0	0
T79	0	1	0	0
T80	0	7	0	0
T82	0	1	0	0
T83	0	1	0	0
T157	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T2
0	1	Covered	T1,T2,T78
1	0	Covered	T4,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T2
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	209733909	3061	0	0
GateOpen_A	209733909	3061	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209733909	3061	0	0
T1	463382	6	0	0
T2	369772	90	0	0
T5	64770	0	0	0
T17	5887	0	0	0
T18	3157	0	0	0
T19	1724	0	0	0
T20	5113	0	0	0
T21	1423	0	0	0
T22	1709	1	0	0
T23	724	0	0	0
T36	0	1	0	0
T78	0	8	0	0
T79	0	1	0	0
T80	0	6	0	0
T82	0	1	0	0
T83	0	1	0	0
T157	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209733909	3061	0	0
T1	463382	6	0	0
T2	369772	90	0	0
T5	64770	0	0	0
T17	5887	0	0	0
T18	3157	0	0	0
T19	1724	0	0	0
T20	5113	0	0	0
T21	1423	0	0	0
T22	1709	1	0	0
T23	724	0	0	0
T36	0	1	0	0
T78	0	8	0	0
T79	0	1	0	0
T80	0	6	0	0
T82	0	1	0	0
T83	0	1	0	0
T157	0	1	0	0