Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	654729	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3935681

1

T7

8

T8

45

T9

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1127835	1			T7	8		T8	68		T9	64
values[0x0]	1589802	1			T7	7		T8	19		T9	21
values[0x1]	1872773	1			T7	10		T8	32		T9	27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	355103	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4235307

1

T7

8

T8

51

T9

51

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17236	1			T8	2		T29	1		T1	2
valid_sources[0x01]	18232	1			T4	2		T1	2		T21	1
valid_sources[0x02]	16488	1			T1	2		T23	12		T5	2
valid_sources[0x03]	17049	1			T8	1		T30	2		T1	3
valid_sources[0x04]	17308	1			T29	2		T1	4		T22	2
valid_sources[0x05]	19599	1			T4	7		T23	5		T2	362
valid_sources[0x06]	16890	1			T4	1		T19	1		T5	3
valid_sources[0x07]	18026	1			T8	1		T4	1		T1	3
valid_sources[0x08]	17263	1			T8	1		T31	5		T22	2
valid_sources[0x09]	15686	1			T8	1		T9	1		T4	5
valid_sources[0x0a]	18495	1			T4	2		T1	1		T23	7
valid_sources[0x0b]	16445	1			T9	5		T29	1		T4	4
valid_sources[0x0c]	18643	1			T9	1		T4	5		T1	3
valid_sources[0x0d]	16313	1			T8	2		T30	4		T34	1
valid_sources[0x0e]	17308	1			T8	1		T1	1		T19	1
valid_sources[0x0f]	17313	1			T8	2		T1	4		T5	2
valid_sources[0x10]	18726	1			T7	1		T29	1		T31	5
valid_sources[0x11]	17207	1			T8	1		T9	1		T29	4
valid_sources[0x12]	18039	1			T8	1		T9	3		T23	14
valid_sources[0x13]	16555	1			T30	1		T4	4		T1	1
valid_sources[0x14]	17181	1			T19	1		T23	5		T5	2
valid_sources[0x15]	17299	1			T5	1		T2	345		T181	4
valid_sources[0x16]	17913	1			T7	4		T9	3		T31	1
valid_sources[0x17]	17686	1			T8	1		T30	1		T4	1
valid_sources[0x18]	17478	1			T1	4		T5	2		T2	349
valid_sources[0x19]	17538	1			T4	10		T1	2		T19	1
valid_sources[0x1a]	16506	1			T34	1		T1	1		T19	1
valid_sources[0x1b]	15797	1			T7	1		T29	1		T23	21
valid_sources[0x1c]	16708	1			T31	2		T4	1		T21	1
valid_sources[0x1d]	18228	1			T8	2		T4	3		T1	3
valid_sources[0x1e]	17545	1			T9	4		T29	1		T4	2
valid_sources[0x1f]	16538	1			T8	1		T9	2		T29	1
valid_sources[0x20]	19810	1			T4	2		T39	2		T19	1
valid_sources[0x21]	17708	1			T21	1		T23	4		T5	1
valid_sources[0x22]	17433	1			T4	2		T1	2		T22	1
valid_sources[0x23]	18401	1			T19	1		T5	5		T2	358
valid_sources[0x24]	17988	1			T7	1		T8	1		T1	2
valid_sources[0x25]	17629	1			T23	8		T5	4		T2	332
valid_sources[0x26]	18650	1			T1	2		T19	2		T23	11
valid_sources[0x27]	19591	1			T9	4		T4	3		T5	4
valid_sources[0x28]	18816	1			T8	1		T4	2		T5	1
valid_sources[0x29]	18204	1			T8	1		T27	2		T29	1
valid_sources[0x2a]	18534	1			T29	1		T1	1		T21	1
valid_sources[0x2b]	17914	1			T8	3		T4	1		T39	1
valid_sources[0x2c]	16803	1			T8	1		T9	2		T30	1
valid_sources[0x2d]	18490	1			T4	2		T1	3		T23	3
valid_sources[0x2e]	20361	1			T9	1		T1	1		T5	1
valid_sources[0x2f]	17300	1			T23	1		T5	14		T2	330
valid_sources[0x30]	18156	1			T30	3		T4	5		T19	1
valid_sources[0x31]	18036	1			T4	2		T1	2		T21	1
valid_sources[0x32]	17772	1			T9	9		T1	2		T2	323
valid_sources[0x33]	17629	1			T1	1		T19	2		T23	6
valid_sources[0x34]	18456	1			T8	1		T9	5		T19	1
valid_sources[0x35]	17658	1			T8	1		T22	2		T5	4
valid_sources[0x36]	18302	1			T9	8		T29	1		T4	1
valid_sources[0x37]	17085	1			T8	2		T21	1		T22	1
valid_sources[0x38]	18559	1			T29	1		T23	3		T5	1
valid_sources[0x39]	17370	1			T4	1		T1	2		T19	3
valid_sources[0x3a]	19731	1			T4	2		T23	1		T5	2
valid_sources[0x3b]	17570	1			T8	1		T9	1		T28	61
valid_sources[0x3c]	17075	1			T29	1		T4	3		T1	1
valid_sources[0x3d]	18289	1			T4	1		T19	1		T22	1
valid_sources[0x3e]	18539	1			T4	1		T1	1		T19	2
valid_sources[0x3f]	17964	1			T1	1		T21	1		T22	1
valid_sources[0x40]	16113	1			T27	2		T17	1		T21	1
valid_sources[0x41]	18055	1			T7	1		T8	1		T1	3
valid_sources[0x42]	17490	1			T29	1		T21	1		T5	9
valid_sources[0x43]	18529	1			T1	2		T5	1		T2	323
valid_sources[0x44]	21060	1			T1	3		T19	1		T5	3
valid_sources[0x45]	18186	1			T8	2		T6	17		T5	1
valid_sources[0x46]	18270	1			T8	3		T4	3		T1	2
valid_sources[0x47]	18508	1			T8	1		T9	1		T29	1
valid_sources[0x48]	17640	1			T30	1		T31	1		T4	1
valid_sources[0x49]	18832	1			T9	3		T4	1		T5	1
valid_sources[0x4a]	17047	1			T9	1		T1	1		T19	1
valid_sources[0x4b]	18408	1			T8	2		T27	1		T1	2
valid_sources[0x4c]	17955	1			T9	3		T27	5		T4	1
valid_sources[0x4d]	17066	1			T27	1		T1	2		T21	1
valid_sources[0x4e]	17574	1			T8	1		T1	3		T21	2
valid_sources[0x4f]	17585	1			T4	1		T1	2		T5	2
valid_sources[0x50]	17151	1			T8	1		T1	3		T2	349
valid_sources[0x51]	17557	1			T5	4		T2	339		T179	2
valid_sources[0x52]	17043	1			T1	8		T21	2		T5	1
valid_sources[0x53]	19252	1			T7	1		T29	1		T1	3
valid_sources[0x54]	17315	1			T1	2		T19	1		T23	4
valid_sources[0x55]	16901	1			T8	1		T29	1		T4	3
valid_sources[0x56]	18012	1			T39	1		T19	1		T22	1
valid_sources[0x57]	17205	1			T29	1		T17	2		T21	3
valid_sources[0x58]	20638	1			T1	1		T23	2		T2	328
valid_sources[0x59]	18894	1			T5	4		T2	335		T32	1
valid_sources[0x5a]	17910	1			T29	1		T4	1		T1	1
valid_sources[0x5b]	17070	1			T1	2		T19	2		T22	2
valid_sources[0x5c]	17442	1			T8	1		T29	1		T1	1
valid_sources[0x5d]	16667	1			T4	2		T1	6		T5	3
valid_sources[0x5e]	18684	1			T8	2		T1	3		T5	6
valid_sources[0x5f]	19651	1			T7	2		T9	2		T29	1
valid_sources[0x60]	17430	1			T8	1		T4	2		T1	4
valid_sources[0x61]	19257	1			T9	2		T1	3		T5	3
valid_sources[0x62]	17034	1			T8	2		T1	1		T23	13
valid_sources[0x63]	17792	1			T27	6		T1	3		T5	1
valid_sources[0x64]	18152	1			T1	1		T23	2		T5	6
valid_sources[0x65]	18756	1			T29	1		T4	1		T1	1
valid_sources[0x66]	15039	1			T29	1		T30	1		T4	2
valid_sources[0x67]	17008	1			T8	1		T21	1		T2	311
valid_sources[0x68]	17845	1			T9	3		T1	6		T19	1
valid_sources[0x69]	17146	1			T29	1		T23	4		T5	5
valid_sources[0x6a]	16584	1			T23	2		T5	2		T2	318
valid_sources[0x6b]	17919	1			T8	1		T9	2		T29	1
valid_sources[0x6c]	18921	1			T9	1		T29	3		T4	1
valid_sources[0x6d]	18947	1			T7	2		T8	2		T9	3
valid_sources[0x6e]	17154	1			T8	1		T4	1		T5	6
valid_sources[0x6f]	19829	1			T27	1		T23	16		T2	362
valid_sources[0x70]	18840	1			T7	1		T4	1		T23	5
valid_sources[0x71]	18059	1			T7	1		T8	2		T1	1
valid_sources[0x72]	16787	1			T29	2		T4	1		T1	2
valid_sources[0x73]	19364	1			T9	1		T30	1		T1	1
valid_sources[0x74]	18321	1			T7	1		T1	4		T23	2
valid_sources[0x75]	17244	1			T27	3		T1	7		T19	1
valid_sources[0x76]	17755	1			T4	1		T1	2		T22	1
valid_sources[0x77]	17243	1			T8	1		T4	1		T1	2
valid_sources[0x78]	18646	1			T8	1		T4	4		T1	4
valid_sources[0x79]	17494	1			T1	5		T23	1		T5	6
valid_sources[0x7a]	17719	1			T4	3		T1	2		T19	1
valid_sources[0x7b]	20243	1			T29	1		T1	1		T22	3
valid_sources[0x7c]	17142	1			T1	1		T21	2		T5	1
valid_sources[0x7d]	18904	1			T4	1		T23	1		T2	360
valid_sources[0x7e]	17891	1			T8	1		T27	1		T6	15
valid_sources[0x7f]	18327	1			T7	1		T8	1		T6	26
valid_sources[0x80]	16620	1			T29	2		T4	1		T1	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

993559

1

T7

4

T8

32

T9

32

values[0x0]

all_enables

biggest_size

1494770

1

T7

2

T8

4

T9

7

values[0x1]

all_enables

biggest_size

1447352

1

T7

2

T8

9

T9

1