Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	844276670	73299	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	844276670	73299	0	0
T1	462670	274	0	0
T2	0	2101	0	0
T3	0	77	0	0
T10	0	775	0	0
T11	0	277	0	0
T12	0	785	0	0
T13	0	420	0	0
T14	0	306	0	0
T15	0	304	0	0
T16	0	177	0	0
T17	8595	0	0	0
T18	15320	0	0	0
T19	11860	0	0	0
T20	11755	0	0	0
T21	11920	0	0	0
T22	14145	0	0	0
T23	56255	0	0	0
T24	7585	0	0	0
T25	6710	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168855334	10718	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168855334	10718	0	0
T1	92534	41	0	0
T2	0	309	0	0
T3	0	11	0	0
T10	0	101	0	0
T11	0	36	0	0
T12	0	126	0	0
T13	0	57	0	0
T14	0	49	0	0
T15	0	43	0	0
T16	0	28	0	0
T17	1719	0	0	0
T18	3064	0	0	0
T19	2372	0	0	0
T20	2351	0	0	0
T21	2384	0	0	0
T22	2829	0	0	0
T23	11251	0	0	0
T24	1517	0	0	0
T25	1342	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168855334	14744	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168855334	14744	0	0
T1	92534	56	0	0
T2	0	427	0	0
T3	0	15	0	0
T10	0	153	0	0
T11	0	57	0	0
T12	0	157	0	0
T13	0	84	0	0
T14	0	63	0	0
T15	0	62	0	0
T16	0	36	0	0
T17	1719	0	0	0
T18	3064	0	0	0
T19	2372	0	0	0
T20	2351	0	0	0
T21	2384	0	0	0
T22	2829	0	0	0
T23	11251	0	0	0
T24	1517	0	0	0
T25	1342	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168855334	22612	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168855334	22612	0	0
T1	92534	81	0	0
T2	0	690	0	0
T3	0	23	0	0
T10	0	264	0	0
T11	0	91	0	0
T12	0	217	0	0
T13	0	141	0	0
T14	0	84	0	0
T15	0	98	0	0
T16	0	49	0	0
T17	1719	0	0	0
T18	3064	0	0	0
T19	2372	0	0	0
T20	2351	0	0	0
T21	2384	0	0	0
T22	2829	0	0	0
T23	11251	0	0	0
T24	1517	0	0	0
T25	1342	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168855334	10485	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168855334	10485	0	0
T1	92534	41	0	0
T2	0	263	0	0
T3	0	11	0	0
T10	0	100	0	0
T11	0	40	0	0
T12	0	125	0	0
T13	0	54	0	0
T14	0	47	0	0
T15	0	41	0	0
T16	0	28	0	0
T17	1719	0	0	0
T18	3064	0	0	0
T19	2372	0	0	0
T20	2351	0	0	0
T21	2384	0	0	0
T22	2829	0	0	0
T23	11251	0	0	0
T24	1517	0	0	0
T25	1342	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168855334	14740	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168855334	14740	0	0
T1	92534	55	0	0
T2	0	412	0	0
T3	0	17	0	0
T10	0	157	0	0
T11	0	53	0	0
T12	0	160	0	0
T13	0	84	0	0
T14	0	63	0	0
T15	0	60	0	0
T16	0	36	0	0
T17	1719	0	0	0
T18	3064	0	0	0
T19	2372	0	0	0
T20	2351	0	0	0
T21	2384	0	0	0
T22	2829	0	0	0
T23	11251	0	0	0
T24	1517	0	0	0
T25	1342	0	0	0