Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T23,T5

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	168855334	166424580	0	0
AllClkBypReqTrue_A	168855334	135617	0	0
IoClkBypReqFalse_A	168855334	166338181	0	2415
IoClkBypReqTrue_A	168855334	217200	0	0
LcClkBypAckFalse_A	168855334	166431503	0	0
LcClkBypAckTrue_A	168855334	128694	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168855334	166424580	0	0
T4	30367	2255	0	0
T6	84427	84231	0	0
T7	1202	1148	0	0
T8	3483	3357	0	0
T9	1945	1918	0	0
T27	2543	2205	0	0
T28	2102	2005	0	0
T29	2602	2456	0	0
T30	1782	1622	0	0
T31	2320	1923	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168855334	135617	0	0
T2	0	1955	0	0
T4	30367	0	0	0
T6	84427	0	0	0
T7	1202	26	0	0
T8	3483	0	0	0
T9	1945	0	0	0
T20	0	57	0	0
T23	0	275	0	0
T27	2543	207	0	0
T28	2102	50	0	0
T29	2602	25	0	0
T30	1782	68	0	0
T31	2320	138	0	0
T42	0	4	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168855334	166338181	0	2415
T4	30367	2243	0	3
T6	84427	84229	0	3
T7	1202	1172	0	3
T8	3483	3355	0	3
T9	1945	1916	0	3
T27	2543	2371	0	3
T28	2102	1538	0	3
T29	2602	1924	0	3
T30	1782	1634	0	3
T31	2320	1750	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168855334	217200	0	0
T2	0	2767	0	0
T4	30367	0	0	0
T6	84427	0	0	0
T20	0	403	0	0
T22	0	619	0	0
T23	0	366	0	0
T27	2543	39	0	0
T28	2102	515	0	0
T29	2602	555	0	0
T30	1782	54	0	0
T31	2320	309	0	0
T34	702	0	0	0
T39	1398	0	0	0
T40	2143	428	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168855334	166431503	0	0
T4	30367	2255	0	0
T6	84427	84231	0	0
T7	1202	1174	0	0
T8	3483	3357	0	0
T9	1945	1918	0	0
T27	2543	2412	0	0
T28	2102	1843	0	0
T29	2602	2267	0	0
T30	1782	1644	0	0
T31	2320	1916	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168855334	128694	0	0
T1	92534	0	0	0
T2	0	1628	0	0
T4	30367	0	0	0
T6	84427	0	0	0
T20	0	165	0	0
T22	0	220	0	0
T23	0	242	0	0
T28	2102	212	0	0
T29	2602	214	0	0
T30	1782	46	0	0
T31	2320	145	0	0
T34	702	0	0	0
T39	1398	0	0	0
T40	2143	176	0	0
T42	0	86	0	0