Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	15677	0	0
TransStop_A	2147483647	8081	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15677	0	0
T2	0	257	0	0
T4	121472	0	0	0
T6	344692	0	0	0
T8	28428	29	0	0
T9	28816	29	0	0
T18	0	36	0	0
T19	0	4	0	0
T21	0	19	0	0
T23	0	70	0	0
T24	0	4	0	0
T27	10944	0	0	0
T28	38232	0	0	0
T29	20820	0	0	0
T30	14264	0	0	0
T31	9672	0	0	0
T34	11716	0	0	0
T41	0	18	0	0
T125	0	36	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8081	0	0
T2	0	113	0	0
T4	121472	0	0	0
T6	344692	0	0	0
T8	28428	18	0	0
T9	28816	19	0	0
T18	0	15	0	0
T19	0	4	0	0
T21	0	14	0	0
T23	0	36	0	0
T24	0	4	0	0
T27	10944	0	0	0
T28	38232	0	0	0
T29	20820	0	0	0
T30	14264	0	0	0
T31	9672	0	0	0
T34	11716	0	0	0
T41	0	10	0	0
T125	0	15	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	544248311	3979	0	0
TransStop_A	544248311	2066	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544248311	3979	0	0
T2	0	76	0	0
T4	30368	0	0	0
T6	86173	0	0	0
T8	7107	6	0	0
T9	7204	5	0	0
T18	0	8	0	0
T19	0	1	0	0
T21	0	5	0	0
T23	0	20	0	0
T24	0	1	0	0
T27	2736	0	0	0
T28	9558	0	0	0
T29	5205	0	0	0
T30	3566	0	0	0
T31	2418	0	0	0
T34	2929	0	0	0
T41	0	4	0	0
T125	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544248311	2066	0	0
T2	0	35	0	0
T4	30368	0	0	0
T6	86173	0	0	0
T8	7107	4	0	0
T9	7204	2	0	0
T18	0	3	0	0
T19	0	1	0	0
T21	0	3	0	0
T23	0	10	0	0
T24	0	1	0	0
T27	2736	0	0	0
T28	9558	0	0	0
T29	5205	0	0	0
T30	3566	0	0	0
T31	2418	0	0	0
T34	2929	0	0	0
T41	0	4	0	0
T125	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	544248311	3924	0	0
TransStop_A	544248311	2010	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544248311	3924	0	0
T2	0	62	0	0
T4	30368	0	0	0
T6	86173	0	0	0
T8	7107	6	0	0
T9	7204	7	0	0
T18	0	13	0	0
T19	0	1	0	0
T21	0	5	0	0
T23	0	16	0	0
T24	0	1	0	0
T27	2736	0	0	0
T28	9558	0	0	0
T29	5205	0	0	0
T30	3566	0	0	0
T31	2418	0	0	0
T34	2929	0	0	0
T41	0	5	0	0
T125	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544248311	2010	0	0
T2	0	28	0	0
T4	30368	0	0	0
T6	86173	0	0	0
T8	7107	3	0	0
T9	7204	5	0	0
T18	0	6	0	0
T19	0	1	0	0
T21	0	3	0	0
T23	0	8	0	0
T24	0	1	0	0
T27	2736	0	0	0
T28	9558	0	0	0
T29	5205	0	0	0
T30	3566	0	0	0
T31	2418	0	0	0
T34	2929	0	0	0
T41	0	2	0	0
T125	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	544248311	3877	0	0
TransStop_A	544248311	1974	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544248311	3877	0	0
T2	0	64	0	0
T4	30368	0	0	0
T6	86173	0	0	0
T8	7107	8	0	0
T9	7204	8	0	0
T18	0	6	0	0
T19	0	1	0	0
T21	0	5	0	0
T23	0	16	0	0
T24	0	1	0	0
T27	2736	0	0	0
T28	9558	0	0	0
T29	5205	0	0	0
T30	3566	0	0	0
T31	2418	0	0	0
T34	2929	0	0	0
T41	0	3	0	0
T125	0	12	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544248311	1974	0	0
T2	0	26	0	0
T4	30368	0	0	0
T6	86173	0	0	0
T8	7107	6	0	0
T9	7204	5	0	0
T18	0	1	0	0
T19	0	1	0	0
T21	0	5	0	0
T23	0	7	0	0
T24	0	1	0	0
T27	2736	0	0	0
T28	9558	0	0	0
T29	5205	0	0	0
T30	3566	0	0	0
T31	2418	0	0	0
T34	2929	0	0	0
T41	0	2	0	0
T125	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	544248311	3897	0	0
TransStop_A	544248311	2031	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544248311	3897	0	0
T2	0	55	0	0
T4	30368	0	0	0
T6	86173	0	0	0
T8	7107	9	0	0
T9	7204	9	0	0
T18	0	9	0	0
T19	0	1	0	0
T21	0	4	0	0
T23	0	18	0	0
T24	0	1	0	0
T27	2736	0	0	0
T28	9558	0	0	0
T29	5205	0	0	0
T30	3566	0	0	0
T31	2418	0	0	0
T34	2929	0	0	0
T41	0	6	0	0
T125	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544248311	2031	0	0
T2	0	24	0	0
T4	30368	0	0	0
T6	86173	0	0	0
T8	7107	5	0	0
T9	7204	7	0	0
T18	0	5	0	0
T19	0	1	0	0
T21	0	3	0	0
T23	0	11	0	0
T24	0	1	0	0
T27	2736	0	0	0
T28	9558	0	0	0
T29	5205	0	0	0
T30	3566	0	0	0
T31	2418	0	0	0
T34	2929	0	0	0
T41	0	2	0	0
T125	0	3	0	0