Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT7,T8,T9
01CoveredT7,T8,T9
10CoveredT27,T28,T29 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT7,T8,T9
10CoveredT27,T28,T29
11CoveredT27,T28,T29 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT27,T28,T29
10CoveredT7,T8,T9
11CoveredT7,T8,T9
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 637980580 637978165 0 0
selKnown1 1536981048 1536978633 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 637980580 637978165 0 0
T4 17796 17793 0 0
T6 88905 88902 0 0
T7 5915 5912 0 0
T8 8360 8357 0 0
T9 8612 8609 0 0
T27 3302 3299 0 0
T28 12188 12185 0 0
T29 6483 6480 0 0
T30 4402 4399 0 0
T31 2870 2867 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1536981048 1536978633 0 0
T4 87456 87453 0 0
T6 213609 213606 0 0
T7 14433 14430 0 0
T8 20466 20463 0 0
T9 20742 20739 0 0
T27 7878 7875 0 0
T28 27525 27522 0 0
T29 14988 14985 0 0
T30 10269 10266 0 0
T31 6960 6957 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT7,T8,T9
01CoveredT7,T8,T9
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT7,T8,T9
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT7,T8,T9
11CoveredT7,T8,T9
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 255334947 255334142 0 0
selKnown1 512327016 512326211 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 255334947 255334142 0 0
T4 7118 7117 0 0
T6 35562 35561 0 0
T7 2366 2365 0 0
T8 3344 3343 0 0
T9 3445 3444 0 0
T27 1344 1343 0 0
T28 5099 5098 0 0
T29 2689 2688 0 0
T30 1834 1833 0 0
T31 1185 1184 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 512327016 512326211 0 0
T4 29152 29151 0 0
T6 71203 71202 0 0
T7 4811 4810 0 0
T8 6822 6821 0 0
T9 6914 6913 0 0
T27 2626 2625 0 0
T28 9175 9174 0 0
T29 4996 4995 0 0
T30 3423 3422 0 0
T31 2320 2319 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT7,T8,T9
01CoveredT7,T8,T9
10CoveredT27,T28,T29 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT7,T8,T9
10CoveredT27,T28,T29
11CoveredT27,T28,T29 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT27,T28,T29
10CoveredT7,T8,T9
11CoveredT7,T8,T9
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 254978795 254977990 0 0
selKnown1 512327016 512326211 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 254978795 254977990 0 0
T4 7118 7117 0 0
T6 35562 35561 0 0
T7 2366 2365 0 0
T8 3344 3343 0 0
T9 3445 3444 0 0
T27 1287 1286 0 0
T28 4541 4540 0 0
T29 2452 2451 0 0
T30 1651 1650 0 0
T31 1093 1092 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 512327016 512326211 0 0
T4 29152 29151 0 0
T6 71203 71202 0 0
T7 4811 4810 0 0
T8 6822 6821 0 0
T9 6914 6913 0 0
T27 2626 2625 0 0
T28 9175 9174 0 0
T29 4996 4995 0 0
T30 3423 3422 0 0
T31 2320 2319 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT7,T8,T9
01CoveredT7,T8,T9
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT7,T8,T9
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT7,T8,T9
11CoveredT7,T8,T9
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 127666838 127666033 0 0
selKnown1 512327016 512326211 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 127666838 127666033 0 0
T4 3560 3559 0 0
T6 17781 17780 0 0
T7 1183 1182 0 0
T8 1672 1671 0 0
T9 1722 1721 0 0
T27 671 670 0 0
T28 2548 2547 0 0
T29 1342 1341 0 0
T30 917 916 0 0
T31 592 591 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 512327016 512326211 0 0
T4 29152 29151 0 0
T6 71203 71202 0 0
T7 4811 4810 0 0
T8 6822 6821 0 0
T9 6914 6913 0 0
T27 2626 2625 0 0
T28 9175 9174 0 0
T29 4996 4995 0 0
T30 3423 3422 0 0
T31 2320 2319 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%