Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	168855334	21883238	0	62

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168855334	21883238	0	62
T1	92534	24426	0	1
T2	0	250415	0	0
T3	0	6742	0	1
T10	0	95127	0	0
T11	0	37175	0	0
T12	0	50390	0	0
T13	0	49226	0	0
T14	0	21800	0	0
T16	0	0	0	1
T17	1719	0	0	0
T18	3064	0	0	0
T19	2372	0	0	0
T20	2351	0	0	0
T21	2384	0	0	0
T22	2829	0	0	0
T23	11251	0	0	0
T24	1517	0	0	0
T25	1342	0	0	0
T32	0	974	0	1
T38	0	1584	0	0
T88	0	0	0	1
T126	0	0	0	1
T127	0	0	0	1
T128	0	0	0	1
T129	0	0	0	1
T130	0	0	0	1