Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	929263	0	0
SrcPulseCheck_M	2147483647	924883	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	929263
T1	779717	380
T2	0	7229
T3	0	228
T4	114800	50
T5	0	160
T6	366269	400
T10	0	3228
T17	7894	0
T18	14152	0
T26	0	20
T30	15190	0
T31	11205	0
T32	0	90
T34	11224	0
T35	0	760
T36	0	42
T37	0	49
T38	0	1430
T39	11535	0
T40	19716	0
T67	13050	1
T68	6011	0
T71	11280	1
T72	7152	2
T73	25448	2
T131	23242	2
T132	14582	2
T133	19830	2
T134	2838	3
T135	11248	0
T136	5655	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	924883
T1	277224	380
T2	0	7139
T3	0	228
T4	68132	50
T5	0	160
T6	205100	400
T10	0	3228
T17	4708	0
T18	8436	0
T26	0	20
T30	6394	0
T31	6501	0
T32	0	90
T34	3586	0
T35	0	760
T36	0	42
T37	0	49
T38	0	1430
T39	4910	0
T40	7998	0
T67	11916	1
T68	5337	0
T71	4830	1
T72	13488	2
T73	13250	2
T131	10012	2
T132	8338	2
T133	71706	2
T134	5667	3
T135	4811	0
T136	2257	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	514851714	24354	0	0
SrcPulseCheck_M	169868639	24354	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	514851714	24354
T1	181283	32
T2	0	373
T4	29152	10
T5	0	32
T6	71203	16
T17	1684	0
T18	2942	0
T26	0	4
T30	3423	0
T31	2320	0
T32	0	6
T34	2812	0
T35	0	28
T36	0	2
T37	0	2
T39	2685	0
T40	4472	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169868639	24354
T1	92534	32
T2	0	373
T4	30367	10
T5	0	32
T6	84427	16
T17	1719	0
T18	3064	0
T26	0	4
T30	1782	0
T31	2320	0
T32	0	6
T34	702	0
T35	0	28
T36	0	2
T37	0	2
T39	1398	0
T40	2143	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	514851714	30358	0	0
SrcPulseCheck_M	169868639	30369	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	514851714	30358
T1	181283	32
T2	0	386
T4	29152	20
T5	0	64
T6	71203	16
T17	1684	0
T18	2942	0
T26	0	8
T30	3423	0
T31	2320	0
T32	0	6
T34	2812	0
T35	0	28
T36	0	2
T37	0	2
T39	2685	0
T40	4472	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169868639	30369
T1	92534	32
T2	0	386
T4	30367	20
T5	0	64
T6	84427	16
T17	1719	0
T18	3064	0
T26	0	8
T30	1782	0
T31	2320	0
T32	0	6
T34	702	0
T35	0	28
T36	0	2
T37	0	2
T39	1398	0
T40	2143	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169868639	30357	0	0
SrcPulseCheck_M	514851714	30360	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169868639	30357
T1	92534	32
T2	0	386
T4	30367	20
T5	0	64
T6	84427	16
T17	1719	0
T18	3064	0
T26	0	8
T30	1782	0
T31	2320	0
T32	0	6
T34	702	0
T35	0	28
T36	0	2
T37	0	2
T39	1398	0
T40	2143	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	514851714	30360
T1	181283	32
T2	0	386
T4	29152	20
T5	0	64
T6	71203	16
T17	1684	0
T18	2942	0
T26	0	8
T30	3423	0
T31	2320	0
T32	0	6
T34	2812	0
T35	0	28
T36	0	2
T37	0	2
T39	2685	0
T40	4472	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	256551798	24354	0	0
SrcPulseCheck_M	169868639	24354	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	256551798	24354
T1	90588	32
T2	0	373
T4	7118	10
T5	0	32
T6	35562	16
T17	782	0
T18	1452	0
T26	0	4
T30	1834	0
T31	1185	0
T32	0	6
T34	1366	0
T35	0	28
T36	0	2
T37	0	2
T39	1330	0
T40	2412	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169868639	24354
T1	92534	32
T2	0	373
T4	30367	10
T5	0	32
T6	84427	16
T17	1719	0
T18	3064	0
T26	0	4
T30	1782	0
T31	2320	0
T32	0	6
T34	702	0
T35	0	28
T36	0	2
T37	0	2
T39	1398	0
T40	2143	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	256551798	30363	0	0
SrcPulseCheck_M	169868639	30390	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	256551798	30363
T1	90588	32
T2	0	386
T4	7118	20
T5	0	64
T6	35562	16
T17	782	0
T18	1452	0
T26	0	8
T30	1834	0
T31	1185	0
T32	0	6
T34	1366	0
T35	0	28
T36	0	2
T37	0	2
T39	1330	0
T40	2412	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169868639	30390
T1	92534	32
T2	0	386
T4	30367	20
T5	0	64
T6	84427	16
T17	1719	0
T18	3064	0
T26	0	8
T30	1782	0
T31	2320	0
T32	0	6
T34	702	0
T35	0	28
T36	0	2
T37	0	2
T39	1398	0
T40	2143	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169868639	30355	0	0
SrcPulseCheck_M	256551798	30367	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169868639	30355
T1	92534	32
T2	0	386
T4	30367	20
T5	0	64
T6	84427	16
T17	1719	0
T18	3064	0
T26	0	8
T30	1782	0
T31	2320	0
T32	0	6
T34	702	0
T35	0	28
T36	0	2
T37	0	2
T39	1398	0
T40	2143	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	256551798	30367
T1	90588	32
T2	0	386
T4	7118	20
T5	0	64
T6	35562	16
T17	782	0
T18	1452	0
T26	0	8
T30	1834	0
T31	1185	0
T32	0	6
T34	1366	0
T35	0	28
T36	0	2
T37	0	2
T39	1330	0
T40	2412	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	128275271	24354	0	0
SrcPulseCheck_M	169868639	24354	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	128275271	24354
T1	45294	32
T2	0	373
T4	3560	10
T5	0	32
T6	17781	16
T17	391	0
T18	726	0
T26	0	4
T30	917	0
T31	592	0
T32	0	6
T34	683	0
T35	0	28
T36	0	2
T37	0	2
T39	665	0
T40	1206	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169868639	24354
T1	92534	32
T2	0	373
T4	30367	10
T5	0	32
T6	84427	16
T17	1719	0
T18	3064	0
T26	0	4
T30	1782	0
T31	2320	0
T32	0	6
T34	702	0
T35	0	28
T36	0	2
T37	0	2
T39	1398	0
T40	2143	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	128275271	30508	0	0
SrcPulseCheck_M	169868639	30537	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	128275271	30508
T1	45294	32
T2	0	386
T4	3560	20
T5	0	64
T6	17781	16
T17	391	0
T18	726	0
T26	0	8
T30	917	0
T31	592	0
T32	0	6
T34	683	0
T35	0	28
T36	0	2
T37	0	2
T39	665	0
T40	1206	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169868639	30537
T1	92534	32
T2	0	386
T4	30367	20
T5	0	64
T6	84427	16
T17	1719	0
T18	3064	0
T26	0	8
T30	1782	0
T31	2320	0
T32	0	6
T34	702	0
T35	0	28
T36	0	2
T37	0	2
T39	1398	0
T40	2143	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169868639	30503	0	0
SrcPulseCheck_M	128275271	30511	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169868639	30503
T1	92534	32
T2	0	386
T4	30367	20
T5	0	64
T6	84427	16
T17	1719	0
T18	3064	0
T26	0	8
T30	1782	0
T31	2320	0
T32	0	6
T34	702	0
T35	0	28
T36	0	2
T37	0	2
T39	1398	0
T40	2143	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	128275271	30511
T1	45294	32
T2	0	386
T4	3560	20
T5	0	64
T6	17781	16
T17	391	0
T18	726	0
T26	0	8
T30	917	0
T31	592	0
T32	0	6
T34	683	0
T35	0	28
T36	0	2
T37	0	2
T39	665	0
T40	1206	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	546877847	24354	0	0
SrcPulseCheck_M	169868639	24354	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	546877847	24354
T1	188842	32
T2	0	373
T4	30367	10
T5	0	32
T6	86172	16
T17	1754	0
T18	3064	0
T26	0	4
T30	3566	0
T31	2418	0
T32	0	6
T34	2929	0
T35	0	28
T36	0	2
T37	0	2
T39	2797	0
T40	4659	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169868639	24354
T1	92534	32
T2	0	373
T4	30367	10
T5	0	32
T6	84427	16
T17	1719	0
T18	3064	0
T26	0	4
T30	1782	0
T31	2320	0
T32	0	6
T34	702	0
T35	0	28
T36	0	2
T37	0	2
T39	1398	0
T40	2143	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	546877847	30336	0	0
SrcPulseCheck_M	169868639	30353	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	546877847	30336
T1	188842	32
T2	0	386
T4	30367	20
T5	0	64
T6	86172	16
T17	1754	0
T18	3064	0
T26	0	8
T30	3566	0
T31	2418	0
T32	0	6
T34	2929	0
T35	0	28
T36	0	2
T37	0	2
T39	2797	0
T40	4659	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169868639	30353
T1	92534	32
T2	0	386
T4	30367	20
T5	0	64
T6	84427	16
T17	1719	0
T18	3064	0
T26	0	8
T30	1782	0
T31	2320	0
T32	0	6
T34	702	0
T35	0	28
T36	0	2
T37	0	2
T39	1398	0
T40	2143	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169868639	30327	0	0
SrcPulseCheck_M	546877847	30339	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169868639	30327
T1	92534	32
T2	0	386
T4	30367	20
T5	0	64
T6	84427	16
T17	1719	0
T18	3064	0
T26	0	8
T30	1782	0
T31	2320	0
T32	0	6
T34	702	0
T35	0	28
T36	0	2
T37	0	2
T39	1398	0
T40	2143	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	546877847	30339
T1	188842	32
T2	0	386
T4	30367	20
T5	0	64
T6	86172	16
T17	1754	0
T18	3064	0
T26	0	8
T30	3566	0
T31	2418	0
T32	0	6
T34	2929	0
T35	0	28
T36	0	2
T37	0	2
T39	2797	0
T40	4659	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T1,T5
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	262520022	23934	0	0
SrcPulseCheck_M	169868639	24354	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	262520022	23934
T1	90645	32
T2	0	373
T4	14577	5
T5	0	16
T6	44244	16
T17	842	0
T18	1471	0
T26	0	2
T30	1712	0
T31	1160	0
T32	0	6
T34	1406	0
T35	0	28
T36	0	2
T37	0	2
T39	1342	0
T40	2236	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169868639	24354
T1	92534	32
T2	0	373
T4	30367	10
T5	0	32
T6	84427	16
T17	1719	0
T18	3064	0
T26	0	4
T30	1782	0
T31	2320	0
T32	0	6
T34	702	0
T35	0	28
T36	0	2
T37	0	2
T39	1398	0
T40	2143	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	262520022	30158	0	0
SrcPulseCheck_M	169868639	30317	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	262520022	30158
T1	90645	32
T2	0	386
T4	14577	15
T5	0	54
T6	44244	16
T17	842	0
T18	1471	0
T26	0	8
T30	1712	0
T31	1160	0
T32	0	6
T34	1406	0
T35	0	28
T36	0	2
T37	0	2
T39	1342	0
T40	2236	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169868639	30317
T1	92534	32
T2	0	386
T4	30367	20
T5	0	64
T6	84427	16
T17	1719	0
T18	3064	0
T26	0	8
T30	1782	0
T31	2320	0
T32	0	6
T34	702	0
T35	0	28
T36	0	2
T37	0	2
T39	1398	0
T40	2143	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169868639	29972	0	0
SrcPulseCheck_M	262520022	30187	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169868639	29972
T1	92534	32
T2	0	386
T4	30367	15
T5	0	48
T6	84427	16
T17	1719	0
T18	3064	0
T26	0	7
T30	1782	0
T31	2320	0
T32	0	6
T34	702	0
T35	0	28
T36	0	2
T37	0	2
T39	1398	0
T40	2143	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	262520022	30187
T1	90645	32
T2	0	386
T4	14577	15
T5	0	61
T6	44244	16
T17	842	0
T18	1471	0
T26	0	8
T30	1712	0
T31	1160	0
T32	0	6
T34	1406	0
T35	0	28
T36	0	2
T37	0	2
T39	1342	0
T40	2236	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T68,T69,T71
1	0	Covered	T68,T69,T71
1	1	Covered	T68,T137

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T68,T69,T71
1	0	Covered	T68,T137
1	1	Covered	T68,T69,T71

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169868639	23	0	0
SrcPulseCheck_M	514851714	23	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169868639	23
T68	6011	2
T69	12108	1
T71	5640	1
T131	11621	2
T133	9915	1
T137	12195	2
T138	7818	1
T139	9851	2
T140	12263	2
T141	10144	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	514851714	23
T68	12023	2
T69	12234	1
T71	5640	1
T131	11500	2
T133	73216	1
T137	40370	2
T138	7984	1
T139	22516	2
T140	11772	2
T141	194769	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T67,T68,T69
1	0	Covered	T67,T68,T69
1	1	Covered	T68,T72,T138

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T67,T68,T69
1	0	Covered	T68,T72,T138
1	1	Covered	T67,T68,T69

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169868639	28	0	0
SrcPulseCheck_M	514851714	28	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169868639	28
T67	6525	1
T68	6011	3
T69	12108	1
T72	3576	3
T131	11621	1
T133	9915	1
T138	7818	2
T142	2373	1
T143	11271	1
T144	15212	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	514851714	28
T67	12528	1
T68	12023	3
T69	12234	1
T72	14303	3
T131	11500	1
T133	73216	1
T138	7984	2
T142	18985	1
T143	10819	1
T144	15212	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T67,T72,T73
1	0	Covered	T67,T72,T73
1	1	Covered	T132,T134,T145

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T67,T72,T73
1	0	Covered	T132,T134,T145
1	1	Covered	T67,T72,T73

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169868639	31	0	0
SrcPulseCheck_M	256551798	31	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169868639	31
T67	6525	1
T71	5640	1
T72	3576	2
T73	12724	2
T131	11621	2
T132	7291	2
T133	9915	2
T134	2838	3
T135	11248	1
T136	5655	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	256551798	31
T67	5958	1
T71	2415	1
T72	6744	2
T73	6625	2
T131	5006	2
T132	4169	2
T133	35853	2
T134	5667	3
T135	4811	1
T136	2257	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T67,T68,T69
1	0	Covered	T67,T68,T69
1	1	Covered	T68,T134,T146

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T67,T68,T69
1	0	Covered	T68,T134,T146
1	1	Covered	T67,T68,T69

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169868639	40	0	0
SrcPulseCheck_M	256551798	40	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169868639	40
T67	6525	1
T68	6011	3
T69	12108	1
T71	5640	2
T72	3576	2
T73	12724	2
T74	3451	1
T131	11621	2
T132	7291	1
T133	9915	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	256551798	40
T67	5958	1
T68	5337	3
T69	5293	1
T71	2415	2
T72	6744	2
T73	6625	2
T74	3055	1
T131	5006	2
T132	4169	1
T133	35853	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T67,T68,T69
1	0	Covered	T67,T68,T69
1	1	Covered	T73,T75,T131

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T67,T68,T69
1	0	Covered	T73,T75,T131
1	1	Covered	T67,T68,T69

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169868639	41	0	0
SrcPulseCheck_M	128275271	41	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169868639	41
T67	6525	1
T68	6011	1
T69	12108	1
T71	5640	2
T72	3576	1
T73	12724	4
T74	3451	2
T75	6186	2
T76	15434	1
T131	11621	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	128275271	41
T67	2981	1
T68	2668	1
T69	2649	1
T71	1209	2
T72	3372	1
T73	3311	4
T74	1528	2
T75	1332	2
T76	3396	1
T131	2505	4

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T67,T68,T69
1	0	Covered	T67,T68,T69
1	1	Covered	T74,T73,T131

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T67,T68,T69
1	0	Covered	T74,T73,T131
1	1	Covered	T67,T68,T69

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169868639	38	0	0
SrcPulseCheck_M	128275271	38	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169868639	38
T67	6525	1
T68	6011	1
T69	12108	1
T71	5640	1
T72	3576	1
T73	12724	3
T74	3451	2
T75	6186	1
T76	15434	1
T131	11621	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	128275271	38
T67	2981	1
T68	2668	1
T69	2649	1
T71	1209	1
T72	3372	1
T73	3311	3
T74	1528	2
T75	1332	1
T76	3396	1
T131	2505	2

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T68,T74,T73
1	0	Covered	T68,T74,T73
1	1	Covered	T74,T136,T147

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T68,T74,T73
1	0	Covered	T74,T136,T147
1	1	Covered	T68,T74,T73

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169868639	35	0	0
SrcPulseCheck_M	546877847	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169868639	35
T68	6011	1
T71	5640	1
T73	12724	3
T74	3451	3
T75	6186	1
T131	11621	2
T133	9915	1
T138	7818	1
T142	2373	1
T148	11449	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	546877847	35
T68	12524	1
T71	5876	1
T73	15330	3
T74	7190	3
T75	6186	1
T131	11980	2
T133	76269	1
T138	8317	1
T142	19778	1
T148	24889	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T68,T74,T73
1	0	Covered	T68,T74,T73
1	1	Covered	T74,T139,T149

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T68,T74,T73
1	0	Covered	T74,T139,T149
1	1	Covered	T68,T74,T73

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169868639	34	0	0
SrcPulseCheck_M	546877847	34	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169868639	34
T68	6011	2
T71	5640	1
T73	12724	1
T74	3451	3
T75	6186	1
T131	11621	2
T133	9915	1
T138	7818	1
T142	2373	1
T148	11449	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	546877847	34
T68	12524	2
T71	5876	1
T73	15330	1
T74	7190	3
T75	6186	1
T131	11980	2
T133	76269	1
T138	8317	1
T142	19778	1
T148	24889	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T68,T69,T76
1	0	Covered	T68,T69,T76
1	1	Covered	T69,T150

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T68,T69,T76
1	0	Covered	T69,T150
1	1	Covered	T68,T69,T76

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169868639	24	0	0
SrcPulseCheck_M	262520022	24	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169868639	24
T68	6011	2
T69	12108	4
T74	3451	1
T75	6186	1
T76	15434	1
T134	2838	1
T135	11248	1
T139	9851	2
T140	12263	1
T149	8915	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	262520022	24
T68	6011	2
T69	6118	4
T74	3451	1
T75	2969	1
T76	7717	1
T134	6192	1
T135	5566	1
T139	11258	2
T140	5886	1
T149	8229	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T68,T69,T76
1	0	Covered	T68,T69,T76
1	1	Covered	T68,T69,T75

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T68,T69,T76
1	0	Covered	T68,T69,T75
1	1	Covered	T68,T69,T76

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169868639	28	0	0
SrcPulseCheck_M	262520022	28	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169868639	28
T68	6011	3
T69	12108	4
T74	3451	1
T75	6186	2
T76	15434	1
T134	2838	2
T135	11248	5
T139	9851	2
T143	11271	1
T149	8915	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	262520022	28
T68	6011	3
T69	6118	4
T74	3451	1
T75	2969	2
T76	7717	1
T134	6192	2
T135	5566	5
T139	11258	2
T143	5410	1
T149	8229	1

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	512327016	95084	0	0
SrcPulseCheck_M	18559288	93403	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	512327016	95084
T1	181283	71
T2	0	1424
T3	0	57
T4	29152	0
T6	71203	82
T10	0	768
T17	1684	0
T18	2942	0
T30	3423	0
T31	2320	0
T32	0	18
T34	2812	0
T35	0	163
T36	0	6
T37	0	9
T38	0	350
T39	2685	0
T40	4472	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	18559288	93403
T1	392	71
T2	0	1425
T3	0	57
T4	70	0
T6	165	82
T10	0	768
T17	122	0
T18	214	0
T30	249	0
T31	169	0
T32	0	18
T34	204	0
T35	0	163
T36	0	6
T37	0	9
T38	0	350
T39	196	0
T40	325	0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	255334947	94039	0	0
SrcPulseCheck_M	18559288	92386	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	255334947	94039
T1	90588	71
T2	0	1424
T3	0	57
T4	7118	0
T6	35562	82
T10	0	768
T17	782	0
T18	1452	0
T30	1834	0
T31	1185	0
T32	0	18
T34	1366	0
T35	0	163
T36	0	6
T37	0	9
T38	0	349
T39	1330	0
T40	2412	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	18559288	92386
T1	392	71
T2	0	1425
T3	0	57
T4	70	0
T6	165	82
T10	0	768
T17	122	0
T18	214	0
T30	249	0
T31	169	0
T32	0	18
T34	204	0
T35	0	163
T36	0	6
T37	0	9
T38	0	349
T39	196	0
T40	325	0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	127666838	92648	0	0
SrcPulseCheck_M	18559288	91036	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	127666838	92648
T1	45294	71
T2	0	1420
T3	0	57
T4	3560	0
T6	17781	82
T10	0	768
T17	391	0
T18	726	0
T30	917	0
T31	592	0
T32	0	18
T34	683	0
T35	0	163
T36	0	6
T37	0	7
T38	0	348
T39	665	0
T40	1206	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	18559288	91036
T1	392	71
T2	0	1421
T3	0	57
T4	70	0
T6	165	82
T10	0	768
T17	122	0
T18	214	0
T30	249	0
T31	169	0
T32	0	18
T34	204	0
T35	0	163
T36	0	6
T37	0	7
T38	0	348
T39	196	0
T40	325	0

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	544247842	112011	0	0
SrcPulseCheck_M	19764948	111692	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	544247842	112011
T1	188842	71
T2	0	1816
T3	0	57
T4	30367	0
T6	86172	106
T10	0	924
T17	1754	0
T18	3064	0
T30	3566	0
T31	2418	0
T32	0	18
T34	2929	0
T35	0	187
T36	0	18
T37	0	18
T38	0	383
T39	2797	0
T40	4659	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	19764948	111692
T1	392	71
T2	0	1723
T3	0	57
T4	70	0
T6	189	106
T10	0	924
T17	122	0
T18	214	0
T30	249	0
T31	169	0
T32	0	18
T34	204	0
T35	0	187
T36	0	18
T37	0	18
T38	0	383
T39	196	0
T40	325	0

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	261257646	110572	0	0
SrcPulseCheck_M	19769215	110544	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	261257646	110572
T1	90645	71
T2	0	1711
T3	0	57
T4	14577	0
T6	44244	118
T10	0	972
T17	842	0
T18	1471	0
T30	1712	0
T31	1160	0
T32	0	18
T34	1406	0
T35	0	163
T36	0	17
T37	0	17
T38	0	406
T39	1342	0
T40	2236	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	19769215	110544
T1	392	71
T2	0	1712
T3	0	57
T4	70	0
T6	201	118
T10	0	972
T17	122	0
T18	214	0
T30	249	0
T31	169	0
T32	0	18
T34	204	0
T35	0	163
T36	0	17
T37	0	17
T38	0	406
T39	196	0
T40	325	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb