Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	169868639	5807306	0	0
clk_enables_rd_A	169868639	44656	0	0
clk_hints_rd_A	169868639	39804	0	0
extclk_ctrl_rd_A	169868639	48724	0	0
extclk_ctrl_regwen_rd_A	169868639	37337	0	0
jitter_enable_rd_A	169868639	55900	0	0
jitter_regwen_rd_A	169868639	42132	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169868639	5807306	0	0
T2	370973	106422	0	0
T10	0	85832	0	0
T12	0	99850	0	0
T13	0	31994	0	0
T32	14340	0	0	0
T35	78527	0	0	0
T36	2424	0	0	0
T37	1584	0	0	0
T38	0	85505	0	0
T41	1646	0	0	0
T42	1505	0	0	0
T43	1480	0	0	0
T44	1488	0	0	0
T45	2080	0	0	0
T77	0	158419	0	0
T78	0	215767	0	0
T79	0	261280	0	0
T80	0	76527	0	0
T81	0	64335	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169868639	44656	0	0
T2	370973	4409	0	0
T11	0	10	0	0
T13	0	1416	0	0
T32	14340	0	0	0
T35	78527	0	0	0
T36	2424	0	0	0
T37	1584	0	0	0
T38	0	3525	0	0
T41	1646	0	0	0
T42	1505	0	0	0
T43	1480	0	0	0
T44	1488	0	0	0
T45	2080	0	0	0
T151	0	1	0	0
T152	0	1887	0	0
T153	0	1	0	0
T154	0	13	0	0
T155	0	3	0	0
T156	0	4079	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169868639	39804	0	0
T2	370973	4063	0	0
T5	36486	0	0	0
T11	0	10	0	0
T13	0	1145	0	0
T19	2372	3	0	0
T20	2351	0	0	0
T21	2384	0	0	0
T22	2829	0	0	0
T23	11251	0	0	0
T24	1517	0	0	0
T25	1342	0	0	0
T26	5215	0	0	0
T38	0	2733	0	0
T151	0	4	0	0
T152	0	1713	0	0
T153	0	4	0	0
T154	0	14	0	0
T155	0	5	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169868639	48724	0	0
T2	0	4333	0	0
T4	30367	0	0	0
T6	84427	0	0	0
T11	0	47	0	0
T20	0	32	0	0
T27	2543	65	0	0
T28	2102	0	0	0
T29	2602	71	0	0
T30	1782	0	0	0
T31	2320	37	0	0
T34	702	0	0	0
T38	0	3521	0	0
T39	1398	0	0	0
T40	2143	0	0	0
T45	0	39	0	0
T157	0	27	0	0
T158	0	95	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169868639	37337	0	0
T2	370973	3757	0	0
T13	0	1185	0	0
T32	14340	0	0	0
T35	78527	0	0	0
T36	2424	0	0	0
T37	1584	0	0	0
T38	0	2884	0	0
T41	1646	0	0	0
T42	1505	0	0	0
T43	1480	0	0	0
T44	1488	0	0	0
T45	2080	0	0	0
T152	0	1532	0	0
T158	0	41	0	0
T159	0	42	0	0
T160	0	11	0	0
T161	0	42	0	0
T162	0	57	0	0
T163	0	40	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169868639	55900	0	0
T2	370973	5705	0	0
T5	36486	0	0	0
T11	0	204	0	0
T13	0	1795	0	0
T19	2372	105	0	0
T20	2351	0	0	0
T21	2384	0	0	0
T22	2829	0	0	0
T23	11251	0	0	0
T24	1517	92	0	0
T25	1342	0	0	0
T26	5215	0	0	0
T38	0	3806	0	0
T151	0	131	0	0
T152	0	2170	0	0
T153	0	127	0	0
T164	0	80	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169868639	42132	0	0
T2	370973	4515	0	0
T13	0	1236	0	0
T32	14340	0	0	0
T35	78527	0	0	0
T36	2424	0	0	0
T37	1584	0	0	0
T38	0	3298	0	0
T41	1646	0	0	0
T42	1505	0	0	0
T43	1480	0	0	0
T44	1488	0	0	0
T45	2080	0	0	0
T152	0	1968	0	0
T156	0	3876	0	0
T165	0	3558	0	0
T166	0	1065	0	0
T167	0	6269	0	0
T168	0	2999	0	0
T169	0	2709	0	0