Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T27,T28
1	1	Covered	T27,T28,T29

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	512327452	4580	0	0
g_div2.Div2Whole_A	512327452	5516	0	0
g_div4.Div4Stepped_A	255335328	4452	0	0
g_div4.Div4Whole_A	255335328	5178	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512327452	4580	0	0
T2	0	37	0	0
T4	29152	0	0	0
T6	71204	0	0	0
T20	0	4	0	0
T22	0	6	0	0
T23	0	11	0	0
T27	2627	4	0	0
T28	9175	10	0	0
T29	4997	8	0	0
T30	3424	4	0	0
T31	2321	4	0	0
T34	2812	0	0	0
T39	2686	0	0	0
T40	4473	6	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512327452	5516	0	0
T2	0	46	0	0
T4	29152	0	0	0
T6	71204	0	0	0
T20	0	6	0	0
T22	0	11	0	0
T23	0	11	0	0
T27	2627	6	0	0
T28	9175	13	0	0
T29	4997	10	0	0
T30	3424	8	0	0
T31	2321	7	0	0
T34	2812	0	0	0
T39	2686	0	0	0
T40	4473	8	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255335328	4452	0	0
T2	0	36	0	0
T4	7119	0	0	0
T6	35562	0	0	0
T20	0	4	0	0
T22	0	6	0	0
T23	0	11	0	0
T27	1344	1	0	0
T28	5100	9	0	0
T29	2689	8	0	0
T30	1835	4	0	0
T31	1185	4	0	0
T34	1367	0	0	0
T39	1331	0	0	0
T40	2412	6	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255335328	5178	0	0
T2	0	44	0	0
T4	7119	0	0	0
T6	35562	0	0	0
T20	0	6	0	0
T22	0	9	0	0
T23	0	11	0	0
T27	1344	6	0	0
T28	5100	13	0	0
T29	2689	10	0	0
T30	1835	8	0	0
T31	1185	6	0	0
T34	1367	0	0	0
T39	1331	0	0	0
T40	2412	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T27,T28
1	1	Covered	T27,T28,T29

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	512327452	4580	0	0
g_div2.Div2Whole_A	512327452	5516	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512327452	4580	0	0
T2	0	37	0	0
T4	29152	0	0	0
T6	71204	0	0	0
T20	0	4	0	0
T22	0	6	0	0
T23	0	11	0	0
T27	2627	4	0	0
T28	9175	10	0	0
T29	4997	8	0	0
T30	3424	4	0	0
T31	2321	4	0	0
T34	2812	0	0	0
T39	2686	0	0	0
T40	4473	6	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512327452	5516	0	0
T2	0	46	0	0
T4	29152	0	0	0
T6	71204	0	0	0
T20	0	6	0	0
T22	0	11	0	0
T23	0	11	0	0
T27	2627	6	0	0
T28	9175	13	0	0
T29	4997	10	0	0
T30	3424	8	0	0
T31	2321	7	0	0
T34	2812	0	0	0
T39	2686	0	0	0
T40	4473	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T27,T28
1	1	Covered	T27,T28,T29

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	255335328	4452	0	0
g_div4.Div4Whole_A	255335328	5178	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255335328	4452	0	0
T2	0	36	0	0
T4	7119	0	0	0
T6	35562	0	0	0
T20	0	4	0	0
T22	0	6	0	0
T23	0	11	0	0
T27	1344	1	0	0
T28	5100	9	0	0
T29	2689	8	0	0
T30	1835	4	0	0
T31	1185	4	0	0
T34	1367	0	0	0
T39	1331	0	0	0
T40	2412	6	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255335328	5178	0	0
T2	0	44	0	0
T4	7119	0	0	0
T6	35562	0	0	0
T20	0	6	0	0
T22	0	9	0	0
T23	0	11	0	0
T27	1344	6	0	0
T28	5100	13	0	0
T29	2689	10	0	0
T30	1835	8	0	0
T31	1185	6	0	0
T34	1367	0	0	0
T39	1331	0	0	0
T40	2412	8	0	0