Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T23,T5
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	50816	0	0
CgEnOn_A	2147483647	41190	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50816	0	0
T4	70197	18	0	0
T6	210718	3	0	0
T7	8360	3	0	0
T8	18945	9	0	0
T9	19284	8	0	0
T10	2101497	0	0	0
T11	1238287	0	0	0
T18	0	8	0	0
T27	7376	3	0	0
T28	26379	3	0	0
T29	14232	3	0	0
T30	9740	3	0	0
T31	6515	3	0	0
T34	2929	0	0	0
T38	1180792	0	0	0
T49	3471	25	0	0
T50	0	10	0	0
T51	0	15	0	0
T64	0	10	0	0
T78	0	5	0	0
T79	0	5	0	0
T83	82225	0	0	0
T96	98680	0	0	0
T97	5077	0	0	0
T98	10132	0	0	0
T99	4087	0	0	0
T100	11923	0	0	0
T170	0	20	0	0
T171	0	10	0	0
T172	0	20	0	0
T173	0	30	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41190	0	0
T1	317165	0	0	0
T2	0	480	0	0
T8	7107	6	0	0
T10	2101497	206	0	0
T11	1238287	94	0	0
T12	0	317	0	0
T17	2857	0	0	0
T18	5120	0	0	0
T19	3936	4	0	0
T20	4483	0	0	0
T21	4133	0	0	0
T22	4996	0	0	0
T23	0	123	0	0
T24	0	4	0	0
T34	7790	3	0	0
T38	1180792	278	0	0
T39	4680	0	0	0
T40	8090	0	0	0
T49	3471	40	0	0
T50	0	10	0	0
T51	0	15	0	0
T64	0	10	0	0
T78	0	4	0	0
T79	0	5	0	0
T83	82225	0	0	0
T96	98680	0	0	0
T97	5077	0	0	0
T98	10132	0	0	0
T99	4087	0	0	0
T100	11923	0	0	0
T170	0	20	0	0
T171	0	10	0	0
T172	0	20	0	0
T173	0	30	0	0
T174	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T23,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	255334947	164	0	0
CgEnOn_A	255334947	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255334947	164	0	0
T10	777917	0	0	0
T11	275187	0	0	0
T38	262484	0	0	0
T49	751	5	0	0
T50	0	2	0	0
T51	0	3	0	0
T64	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T83	10904	0	0	0
T96	15828	0	0	0
T97	1340	0	0	0
T98	2240	0	0	0
T99	887	0	0	0
T100	2626	0	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	4	0	0
T173	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255334947	164	0	0
T10	777917	0	0	0
T11	275187	0	0	0
T38	262484	0	0	0
T49	751	5	0	0
T50	0	2	0	0
T51	0	3	0	0
T64	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T83	10904	0	0	0
T96	15828	0	0	0
T97	1340	0	0	0
T98	2240	0	0	0
T99	887	0	0	0
T100	2626	0	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	4	0	0
T173	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T23,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	127666838	164	0	0
CgEnOn_A	127666838	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127666838	164	0	0
T10	388957	0	0	0
T11	137590	0	0	0
T38	131241	0	0	0
T49	375	5	0	0
T50	0	2	0	0
T51	0	3	0	0
T64	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T83	5450	0	0	0
T96	7915	0	0	0
T97	670	0	0	0
T98	1120	0	0	0
T99	444	0	0	0
T100	1313	0	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	4	0	0
T173	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127666838	164	0	0
T10	388957	0	0	0
T11	137590	0	0	0
T38	131241	0	0	0
T49	375	5	0	0
T50	0	2	0	0
T51	0	3	0	0
T64	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T83	5450	0	0	0
T96	7915	0	0	0
T97	670	0	0	0
T98	1120	0	0	0
T99	444	0	0	0
T100	1313	0	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	4	0	0
T173	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T23,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	512327016	164	0	0
CgEnOn_A	512327016	159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512327016	164	0	0
T10	156709	0	0	0
T11	550330	0	0	0
T38	524585	0	0	0
T49	1595	5	0	0
T50	0	2	0	0
T51	0	3	0	0
T64	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T83	54971	0	0	0
T96	59107	0	0	0
T97	1727	0	0	0
T98	4532	0	0	0
T99	1868	0	0	0
T100	5358	0	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	4	0	0
T173	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512327016	159	0	0
T10	156709	0	0	0
T11	550330	0	0	0
T38	524585	0	0	0
T49	1595	5	0	0
T50	0	2	0	0
T51	0	3	0	0
T64	0	2	0	0
T79	0	1	0	0
T83	54971	0	0	0
T96	59107	0	0	0
T97	1727	0	0	0
T98	4532	0	0	0
T99	1868	0	0	0
T100	5358	0	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	4	0	0
T173	0	6	0	0
T174	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T23,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	544247842	147	0	0
CgEnOn_A	544247842	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544247842	147	0	0
T2	377548	1	0	0
T32	32589	0	0	0
T35	152710	0	0	0
T36	17324	0	0	0
T37	26423	0	0	0
T41	32936	0	0	0
T42	15064	0	0	0
T43	1495	0	0	0
T44	4022	0	0	0
T45	4333	0	0	0
T49	0	3	0	0
T50	0	3	0	0
T51	0	4	0	0
T64	0	5	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	6	0	0
T173	0	5	0	0
T174	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544247842	146	0	0
T10	171044	0	0	0
T11	621279	0	0	0
T38	548260	0	0	0
T49	1558	3	0	0
T50	0	3	0	0
T51	0	4	0	0
T64	0	5	0	0
T83	57264	0	0	0
T96	61572	0	0	0
T97	1799	0	0	0
T98	4720	0	0	0
T99	1946	0	0	0
T100	5582	0	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	6	0	0
T173	0	5	0	0
T174	0	4	0	0
T175	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T23,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	127666838	164	0	0
CgEnOn_A	127666838	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127666838	164	0	0
T10	388957	0	0	0
T11	137590	0	0	0
T38	131241	0	0	0
T49	375	5	0	0
T50	0	2	0	0
T51	0	3	0	0
T64	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T83	5450	0	0	0
T96	7915	0	0	0
T97	670	0	0	0
T98	1120	0	0	0
T99	444	0	0	0
T100	1313	0	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	4	0	0
T173	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127666838	164	0	0
T10	388957	0	0	0
T11	137590	0	0	0
T38	131241	0	0	0
T49	375	5	0	0
T50	0	2	0	0
T51	0	3	0	0
T64	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T83	5450	0	0	0
T96	7915	0	0	0
T97	670	0	0	0
T98	1120	0	0	0
T99	444	0	0	0
T100	1313	0	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	4	0	0
T173	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T23,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	544247842	147	0	0
CgEnOn_A	544247842	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544247842	147	0	0
T2	377548	1	0	0
T32	32589	0	0	0
T35	152710	0	0	0
T36	17324	0	0	0
T37	26423	0	0	0
T41	32936	0	0	0
T42	15064	0	0	0
T43	1495	0	0	0
T44	4022	0	0	0
T45	4333	0	0	0
T49	0	3	0	0
T50	0	3	0	0
T51	0	4	0	0
T64	0	5	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	6	0	0
T173	0	5	0	0
T174	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544247842	146	0	0
T10	171044	0	0	0
T11	621279	0	0	0
T38	548260	0	0	0
T49	1558	3	0	0
T50	0	3	0	0
T51	0	4	0	0
T64	0	5	0	0
T83	57264	0	0	0
T96	61572	0	0	0
T97	1799	0	0	0
T98	4720	0	0	0
T99	1946	0	0	0
T100	5582	0	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	6	0	0
T173	0	5	0	0
T174	0	4	0	0
T175	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T23,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	127666838	164	0	0
CgEnOn_A	127666838	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127666838	164	0	0
T10	388957	0	0	0
T11	137590	0	0	0
T38	131241	0	0	0
T49	375	5	0	0
T50	0	2	0	0
T51	0	3	0	0
T64	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T83	5450	0	0	0
T96	7915	0	0	0
T97	670	0	0	0
T98	1120	0	0	0
T99	444	0	0	0
T100	1313	0	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	4	0	0
T173	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127666838	164	0	0
T10	388957	0	0	0
T11	137590	0	0	0
T38	131241	0	0	0
T49	375	5	0	0
T50	0	2	0	0
T51	0	3	0	0
T64	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T83	5450	0	0	0
T96	7915	0	0	0
T97	670	0	0	0
T98	1120	0	0	0
T99	444	0	0	0
T100	1313	0	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	4	0	0
T173	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T49,T50,T51
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	255334947	8402	0	0
CgEnOn_A	255334947	6001	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255334947	8402	0	0
T4	7118	6	0	0
T6	35562	1	0	0
T7	2366	1	0	0
T8	3344	1	0	0
T9	3445	1	0	0
T27	1344	1	0	0
T28	5099	1	0	0
T29	2689	1	0	0
T30	1834	1	0	0
T31	1185	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255334947	6001	0	0
T1	90588	0	0	0
T2	0	134	0	0
T10	0	71	0	0
T11	0	30	0	0
T12	0	104	0	0
T17	782	0	0	0
T18	1452	0	0	0
T19	1106	1	0	0
T20	1318	0	0	0
T21	1166	0	0	0
T22	1465	0	0	0
T23	0	35	0	0
T24	0	1	0	0
T34	1366	1	0	0
T38	0	95	0	0
T39	1330	0	0	0
T40	2412	0	0	0
T49	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T49,T50,T51
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	127666838	8297	0	0
CgEnOn_A	127666838	5896	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127666838	8297	0	0
T4	3560	6	0	0
T6	17781	1	0	0
T7	1183	1	0	0
T8	1672	1	0	0
T9	1722	1	0	0
T27	671	1	0	0
T28	2548	1	0	0
T29	1342	1	0	0
T30	917	1	0	0
T31	592	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127666838	5896	0	0
T1	45294	0	0	0
T2	0	135	0	0
T10	0	63	0	0
T11	0	33	0	0
T12	0	105	0	0
T17	391	0	0	0
T18	726	0	0	0
T19	553	1	0	0
T20	658	0	0	0
T21	583	0	0	0
T22	732	0	0	0
T23	0	34	0	0
T24	0	1	0	0
T34	683	1	0	0
T38	0	92	0	0
T39	665	0	0	0
T40	1206	0	0	0
T49	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T49,T50,T51
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	512327016	8378	0	0
CgEnOn_A	512327016	5972	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512327016	8378	0	0
T4	29152	6	0	0
T6	71203	1	0	0
T7	4811	1	0	0
T8	6822	1	0	0
T9	6914	1	0	0
T27	2626	1	0	0
T28	9175	1	0	0
T29	4996	1	0	0
T30	3423	1	0	0
T31	2320	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512327016	5972	0	0
T1	181283	0	0	0
T2	0	135	0	0
T10	0	72	0	0
T11	0	31	0	0
T12	0	108	0	0
T17	1684	0	0	0
T18	2942	0	0	0
T19	2277	1	0	0
T20	2507	0	0	0
T21	2384	0	0	0
T22	2799	0	0	0
T23	0	34	0	0
T24	0	1	0	0
T34	2812	1	0	0
T38	0	91	0	0
T39	2685	0	0	0
T40	4472	0	0	0
T49	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T49,T50,T52
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	261257646	8360	0	0
CgEnOn_A	261257646	5953	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261257646	8360	0	0
T4	14577	6	0	0
T6	44244	1	0	0
T7	2405	1	0	0
T8	3411	1	0	0
T9	3457	1	0	0
T27	1312	1	0	0
T28	4588	1	0	0
T29	2498	1	0	0
T30	1712	1	0	0
T31	1160	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261257646	5953	0	0
T1	90645	0	0	0
T2	0	128	0	0
T10	0	65	0	0
T11	0	30	0	0
T12	0	102	0	0
T17	842	0	0	0
T18	1471	0	0	0
T19	1138	1	0	0
T20	1254	0	0	0
T21	1192	0	0	0
T22	1399	0	0	0
T23	0	34	0	0
T24	0	1	0	0
T34	1406	1	0	0
T38	0	97	0	0
T39	1342	0	0	0
T40	2236	0	0	0
T49	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T23,T5
1	0	Covered	T8,T9,T18
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	544247842	4126	0	0
CgEnOn_A	544247842	4125	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544247842	4126	0	0
T2	0	77	0	0
T4	30367	0	0	0
T6	86172	0	0	0
T8	7107	6	0	0
T9	7203	5	0	0
T18	0	8	0	0
T19	0	1	0	0
T21	0	5	0	0
T23	0	20	0	0
T24	0	1	0	0
T27	2735	0	0	0
T28	9557	0	0	0
T29	5205	0	0	0
T30	3566	0	0	0
T31	2418	0	0	0
T34	2929	0	0	0
T41	0	4	0	0
T125	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544247842	4125	0	0
T2	0	76	0	0
T4	30367	0	0	0
T6	86172	0	0	0
T8	7107	6	0	0
T9	7203	5	0	0
T18	0	8	0	0
T19	0	1	0	0
T21	0	5	0	0
T23	0	20	0	0
T24	0	1	0	0
T27	2735	0	0	0
T28	9557	0	0	0
T29	5205	0	0	0
T30	3566	0	0	0
T31	2418	0	0	0
T34	2929	0	0	0
T41	0	4	0	0
T125	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T23,T5
1	0	Covered	T8,T9,T18
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	544247842	4071	0	0
CgEnOn_A	544247842	4070	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544247842	4071	0	0
T2	0	63	0	0
T4	30367	0	0	0
T6	86172	0	0	0
T8	7107	6	0	0
T9	7203	7	0	0
T18	0	13	0	0
T19	0	1	0	0
T21	0	5	0	0
T23	0	16	0	0
T24	0	1	0	0
T27	2735	0	0	0
T28	9557	0	0	0
T29	5205	0	0	0
T30	3566	0	0	0
T31	2418	0	0	0
T34	2929	0	0	0
T41	0	5	0	0
T125	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544247842	4070	0	0
T2	0	62	0	0
T4	30367	0	0	0
T6	86172	0	0	0
T8	7107	6	0	0
T9	7203	7	0	0
T18	0	13	0	0
T19	0	1	0	0
T21	0	5	0	0
T23	0	16	0	0
T24	0	1	0	0
T27	2735	0	0	0
T28	9557	0	0	0
T29	5205	0	0	0
T30	3566	0	0	0
T31	2418	0	0	0
T34	2929	0	0	0
T41	0	5	0	0
T125	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T23,T5
1	0	Covered	T8,T9,T18
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	544247842	4024	0	0
CgEnOn_A	544247842	4023	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544247842	4024	0	0
T2	0	65	0	0
T4	30367	0	0	0
T6	86172	0	0	0
T8	7107	8	0	0
T9	7203	8	0	0
T18	0	6	0	0
T19	0	1	0	0
T21	0	5	0	0
T23	0	16	0	0
T24	0	1	0	0
T27	2735	0	0	0
T28	9557	0	0	0
T29	5205	0	0	0
T30	3566	0	0	0
T31	2418	0	0	0
T34	2929	0	0	0
T41	0	3	0	0
T125	0	12	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544247842	4023	0	0
T2	0	64	0	0
T4	30367	0	0	0
T6	86172	0	0	0
T8	7107	8	0	0
T9	7203	8	0	0
T18	0	6	0	0
T19	0	1	0	0
T21	0	5	0	0
T23	0	16	0	0
T24	0	1	0	0
T27	2735	0	0	0
T28	9557	0	0	0
T29	5205	0	0	0
T30	3566	0	0	0
T31	2418	0	0	0
T34	2929	0	0	0
T41	0	3	0	0
T125	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T23,T5
1	0	Covered	T8,T9,T18
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	544247842	4044	0	0
CgEnOn_A	544247842	4043	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544247842	4044	0	0
T2	0	56	0	0
T4	30367	0	0	0
T6	86172	0	0	0
T8	7107	9	0	0
T9	7203	9	0	0
T18	0	9	0	0
T19	0	1	0	0
T21	0	4	0	0
T23	0	18	0	0
T24	0	1	0	0
T27	2735	0	0	0
T28	9557	0	0	0
T29	5205	0	0	0
T30	3566	0	0	0
T31	2418	0	0	0
T34	2929	0	0	0
T41	0	6	0	0
T125	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544247842	4043	0	0
T2	0	55	0	0
T4	30367	0	0	0
T6	86172	0	0	0
T8	7107	9	0	0
T9	7203	9	0	0
T18	0	9	0	0
T19	0	1	0	0
T21	0	4	0	0
T23	0	18	0	0
T24	0	1	0	0
T27	2735	0	0	0
T28	9557	0	0	0
T29	5205	0	0	0
T30	3566	0	0	0
T31	2418	0	0	0
T34	2929	0	0	0
T41	0	6	0	0
T125	0	7	0	0