Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T23,T24
0	1	Covered	T34,T23,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T19,T23
1	0	Covered	T49,T50,T52
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1156588067	15159	0	0
GateOpen_A	1156588067	15159	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1156588067	15159	0	0
T2	1550430	321	0	0
T5	161219	0	0	0
T10	0	181	0	0
T11	0	73	0	0
T12	0	264	0	0
T13	0	13	0	0
T19	5074	4	0	0
T20	5739	0	0	0
T21	5327	0	0	0
T22	6397	0	0	0
T23	97982	86	0	0
T24	15579	4	0	0
T25	2983	0	0	0
T26	40656	0	0	0
T38	0	234	0	0
T49	0	19	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1156588067	15159	0	0
T2	1550430	321	0	0
T5	161219	0	0	0
T10	0	181	0	0
T11	0	73	0	0
T12	0	264	0	0
T13	0	13	0	0
T19	5074	4	0	0
T20	5739	0	0	0
T21	5327	0	0	0
T22	6397	0	0	0
T23	97982	86	0	0
T24	15579	4	0	0
T25	2983	0	0	0
T26	40656	0	0	0
T38	0	234	0	0
T49	0	19	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T23,T24
0	1	Covered	T34,T23,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T19,T23
1	0	Covered	T49,T50,T51
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	127667251	3743	0	0
GateOpen_A	127667251	3743	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127667251	3743	0	0
T2	856861	80	0	0
T5	11027	0	0	0
T10	0	43	0	0
T11	0	20	0	0
T12	0	66	0	0
T13	0	3	0	0
T19	553	1	0	0
T20	659	0	0	0
T21	583	0	0	0
T22	732	0	0	0
T23	11056	22	0	0
T24	1725	1	0	0
T25	323	0	0	0
T26	3538	0	0	0
T38	0	60	0	0
T49	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127667251	3743	0	0
T2	856861	80	0	0
T5	11027	0	0	0
T10	0	43	0	0
T11	0	20	0	0
T12	0	66	0	0
T13	0	3	0	0
T19	553	1	0	0
T20	659	0	0	0
T21	583	0	0	0
T22	732	0	0	0
T23	11056	22	0	0
T24	1725	1	0	0
T25	323	0	0	0
T26	3538	0	0	0
T38	0	60	0	0
T49	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T23,T24
0	1	Covered	T34,T23,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T19,T23
1	0	Covered	T49,T50,T51
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	255335328	3783	0	0
GateOpen_A	255335328	3783	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255335328	3783	0	0
T2	171373	83	0	0
T5	22051	0	0	0
T10	0	46	0	0
T11	0	16	0	0
T12	0	64	0	0
T13	0	3	0	0
T19	1106	1	0	0
T20	1318	0	0	0
T21	1166	0	0	0
T22	1465	0	0	0
T23	22115	19	0	0
T24	3449	1	0	0
T25	645	0	0	0
T26	7075	0	0	0
T38	0	59	0	0
T49	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255335328	3783	0	0
T2	171373	83	0	0
T5	22051	0	0	0
T10	0	46	0	0
T11	0	16	0	0
T12	0	64	0	0
T13	0	3	0	0
T19	1106	1	0	0
T20	1318	0	0	0
T21	1166	0	0	0
T22	1465	0	0	0
T23	22115	19	0	0
T24	3449	1	0	0
T25	645	0	0	0
T26	7075	0	0	0
T38	0	59	0	0
T49	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T23,T24
0	1	Covered	T34,T23,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T19,T23
1	0	Covered	T49,T50,T51
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	512327452	3812	0	0
GateOpen_A	512327452	3812	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512327452	3812	0	0
T2	343325	81	0	0
T5	85426	0	0	0
T10	0	51	0	0
T11	0	20	0	0
T12	0	68	0	0
T13	0	4	0	0
T19	2277	1	0	0
T20	2508	0	0	0
T21	2385	0	0	0
T22	2800	0	0	0
T23	43207	22	0	0
T24	6936	1	0	0
T25	1343	0	0	0
T26	20028	0	0	0
T38	0	57	0	0
T49	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512327452	3812	0	0
T2	343325	81	0	0
T5	85426	0	0	0
T10	0	51	0	0
T11	0	20	0	0
T12	0	68	0	0
T13	0	4	0	0
T19	2277	1	0	0
T20	2508	0	0	0
T21	2385	0	0	0
T22	2800	0	0	0
T23	43207	22	0	0
T24	6936	1	0	0
T25	1343	0	0	0
T26	20028	0	0	0
T38	0	57	0	0
T49	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T23,T24
0	1	Covered	T34,T23,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T19,T23
1	0	Covered	T49,T50,T52
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	261258036	3821	0	0
GateOpen_A	261258036	3821	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261258036	3821	0	0
T2	178871	77	0	0
T5	42715	0	0	0
T10	0	41	0	0
T11	0	17	0	0
T12	0	66	0	0
T13	0	3	0	0
T19	1138	1	0	0
T20	1254	0	0	0
T21	1193	0	0	0
T22	1400	0	0	0
T23	21604	23	0	0
T24	3469	1	0	0
T25	672	0	0	0
T26	10015	0	0	0
T38	0	58	0	0
T49	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261258036	3821	0	0
T2	178871	77	0	0
T5	42715	0	0	0
T10	0	41	0	0
T11	0	17	0	0
T12	0	66	0	0
T13	0	3	0	0
T19	1138	1	0	0
T20	1254	0	0	0
T21	1193	0	0	0
T22	1400	0	0	0
T23	21604	23	0	0
T24	3469	1	0	0
T25	672	0	0	0
T26	10015	0	0	0
T38	0	58	0	0
T49	0	4	0	0