Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	671288	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4023136

1

T4

118

T5

9

T6

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1152000	1			T4	12		T5	13		T6	11
values[0x0]	1626417	1			T4	114		T5	15		T6	9
values[0x1]	1916007	1			T4	139		T5	12		T6	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	364262	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4330162

1

T4

158

T5

10

T6

17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17477	1			T4	13		T1	6		T2	392
valid_sources[0x01]	19578	1			T1	4		T2	386		T3	1
valid_sources[0x02]	19594	1			T4	5		T23	1		T2	417
valid_sources[0x03]	18926	1			T4	8		T1	2		T2	408
valid_sources[0x04]	19916	1			T4	1		T23	3		T2	388
valid_sources[0x05]	17928	1			T1	2		T2	406		T3	1
valid_sources[0x06]	18058	1			T1	6		T2	422		T3	3
valid_sources[0x07]	17787	1			T1	1		T2	343		T3	2
valid_sources[0x08]	18285	1			T4	5		T1	1		T2	384
valid_sources[0x09]	17866	1			T1	3		T2	352		T18	1
valid_sources[0x0a]	17483	1			T1	2		T2	390		T3	2
valid_sources[0x0b]	17932	1			T1	2		T2	411		T17	25
valid_sources[0x0c]	19084	1			T1	2		T2	387		T3	1
valid_sources[0x0d]	17204	1			T4	13		T1	1		T2	365
valid_sources[0x0e]	19146	1			T23	1		T1	4		T2	384
valid_sources[0x0f]	17302	1			T4	2		T22	1		T1	5
valid_sources[0x10]	18123	1			T1	3		T2	359		T9	4
valid_sources[0x11]	18996	1			T1	1		T2	413		T9	2
valid_sources[0x12]	18091	1			T23	1		T1	2		T2	389
valid_sources[0x13]	18528	1			T1	2		T2	431		T9	3
valid_sources[0x14]	19313	1			T23	1		T1	3		T2	392
valid_sources[0x15]	18919	1			T23	1		T1	4		T2	356
valid_sources[0x16]	18480	1			T5	8		T2	326		T9	5
valid_sources[0x17]	18470	1			T1	1		T2	391		T9	5
valid_sources[0x18]	18558	1			T1	1		T2	410		T9	6
valid_sources[0x19]	17155	1			T2	401		T3	2		T9	4
valid_sources[0x1a]	18521	1			T23	5		T1	5		T2	416
valid_sources[0x1b]	18410	1			T1	3		T2	371		T3	2
valid_sources[0x1c]	19104	1			T23	1		T1	2		T2	351
valid_sources[0x1d]	18481	1			T1	1		T2	359		T3	1
valid_sources[0x1e]	18275	1			T1	3		T2	404		T9	5
valid_sources[0x1f]	17242	1			T4	5		T1	2		T2	327
valid_sources[0x20]	18605	1			T2	380		T9	4		T10	64
valid_sources[0x21]	18610	1			T1	2		T2	414		T9	2
valid_sources[0x22]	17688	1			T4	6		T22	1		T1	2
valid_sources[0x23]	18559	1			T1	2		T2	403		T3	2
valid_sources[0x24]	18723	1			T1	2		T2	391		T18	1
valid_sources[0x25]	19005	1			T1	1		T2	374		T3	2
valid_sources[0x26]	18016	1			T2	381		T9	3		T10	86
valid_sources[0x27]	19062	1			T1	5		T2	410		T9	2
valid_sources[0x28]	17741	1			T4	4		T22	1		T1	4
valid_sources[0x29]	17925	1			T1	3		T2	367		T3	1
valid_sources[0x2a]	19017	1			T1	1		T2	423		T3	3
valid_sources[0x2b]	19276	1			T1	2		T2	374		T3	1
valid_sources[0x2c]	17807	1			T1	3		T2	462		T3	3
valid_sources[0x2d]	18903	1			T1	3		T2	382		T3	2
valid_sources[0x2e]	18145	1			T1	5		T2	392		T3	2
valid_sources[0x2f]	17669	1			T23	1		T1	4		T2	401
valid_sources[0x30]	18340	1			T4	6		T1	4		T2	407
valid_sources[0x31]	18611	1			T2	384		T3	2		T9	1
valid_sources[0x32]	18243	1			T5	4		T2	397		T3	2
valid_sources[0x33]	19431	1			T1	1		T2	374		T3	2
valid_sources[0x34]	18940	1			T1	1		T2	405		T9	2
valid_sources[0x35]	18209	1			T4	10		T1	1		T2	376
valid_sources[0x36]	18089	1			T23	2		T1	5		T2	428
valid_sources[0x37]	18559	1			T1	3		T2	400		T9	2
valid_sources[0x38]	18403	1			T1	3		T2	393		T3	2
valid_sources[0x39]	17981	1			T1	2		T2	353		T9	3
valid_sources[0x3a]	16356	1			T1	2		T2	370		T18	11
valid_sources[0x3b]	18476	1			T23	6		T2	410		T3	1
valid_sources[0x3c]	17792	1			T1	1		T2	399		T18	2
valid_sources[0x3d]	18921	1			T23	2		T1	4		T2	406
valid_sources[0x3e]	18690	1			T4	29		T1	3		T2	385
valid_sources[0x3f]	18999	1			T1	2		T2	389		T3	3
valid_sources[0x40]	17819	1			T1	3		T2	394		T3	2
valid_sources[0x41]	18495	1			T23	4		T1	3		T2	376
valid_sources[0x42]	17778	1			T2	387		T3	1		T9	7
valid_sources[0x43]	17897	1			T1	1		T2	352		T3	4
valid_sources[0x44]	18017	1			T23	1		T1	2		T2	360
valid_sources[0x45]	16804	1			T1	2		T2	394		T9	3
valid_sources[0x46]	18318	1			T4	4		T1	4		T2	378
valid_sources[0x47]	18497	1			T22	1		T23	2		T1	2
valid_sources[0x48]	18256	1			T1	2		T2	372		T9	2
valid_sources[0x49]	17335	1			T1	1		T2	358		T3	1
valid_sources[0x4a]	18751	1			T23	1		T1	3		T2	395
valid_sources[0x4b]	20632	1			T25	13		T1	5		T2	354
valid_sources[0x4c]	19531	1			T1	5		T2	354		T9	3
valid_sources[0x4d]	18129	1			T1	1		T2	381		T3	1
valid_sources[0x4e]	18221	1			T1	3		T2	421		T18	1
valid_sources[0x4f]	18426	1			T1	3		T2	378		T3	4
valid_sources[0x50]	17857	1			T1	3		T2	355		T3	1
valid_sources[0x51]	20152	1			T1	7		T2	422		T9	2
valid_sources[0x52]	17229	1			T23	1		T1	6		T2	381
valid_sources[0x53]	17822	1			T1	3		T2	374		T3	2
valid_sources[0x54]	17921	1			T2	426		T3	3		T9	5
valid_sources[0x55]	17907	1			T1	2		T2	364		T3	3
valid_sources[0x56]	19235	1			T4	8		T5	2		T2	394
valid_sources[0x57]	18245	1			T1	1		T2	395		T3	3
valid_sources[0x58]	18212	1			T2	389		T9	4		T10	160
valid_sources[0x59]	16753	1			T23	2		T1	5		T2	360
valid_sources[0x5a]	17688	1			T1	4		T2	380		T3	1
valid_sources[0x5b]	19569	1			T1	6		T2	432		T3	5
valid_sources[0x5c]	18483	1			T4	10		T23	2		T1	5
valid_sources[0x5d]	17816	1			T23	1		T1	1		T2	355
valid_sources[0x5e]	17476	1			T1	2		T2	402		T9	2
valid_sources[0x5f]	19547	1			T1	1		T2	432		T3	1
valid_sources[0x60]	17530	1			T4	1		T1	2		T2	398
valid_sources[0x61]	19206	1			T1	2		T2	391		T9	2
valid_sources[0x62]	18325	1			T22	1		T1	1		T2	365
valid_sources[0x63]	18347	1			T1	1		T2	378		T9	2
valid_sources[0x64]	18873	1			T5	13		T23	2		T2	360
valid_sources[0x65]	16480	1			T1	3		T2	392		T3	1
valid_sources[0x66]	18528	1			T1	3		T2	360		T3	4
valid_sources[0x67]	19238	1			T1	3		T2	385		T3	2
valid_sources[0x68]	20841	1			T1	6		T2	427		T3	1
valid_sources[0x69]	17854	1			T1	1		T2	377		T9	3
valid_sources[0x6a]	19075	1			T1	1		T2	387		T9	6
valid_sources[0x6b]	18067	1			T5	1		T1	5		T2	414
valid_sources[0x6c]	18345	1			T1	1		T2	392		T3	2
valid_sources[0x6d]	18668	1			T1	3		T2	409		T3	1
valid_sources[0x6e]	17630	1			T1	4		T2	439		T3	3
valid_sources[0x6f]	18102	1			T23	3		T1	3		T2	424
valid_sources[0x70]	18790	1			T23	2		T1	1		T2	346
valid_sources[0x71]	17817	1			T2	397		T3	2		T9	2
valid_sources[0x72]	17360	1			T1	2		T2	370		T3	2
valid_sources[0x73]	17576	1			T1	2		T2	394		T3	2
valid_sources[0x74]	19538	1			T1	1		T2	384		T9	4
valid_sources[0x75]	18217	1			T23	1		T1	4		T2	389
valid_sources[0x76]	17260	1			T23	2		T1	7		T2	378
valid_sources[0x77]	18110	1			T1	5		T2	436		T3	2
valid_sources[0x78]	17623	1			T1	1		T2	397		T9	6
valid_sources[0x79]	18381	1			T5	1		T1	2		T2	365
valid_sources[0x7a]	20651	1			T4	1		T1	1		T2	436
valid_sources[0x7b]	18198	1			T4	7		T23	1		T1	3
valid_sources[0x7c]	18225	1			T1	5		T2	368		T3	1
valid_sources[0x7d]	18094	1			T1	2		T2	423		T9	6
valid_sources[0x7e]	18774	1			T5	10		T1	2		T2	393
valid_sources[0x7f]	18615	1			T1	2		T2	403		T3	1
valid_sources[0x80]	18581	1			T4	1		T1	3		T2	410

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1015103

1

T4

5

T5

6

T6

6

values[0x0]

all_enables

biggest_size

1528300

1

T4

68

T5

2

T6

5

values[0x1]

all_enables

biggest_size

1479733

1

T4

45

T5

1

T6

2