Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_peri_cg_wrap::peri_cg

Group : clkmgr_env_pkg::clkmgr_peri_cg_wrap::peri_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
PeriDiv2	100.00	1	100	1	64	64
PeriDiv4	100.00	1	100	1	64	64
PeriIo	100.00	1	100	1	64	64
PeriUsb	100.00	1	100	1	64	64

---

Group Instance : PeriDiv2

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance PeriDiv2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	0	6	100.00

Variables for Group Instance PeriDiv2

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_enable_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance PeriDiv2

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
peri_cross	6	0	6	100.00	100	1	1	0

---

Group Instance : PeriDiv4

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance PeriDiv4

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	0	6	100.00

Variables for Group Instance PeriDiv4

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_enable_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance PeriDiv4

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
peri_cross	6	0	6	100.00	100	1	1	0

---

Group Instance : PeriIo

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance PeriIo

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	0	6	100.00

Variables for Group Instance PeriIo

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_enable_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance PeriIo

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
peri_cross	6	0	6	100.00	100	1	1	0

---

Group Instance : PeriUsb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance PeriUsb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	0	6	100.00

Variables for Group Instance PeriUsb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_enable_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance PeriUsb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
peri_cross	6	0	6	100.00	100	1	1	0

Summary for Variable csr_enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

306687

1

T4

2

T5

2

T6

2

auto[1]

244323898

1

T4

47056

T5

1751

T6

3587

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8854

1

T4

2

T5

2

T6

2

auto[1]

244621731

1

T4

47056

T5

1751

T6

3587

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

134553988

1

T4

47053

T5

1568

T6

3441

auto[1]

110076597

1

T4

5

T5

185

T6

148

---

Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	0	6	100.00
Automatically Generated Cross Bins	6	0	6	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for peri_cross

Bins

csr_enable_cp

ip_clk_en_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

5298

1

T5

2

T6

2

T24

2

auto[0]

auto[0]

auto[1]

1550

1

T4

2

T21

2

T22

2

auto[0]

auto[1]

auto[0]

225941

1

T1

23

T16

2

T2

1065

auto[0]

auto[1]

auto[1]

73898

1

T1

15

T2

897

T9

92

auto[1]

auto[1]

auto[0]

134320743

1

T4

47053

T5

1566

T6

3439

auto[1]

auto[1]

auto[1]

110001149

1

T4

3

T5

185

T6

148

User Defined Cross Bins for peri_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_enable_off	0	Excluded

Summary for Variable csr_enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

159901

1

T4

2

T5

2

T6

2

auto[1]

122153392

1

T4

23527

T5

871

T6

1789

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7859

1

T4

2

T5

2

T6

2

auto[1]

122305434

1

T4

23527

T5

871

T6

1789

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67274982

1

T4

23526

T5

781

T6

1717

auto[1]

55038311

1

T4

3

T5

92

T6

74

---

Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	0	6	100.00
Automatically Generated Cross Bins	6	0	6	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for peri_cross

Bins

csr_enable_cp

ip_clk_en_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

5300

1

T5

2

T6

2

T24

2

auto[0]

auto[0]

auto[1]

1548

1

T4

2

T21

2

T22

2

auto[0]

auto[1]

auto[0]

115812

1

T1

9

T16

1

T2

469

auto[0]

auto[1]

auto[1]

37241

1

T1

9

T2

517

T9

50

auto[1]

auto[1]

auto[0]

67152859

1

T4

23526

T5

779

T6

1715

auto[1]

auto[1]

auto[1]

54999522

1

T4

1

T5

92

T6

74

User Defined Cross Bins for peri_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_enable_off	0	Excluded

Summary for Variable csr_enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

676319

1

T4

2

T5

2

T6

2

auto[1]

487956572

1

T4

94114

T5

3229

T6

6661

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10858

1

T4

2

T5

2

T6

2

auto[1]

488622033

1

T4

94114

T5

3229

T6

6661

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

268479718

1

T4

94105

T5

2862

T6

6367

auto[1]

220153173

1

T4

11

T5

369

T6

296

---

Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	0	6	100.00
Automatically Generated Cross Bins	6	0	6	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for peri_cross

Bins

csr_enable_cp

ip_clk_en_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

5298

1

T5

2

T6

2

T24

2

auto[0]

auto[0]

auto[1]

1550

1

T4

2

T21

2

T22

2

auto[0]

auto[1]

auto[0]

519399

1

T1

46

T16

5

T2

2050

auto[0]

auto[1]

auto[1]

150072

1

T1

29

T2

1998

T9

185

auto[1]

auto[1]

auto[0]

267951011

1

T4

94105

T5

2860

T6

6365

auto[1]

auto[1]

auto[1]

220001551

1

T4

9

T5

369

T6

296

User Defined Cross Bins for peri_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_enable_off	0	Excluded

Summary for Variable csr_enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

305165

1

T4

2

T5

2

T6

2

auto[1]

249862002

1

T4

70099

T5

1613

T6

3329

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8452

1

T4

2

T5

2

T6

2

auto[1]

250158715

1

T4

70099

T5

1613

T6

3329

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137958579

1

T4

70095

T5

1428

T6

3183

auto[1]

112208588

1

T4

6

T5

187

T6

148

---

Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	0	6	100.00
Automatically Generated Cross Bins	6	0	6	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for peri_cross

Bins

csr_enable_cp

ip_clk_en_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

5298

1

T5

2

T6

2

T24

2

auto[0]

auto[0]

auto[1]

1550

1

T4

2

T21

2

T22

2

auto[0]

auto[1]

auto[0]

224982

1

T1

29

T16

3

T2

1001

auto[0]

auto[1]

auto[1]

73335

1

T1

10

T2

980

T9

95

auto[1]

auto[1]

auto[0]

137726695

1

T4

70095

T5

1426

T6

3181

auto[1]

auto[1]

auto[1]

112133703

1

T4

4

T5

187

T6

148

User Defined Cross Bins for peri_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_enable_off	0	Excluded