Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T24,T1,T16
0	1	Covered	T1,T2,T9
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T2
1	0	Covered	T24,T39,T40
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1109348100	14614	0	0
GateOpen_A	1109348100	14614	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109348100	14614	0	0
T1	479273	11	0	0
T2	1703364	375	0	0
T3	251997	0	0	0
T9	346727	53	0	0
T10	1444344	31	0	0
T11	0	12	0	0
T12	0	335	0	0
T16	4685	4	0	0
T17	13762	0	0	0
T18	4248	0	0	0
T24	4912	18	0	0
T25	10544	0	0	0
T39	0	7	0	0
T181	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109348100	14614	0	0
T1	479273	11	0	0
T2	1703364	375	0	0
T3	251997	0	0	0
T9	346727	53	0	0
T10	1444344	31	0	0
T11	0	12	0	0
T12	0	335	0	0
T16	4685	4	0	0
T17	13762	0	0	0
T18	4248	0	0	0
T24	4912	18	0	0
T25	10544	0	0	0
T39	0	7	0	0
T181	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T24,T1,T16
0	1	Covered	T1,T2,T9
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T2
1	0	Covered	T24,T39,T40
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	122328828	3623	0	0
GateOpen_A	122328828	3623	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122328828	3623	0	0
T1	52143	3	0	0
T2	940565	91	0	0
T3	27987	0	0	0
T9	38590	12	0	0
T10	159910	8	0	0
T11	0	3	0	0
T12	0	81	0	0
T16	508	1	0	0
T17	1558	0	0	0
T18	471	0	0	0
T24	521	5	0	0
T25	1232	0	0	0
T39	0	2	0	0
T181	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122328828	3623	0	0
T1	52143	3	0	0
T2	940565	91	0	0
T3	27987	0	0	0
T9	38590	12	0	0
T10	159910	8	0	0
T11	0	3	0	0
T12	0	81	0	0
T16	508	1	0	0
T17	1558	0	0	0
T18	471	0	0	0
T24	521	5	0	0
T25	1232	0	0	0
T39	0	2	0	0
T181	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T24,T1,T16
0	1	Covered	T1,T2,T9
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T2
1	0	Covered	T24,T39,T40
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	244658620	3660	0	0
GateOpen_A	244658620	3660	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244658620	3660	0	0
T1	104291	3	0	0
T2	188116	94	0	0
T3	55973	0	0	0
T9	77183	12	0	0
T10	319825	8	0	0
T11	0	3	0	0
T12	0	82	0	0
T16	1015	1	0	0
T17	3116	0	0	0
T18	942	0	0	0
T24	1041	5	0	0
T25	2464	0	0	0
T39	0	2	0	0
T181	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244658620	3660	0	0
T1	104291	3	0	0
T2	188116	94	0	0
T3	55973	0	0	0
T9	77183	12	0	0
T10	319825	8	0	0
T11	0	3	0	0
T12	0	82	0	0
T16	1015	1	0	0
T17	3116	0	0	0
T18	942	0	0	0
T24	1041	5	0	0
T25	2464	0	0	0
T39	0	2	0	0
T181	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T24,T1,T16
0	1	Covered	T1,T2,T9
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T2
1	0	Covered	T24,T39,T40
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	490999074	3658	0	0
GateOpen_A	490999074	3658	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490999074	3658	0	0
T1	205623	3	0	0
T2	376396	94	0	0
T3	112023	0	0	0
T9	153967	15	0	0
T10	644983	8	0	0
T11	0	3	0	0
T12	0	88	0	0
T16	2108	1	0	0
T17	6058	0	0	0
T18	1890	0	0	0
T24	2174	5	0	0
T25	4565	0	0	0
T39	0	2	0	0
T181	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490999074	3658	0	0
T1	205623	3	0	0
T2	376396	94	0	0
T3	112023	0	0	0
T9	153967	15	0	0
T10	644983	8	0	0
T11	0	3	0	0
T12	0	88	0	0
T16	2108	1	0	0
T17	6058	0	0	0
T18	1890	0	0	0
T24	2174	5	0	0
T25	4565	0	0	0
T39	0	2	0	0
T181	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T24,T1,T16
0	1	Covered	T1,T2,T9
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T2
1	0	Covered	T24,T39,T40
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	251361578	3673	0	0
GateOpen_A	251361578	3673	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	251361578	3673	0	0
T1	117216	2	0	0
T2	198287	96	0	0
T3	56014	0	0	0
T9	76987	14	0	0
T10	319626	7	0	0
T11	0	3	0	0
T12	0	84	0	0
T16	1054	1	0	0
T17	3030	0	0	0
T18	945	0	0	0
T24	1176	3	0	0
T25	2283	0	0	0
T39	0	1	0	0
T181	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	251361578	3673	0	0
T1	117216	2	0	0
T2	198287	96	0	0
T3	56014	0	0	0
T9	76987	14	0	0
T10	319626	7	0	0
T11	0	3	0	0
T12	0	84	0	0
T16	1054	1	0	0
T17	3030	0	0	0
T18	945	0	0	0
T24	1176	3	0	0
T25	2283	0	0	0
T39	0	1	0	0
T181	0	1	0	0