Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	848162580	75764	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	848162580	75764	0	0
T1	237680	44	0	0
T2	2034615	1513	0	0
T3	280070	216	0	0
T9	761865	222	0	0
T10	3359385	408	0	0
T11	0	905	0	0
T12	0	1365	0	0
T13	0	122	0	0
T14	0	492	0	0
T15	0	855	0	0
T16	10760	0	0	0
T17	7570	0	0	0
T18	9650	0	0	0
T19	179210	0	0	0
T20	8980	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169632516	11177	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169632516	11177	0	0
T1	47536	7	0	0
T2	406923	222	0	0
T3	56014	30	0	0
T9	152373	30	0	0
T10	671877	52	0	0
T11	0	133	0	0
T12	0	177	0	0
T13	0	17	0	0
T14	0	65	0	0
T15	0	115	0	0
T16	2152	0	0	0
T17	1514	0	0	0
T18	1930	0	0	0
T19	35842	0	0	0
T20	1796	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169632516	15230	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169632516	15230	0	0
T1	47536	9	0	0
T2	406923	308	0	0
T3	56014	42	0	0
T9	152373	46	0	0
T10	671877	80	0	0
T11	0	180	0	0
T12	0	268	0	0
T13	0	24	0	0
T14	0	99	0	0
T15	0	170	0	0
T16	2152	0	0	0
T17	1514	0	0	0
T18	1930	0	0	0
T19	35842	0	0	0
T20	1796	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169632516	23079	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169632516	23079	0	0
T1	47536	12	0	0
T2	406923	502	0	0
T3	56014	66	0	0
T9	152373	72	0	0
T10	671877	136	0	0
T11	0	302	0	0
T12	0	447	0	0
T13	0	39	0	0
T14	0	163	0	0
T15	0	275	0	0
T16	2152	0	0	0
T17	1514	0	0	0
T18	1930	0	0	0
T19	35842	0	0	0
T20	1796	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169632516	11044	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169632516	11044	0	0
T1	47536	7	0	0
T2	406923	187	0	0
T3	56014	30	0	0
T9	152373	29	0	0
T10	671877	59	0	0
T11	0	112	0	0
T12	0	199	0	0
T13	0	17	0	0
T14	0	64	0	0
T15	0	118	0	0
T16	2152	0	0	0
T17	1514	0	0	0
T18	1930	0	0	0
T19	35842	0	0	0
T20	1796	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169632516	15234	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169632516	15234	0	0
T1	47536	9	0	0
T2	406923	294	0	0
T3	56014	48	0	0
T9	152373	45	0	0
T10	671877	81	0	0
T11	0	178	0	0
T12	0	274	0	0
T13	0	25	0	0
T14	0	101	0	0
T15	0	177	0	0
T16	2152	0	0	0
T17	1514	0	0	0
T18	1930	0	0	0
T19	35842	0	0	0
T20	1796	0	0	0