Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T9

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	169632516	166741789	0	0
AllClkBypReqTrue_A	169632516	138688	0	0
IoClkBypReqFalse_A	169632516	166653759	0	2415
IoClkBypReqTrue_A	169632516	222122	0	0
LcClkBypAckFalse_A	169632516	166750764	0	0
LcClkBypAckTrue_A	169632516	129713	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169632516	166741789	0	0
T1	47536	46907	0	0
T4	144762	144580	0	0
T5	1774	1493	0	0
T6	1622	1467	0	0
T16	2152	1972	0	0
T21	838	804	0	0
T22	891	765	0	0
T23	3423	3316	0	0
T24	1219	1130	0	0
T25	1188	1114	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169632516	138688	0	0
T1	47536	501	0	0
T2	406923	3445	0	0
T5	1774	156	0	0
T6	1622	129	0	0
T9	0	785	0	0
T10	0	656	0	0
T16	2152	0	0	0
T17	0	61	0	0
T18	0	99	0	0
T21	838	0	0	0
T22	891	75	0	0
T23	3423	0	0	0
T24	1219	0	0	0
T25	1188	38	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169632516	166653759	0	2415
T1	47536	46530	0	3
T4	144762	144578	0	3
T5	1774	1420	0	3
T6	1622	1572	0	3
T16	2152	1970	0	3
T21	838	802	0	3
T22	891	752	0	3
T23	3423	3314	0	3
T24	1219	1128	0	3
T25	1188	1025	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169632516	222122	0	0
T1	47536	870	0	0
T2	406923	5032	0	0
T5	1774	227	0	0
T6	1622	22	0	0
T9	0	947	0	0
T10	0	937	0	0
T16	2152	0	0	0
T18	0	237	0	0
T20	0	141	0	0
T21	838	0	0	0
T22	891	86	0	0
T23	3423	0	0	0
T24	1219	0	0	0
T25	1188	125	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169632516	166750764	0	0
T1	47536	46862	0	0
T4	144762	144580	0	0
T5	1774	1523	0	0
T6	1622	1578	0	0
T16	2152	1972	0	0
T21	838	804	0	0
T22	891	773	0	0
T23	3423	3316	0	0
T24	1219	1130	0	0
T25	1188	1039	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169632516	129713	0	0
T1	47536	546	0	0
T2	406923	2849	0	0
T5	1774	126	0	0
T6	1622	18	0	0
T9	0	706	0	0
T10	0	574	0	0
T16	2152	0	0	0
T18	0	100	0	0
T20	0	88	0	0
T21	838	0	0	0
T22	891	67	0	0
T23	3423	0	0	0
T24	1219	0	0	0
T25	1188	113	0	0