Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2094437808	16415	0	0
TransStop_A	2094437808	8255	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2094437808	16415	0	0
T1	952788	4	0	0
T2	1658104	238	0	0
T3	466776	0	0	0
T9	617548	83	0	0
T10	0	68	0	0
T11	0	71	0	0
T12	0	191	0	0
T16	8788	4	0	0
T17	25244	0	0	0
T18	7876	0	0	0
T23	23608	36	0	0
T24	9736	0	0	0
T25	19024	0	0	0
T28	0	7	0	0
T128	0	45	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2094437808	8255	0	0
T1	952788	4	0	0
T2	1658104	111	0	0
T3	466776	0	0	0
T9	617548	47	0	0
T10	0	44	0	0
T11	0	37	0	0
T12	0	95	0	0
T16	8788	4	0	0
T17	25244	0	0	0
T18	7876	0	0	0
T23	23608	23	0	0
T24	9736	0	0	0
T25	19024	0	0	0
T28	0	5	0	0
T128	0	34	0	0
T129	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	523609452	4141	0	0
TransStop_A	523609452	2068	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523609452	4141	0	0
T1	238197	1	0	0
T2	414526	63	0	0
T3	116694	0	0	0
T9	154387	20	0	0
T10	0	19	0	0
T11	0	20	0	0
T12	0	42	0	0
T16	2197	1	0	0
T17	6311	0	0	0
T18	1969	0	0	0
T23	5902	10	0	0
T24	2434	0	0	0
T25	4756	0	0	0
T28	0	2	0	0
T128	0	12	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523609452	2068	0	0
T1	238197	1	0	0
T2	414526	29	0	0
T3	116694	0	0	0
T9	154387	11	0	0
T10	0	11	0	0
T11	0	9	0	0
T12	0	17	0	0
T16	2197	1	0	0
T17	6311	0	0	0
T18	1969	0	0	0
T23	5902	5	0	0
T24	2434	0	0	0
T25	4756	0	0	0
T28	0	2	0	0
T128	0	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	523609452	4036	0	0
TransStop_A	523609452	2052	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523609452	4036	0	0
T1	238197	1	0	0
T2	414526	56	0	0
T3	116694	0	0	0
T9	154387	23	0	0
T10	0	16	0	0
T11	0	15	0	0
T12	0	48	0	0
T16	2197	1	0	0
T17	6311	0	0	0
T18	1969	0	0	0
T23	5902	6	0	0
T24	2434	0	0	0
T25	4756	0	0	0
T28	0	2	0	0
T128	0	13	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523609452	2052	0	0
T1	238197	1	0	0
T2	414526	26	0	0
T3	116694	0	0	0
T9	154387	13	0	0
T10	0	11	0	0
T11	0	9	0	0
T12	0	23	0	0
T16	2197	1	0	0
T17	6311	0	0	0
T18	1969	0	0	0
T23	5902	5	0	0
T24	2434	0	0	0
T25	4756	0	0	0
T28	0	2	0	0
T128	0	10	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	523609452	4027	0	0
TransStop_A	523609452	2025	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523609452	4027	0	0
T1	238197	1	0	0
T2	414526	65	0	0
T3	116694	0	0	0
T9	154387	23	0	0
T10	0	16	0	0
T11	0	20	0	0
T12	0	45	0	0
T16	2197	1	0	0
T17	6311	0	0	0
T18	1969	0	0	0
T23	5902	8	0	0
T24	2434	0	0	0
T25	4756	0	0	0
T28	0	1	0	0
T128	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523609452	2025	0	0
T1	238197	1	0	0
T2	414526	31	0	0
T3	116694	0	0	0
T9	154387	11	0	0
T10	0	9	0	0
T11	0	11	0	0
T12	0	27	0	0
T16	2197	1	0	0
T17	6311	0	0	0
T18	1969	0	0	0
T23	5902	5	0	0
T24	2434	0	0	0
T25	4756	0	0	0
T128	0	7	0	0
T129	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	523609452	4211	0	0
TransStop_A	523609452	2110	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523609452	4211	0	0
T1	238197	1	0	0
T2	414526	54	0	0
T3	116694	0	0	0
T9	154387	17	0	0
T10	0	17	0	0
T11	0	16	0	0
T12	0	56	0	0
T16	2197	1	0	0
T17	6311	0	0	0
T18	1969	0	0	0
T23	5902	12	0	0
T24	2434	0	0	0
T25	4756	0	0	0
T28	0	2	0	0
T128	0	11	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523609452	2110	0	0
T1	238197	1	0	0
T2	414526	25	0	0
T3	116694	0	0	0
T9	154387	12	0	0
T10	0	13	0	0
T11	0	8	0	0
T12	0	28	0	0
T16	2197	1	0	0
T17	6311	0	0	0
T18	1969	0	0	0
T23	5902	8	0	0
T24	2434	0	0	0
T25	4756	0	0	0
T28	0	1	0	0
T128	0	8	0	0