Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	169632516	20428565	0	58

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169632516	20428565	0	58
T1	47536	2787	0	0
T2	406923	175947	0	0
T3	56014	18339	0	1
T9	152373	24557	0	1
T10	671877	46551	0	0
T11	0	106388	0	0
T12	0	149543	0	0
T13	0	12498	0	1
T14	0	58775	0	0
T15	0	98206	0	0
T16	2152	0	0	0
T17	1514	0	0	0
T18	1930	0	0	0
T19	35842	0	0	0
T20	1796	0	0	0
T26	0	0	0	1
T130	0	0	0	1
T131	0	0	0	1
T132	0	0	0	1
T133	0	0	0	1
T134	0	0	0	1
T135	0	0	0	1