Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	170498765	5908616	0	0
clk_enables_rd_A	170498765	52296	0	0
clk_hints_rd_A	170498765	45051	0	0
extclk_ctrl_rd_A	170498765	58507	0	0
extclk_ctrl_regwen_rd_A	170498765	44465	0	0
jitter_enable_rd_A	170498765	65082	0	0
jitter_regwen_rd_A	170498765	48833	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170498765	5908616	0	0
T2	406923	140127	0	0
T3	56014	0	0	0
T9	152373	0	0	0
T10	671877	33906	0	0
T12	0	120976	0	0
T15	0	36646	0	0
T17	1514	0	0	0
T18	1930	0	0	0
T19	35842	0	0	0
T20	1796	0	0	0
T27	0	252009	0	0
T28	1461	0	0	0
T29	1524	0	0	0
T33	0	92945	0	0
T76	0	209948	0	0
T77	0	85030	0	0
T78	0	86568	0	0
T79	0	59139	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170498765	52296	0	0
T9	152373	16	0	0
T10	671877	0	0	0
T11	447579	0	0	0
T12	249364	0	0	0
T15	0	875	0	0
T19	35842	0	0	0
T20	1796	0	0	0
T28	1461	0	0	0
T29	1524	0	0	0
T30	1806	0	0	0
T77	0	3413	0	0
T78	0	1766	0	0
T134	0	7	0	0
T149	0	11	0	0
T150	0	1	0	0
T151	0	6	0	0
T152	0	3	0	0
T153	0	2206	0	0
T154	1550	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170498765	45051	0	0
T9	152373	15	0	0
T10	671877	0	0	0
T11	447579	15	0	0
T12	249364	0	0	0
T15	0	694	0	0
T19	35842	0	0	0
T20	1796	0	0	0
T28	1461	0	0	0
T29	1524	0	0	0
T30	1806	0	0	0
T77	0	3074	0	0
T78	0	1484	0	0
T149	0	13	0	0
T150	0	4	0	0
T151	0	1	0	0
T154	1550	0	0	0
T155	0	1	0	0
T156	0	4	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170498765	58507	0	0
T3	56014	0	0	0
T9	152373	105	0	0
T10	671877	0	0	0
T11	0	25	0	0
T15	0	905	0	0
T17	1514	25	0	0
T18	1930	0	0	0
T19	35842	0	0	0
T20	1796	0	0	0
T28	1461	0	0	0
T29	1524	25	0	0
T154	1550	0	0	0
T157	0	37	0	0
T158	0	72	0	0
T159	0	25	0	0
T160	0	4	0	0
T161	0	12	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170498765	44465	0	0
T15	116609	731	0	0
T35	1279	0	0	0
T36	872	0	0	0
T43	0	3	0	0
T49	0	1800	0	0
T77	0	3129	0	0
T78	0	1484	0	0
T81	1852	0	0	0
T91	24823	0	0	0
T112	0	20	0	0
T153	0	1665	0	0
T161	1280	0	0	0
T162	0	43	0	0
T163	0	7	0	0
T164	0	863	0	0
T165	1761	0	0	0
T166	963	0	0	0
T167	1449	0	0	0
T168	2293	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170498765	65082	0	0
T9	152373	308	0	0
T10	671877	0	0	0
T11	447579	184	0	0
T12	249364	0	0	0
T15	0	786	0	0
T19	35842	0	0	0
T20	1796	0	0	0
T28	1461	0	0	0
T29	1524	0	0	0
T30	1806	0	0	0
T77	0	4632	0	0
T149	0	215	0	0
T150	0	95	0	0
T151	0	73	0	0
T154	1550	0	0	0
T155	0	40	0	0
T156	0	81	0	0
T165	0	33	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170498765	48833	0	0
T15	116609	896	0	0
T35	1279	0	0	0
T36	872	0	0	0
T49	0	1855	0	0
T77	0	3400	0	0
T78	0	1635	0	0
T81	1852	0	0	0
T91	24823	0	0	0
T153	0	1986	0	0
T161	1280	0	0	0
T164	0	931	0	0
T165	1761	0	0	0
T166	963	0	0	0
T167	1449	0	0	0
T168	2293	0	0	0
T169	0	1567	0	0
T170	0	3386	0	0
T171	0	548	0	0
T172	0	5757	0	0