Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T6,T22

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	490999074	4658	0	0
g_div2.Div2Whole_A	490999074	5545	0	0
g_div4.Div4Stepped_A	244658620	4567	0	0
g_div4.Div4Whole_A	244658620	5270	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490999074	4658	0	0
T1	205623	24	0	0
T2	376396	89	0	0
T5	3476	5	0	0
T6	6771	7	0	0
T9	0	19	0	0
T10	0	19	0	0
T16	2108	0	0	0
T17	0	3	0	0
T18	0	1	0	0
T21	3662	0	0	0
T22	2852	2	0	0
T23	5666	0	0	0
T24	2174	0	0	0
T25	4565	3	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490999074	5545	0	0
T1	205623	26	0	0
T2	376396	125	0	0
T5	3476	7	0	0
T6	6771	7	0	0
T9	0	23	0	0
T10	0	23	0	0
T16	2108	0	0	0
T17	0	3	0	0
T18	0	8	0	0
T21	3662	0	0	0
T22	2852	2	0	0
T23	5666	0	0	0
T24	2174	0	0	0
T25	4565	3	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244658620	4567	0	0
T1	104291	24	0	0
T2	188116	86	0	0
T5	1820	5	0	0
T6	3619	7	0	0
T9	0	19	0	0
T10	0	17	0	0
T16	1015	0	0	0
T17	0	3	0	0
T18	0	1	0	0
T21	1785	0	0	0
T22	1514	2	0	0
T23	2773	0	0	0
T24	1041	0	0	0
T25	2464	3	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244658620	5270	0	0
T1	104291	26	0	0
T2	188116	109	0	0
T5	1820	7	0	0
T6	3619	7	0	0
T9	0	21	0	0
T10	0	17	0	0
T16	1015	0	0	0
T17	0	3	0	0
T18	0	6	0	0
T21	1785	0	0	0
T22	1514	2	0	0
T23	2773	0	0	0
T24	1041	0	0	0
T25	2464	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T6,T22

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	490999074	4658	0	0
g_div2.Div2Whole_A	490999074	5545	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490999074	4658	0	0
T1	205623	24	0	0
T2	376396	89	0	0
T5	3476	5	0	0
T6	6771	7	0	0
T9	0	19	0	0
T10	0	19	0	0
T16	2108	0	0	0
T17	0	3	0	0
T18	0	1	0	0
T21	3662	0	0	0
T22	2852	2	0	0
T23	5666	0	0	0
T24	2174	0	0	0
T25	4565	3	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490999074	5545	0	0
T1	205623	26	0	0
T2	376396	125	0	0
T5	3476	7	0	0
T6	6771	7	0	0
T9	0	23	0	0
T10	0	23	0	0
T16	2108	0	0	0
T17	0	3	0	0
T18	0	8	0	0
T21	3662	0	0	0
T22	2852	2	0	0
T23	5666	0	0	0
T24	2174	0	0	0
T25	4565	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T6,T22

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	244658620	4567	0	0
g_div4.Div4Whole_A	244658620	5270	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244658620	4567	0	0
T1	104291	24	0	0
T2	188116	86	0	0
T5	1820	5	0	0
T6	3619	7	0	0
T9	0	19	0	0
T10	0	17	0	0
T16	1015	0	0	0
T17	0	3	0	0
T18	0	1	0	0
T21	1785	0	0	0
T22	1514	2	0	0
T23	2773	0	0	0
T24	1041	0	0	0
T25	2464	3	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244658620	5270	0	0
T1	104291	26	0	0
T2	188116	109	0	0
T5	1820	7	0	0
T6	3619	7	0	0
T9	0	21	0	0
T10	0	17	0	0
T16	1015	0	0	0
T17	0	3	0	0
T18	0	6	0	0
T21	1785	0	0	0
T22	1514	2	0	0
T23	2773	0	0	0
T24	1041	0	0	0
T25	2464	3	0	0