Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T1,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	50293	0	0
CgEnOn_A	2147483647	41087	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50293	0	0
T1	2374790	23	0	0
T2	5873356	64	0	0
T3	952117	0	0	0
T4	235110	3	0	0
T5	7941	3	0	0
T6	15581	3	0	0
T9	1273237	20	0	0
T10	2776288	0	0	0
T16	22502	6	0	0
T17	51707	0	0	0
T18	16054	0	0	0
T21	8168	3	0	0
T22	6546	3	0	0
T23	36263	13	0	0
T24	24286	47	0	0
T25	49798	3	0	0
T39	0	10	0	0
T40	0	25	0	0
T173	0	20	0	0
T174	0	25	0	0
T175	0	30	0	0
T176	0	15	0	0
T177	0	25	0	0
T178	0	10	0	0
T179	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41087	0	0
T1	2374790	11	0	0
T2	7576719	512	0	0
T3	1204112	0	0	0
T9	1619961	78	0	0
T10	4220630	56	0	0
T11	0	28	0	0
T12	0	412	0	0
T16	22502	3	0	0
T17	65467	0	0	0
T18	20298	0	0	0
T23	23608	10	0	0
T24	24286	44	0	0
T25	49798	0	0	0
T28	0	2	0	0
T39	0	16	0	0
T40	0	25	0	0
T173	0	20	0	0
T174	0	25	0	0
T175	0	30	0	0
T176	0	15	0	0
T177	0	25	0	0
T178	0	10	0	0
T179	0	15	0	0
T181	0	8	0	0
T182	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T1,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	244658226	166	0	0
CgEnOn_A	244658226	166	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244658226	166	0	0
T1	104291	0	0	0
T2	188115	0	0	0
T3	55972	0	0	0
T9	77182	0	0	0
T10	319825	0	0	0
T16	1014	0	0	0
T17	3115	0	0	0
T18	941	0	0	0
T24	1040	5	0	0
T25	2463	0	0	0
T39	0	2	0	0
T40	0	5	0	0
T173	0	4	0	0
T174	0	5	0	0
T175	0	6	0	0
T176	0	3	0	0
T177	0	5	0	0
T178	0	2	0	0
T179	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244658226	166	0	0
T1	104291	0	0	0
T2	188115	0	0	0
T3	55972	0	0	0
T9	77182	0	0	0
T10	319825	0	0	0
T16	1014	0	0	0
T17	3115	0	0	0
T18	941	0	0	0
T24	1040	5	0	0
T25	2463	0	0	0
T39	0	2	0	0
T40	0	5	0	0
T173	0	4	0	0
T174	0	5	0	0
T175	0	6	0	0
T176	0	3	0	0
T177	0	5	0	0
T178	0	2	0	0
T179	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T1,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	122328416	166	0	0
CgEnOn_A	122328416	166	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122328416	166	0	0
T1	52143	0	0	0
T2	940565	0	0	0
T3	27986	0	0	0
T9	38589	0	0	0
T10	159909	0	0	0
T16	507	0	0	0
T17	1558	0	0	0
T18	470	0	0	0
T24	520	5	0	0
T25	1231	0	0	0
T39	0	2	0	0
T40	0	5	0	0
T173	0	4	0	0
T174	0	5	0	0
T175	0	6	0	0
T176	0	3	0	0
T177	0	5	0	0
T178	0	2	0	0
T179	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122328416	166	0	0
T1	52143	0	0	0
T2	940565	0	0	0
T3	27986	0	0	0
T9	38589	0	0	0
T10	159909	0	0	0
T16	507	0	0	0
T17	1558	0	0	0
T18	470	0	0	0
T24	520	5	0	0
T25	1231	0	0	0
T39	0	2	0	0
T40	0	5	0	0
T173	0	4	0	0
T174	0	5	0	0
T175	0	6	0	0
T176	0	3	0	0
T177	0	5	0	0
T178	0	2	0	0
T179	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T1,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	490998608	166	0	0
CgEnOn_A	490998608	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490998608	166	0	0
T1	205622	0	0	0
T2	376396	0	0	0
T3	112023	0	0	0
T9	153966	0	0	0
T10	644982	0	0	0
T16	2108	0	0	0
T17	6058	0	0	0
T18	1889	0	0	0
T24	2173	5	0	0
T25	4565	0	0	0
T39	0	2	0	0
T40	0	5	0	0
T173	0	4	0	0
T174	0	5	0	0
T175	0	6	0	0
T176	0	3	0	0
T177	0	5	0	0
T178	0	2	0	0
T179	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490998608	163	0	0
T1	205622	0	0	0
T2	376396	0	0	0
T3	112023	0	0	0
T9	153966	0	0	0
T10	644982	0	0	0
T16	2108	0	0	0
T17	6058	0	0	0
T18	1889	0	0	0
T24	2173	5	0	0
T25	4565	0	0	0
T39	0	2	0	0
T40	0	5	0	0
T173	0	4	0	0
T174	0	5	0	0
T175	0	6	0	0
T176	0	3	0	0
T177	0	5	0	0
T178	0	2	0	0
T179	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T1,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	523609009	169	0	0
CgEnOn_A	523609009	166	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523609009	169	0	0
T1	238196	0	0	0
T2	414525	1	0	0
T3	116694	0	0	0
T9	154387	0	0	0
T10	665877	0	0	0
T16	2196	0	0	0
T17	6310	0	0	0
T18	1969	0	0	0
T24	2434	4	0	0
T25	4756	0	0	0
T39	0	2	0	0
T40	0	4	0	0
T77	0	1	0	0
T173	0	4	0	0
T174	0	4	0	0
T175	0	6	0	0
T176	0	3	0	0
T180	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523609009	166	0	0
T1	238196	0	0	0
T2	414525	1	0	0
T3	116694	0	0	0
T9	154387	0	0	0
T10	665877	0	0	0
T16	2196	0	0	0
T17	6310	0	0	0
T18	1969	0	0	0
T24	2434	4	0	0
T25	4756	0	0	0
T39	0	2	0	0
T40	0	4	0	0
T173	0	4	0	0
T174	0	4	0	0
T175	0	6	0	0
T176	0	3	0	0
T177	0	3	0	0
T180	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T1,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	122328416	166	0	0
CgEnOn_A	122328416	166	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122328416	166	0	0
T1	52143	0	0	0
T2	940565	0	0	0
T3	27986	0	0	0
T9	38589	0	0	0
T10	159909	0	0	0
T16	507	0	0	0
T17	1558	0	0	0
T18	470	0	0	0
T24	520	5	0	0
T25	1231	0	0	0
T39	0	2	0	0
T40	0	5	0	0
T173	0	4	0	0
T174	0	5	0	0
T175	0	6	0	0
T176	0	3	0	0
T177	0	5	0	0
T178	0	2	0	0
T179	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122328416	166	0	0
T1	52143	0	0	0
T2	940565	0	0	0
T3	27986	0	0	0
T9	38589	0	0	0
T10	159909	0	0	0
T16	507	0	0	0
T17	1558	0	0	0
T18	470	0	0	0
T24	520	5	0	0
T25	1231	0	0	0
T39	0	2	0	0
T40	0	5	0	0
T173	0	4	0	0
T174	0	5	0	0
T175	0	6	0	0
T176	0	3	0	0
T177	0	5	0	0
T178	0	2	0	0
T179	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T1,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	523609009	169	0	0
CgEnOn_A	523609009	166	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523609009	169	0	0
T1	238196	0	0	0
T2	414525	1	0	0
T3	116694	0	0	0
T9	154387	0	0	0
T10	665877	0	0	0
T16	2196	0	0	0
T17	6310	0	0	0
T18	1969	0	0	0
T24	2434	4	0	0
T25	4756	0	0	0
T39	0	2	0	0
T40	0	4	0	0
T77	0	1	0	0
T173	0	4	0	0
T174	0	4	0	0
T175	0	6	0	0
T176	0	3	0	0
T180	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523609009	166	0	0
T1	238196	0	0	0
T2	414525	1	0	0
T3	116694	0	0	0
T9	154387	0	0	0
T10	665877	0	0	0
T16	2196	0	0	0
T17	6310	0	0	0
T18	1969	0	0	0
T24	2434	4	0	0
T25	4756	0	0	0
T39	0	2	0	0
T40	0	4	0	0
T173	0	4	0	0
T174	0	4	0	0
T175	0	6	0	0
T176	0	3	0	0
T177	0	3	0	0
T180	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T1,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	122328416	166	0	0
CgEnOn_A	122328416	166	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122328416	166	0	0
T1	52143	0	0	0
T2	940565	0	0	0
T3	27986	0	0	0
T9	38589	0	0	0
T10	159909	0	0	0
T16	507	0	0	0
T17	1558	0	0	0
T18	470	0	0	0
T24	520	5	0	0
T25	1231	0	0	0
T39	0	2	0	0
T40	0	5	0	0
T173	0	4	0	0
T174	0	5	0	0
T175	0	6	0	0
T176	0	3	0	0
T177	0	5	0	0
T178	0	2	0	0
T179	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122328416	166	0	0
T1	52143	0	0	0
T2	940565	0	0	0
T3	27986	0	0	0
T9	38589	0	0	0
T10	159909	0	0	0
T16	507	0	0	0
T17	1558	0	0	0
T18	470	0	0	0
T24	520	5	0	0
T25	1231	0	0	0
T39	0	2	0	0
T40	0	5	0	0
T173	0	4	0	0
T174	0	5	0	0
T175	0	6	0	0
T176	0	3	0	0
T177	0	5	0	0
T178	0	2	0	0
T179	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T39,T40
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	244658226	8059	0	0
CgEnOn_A	244658226	5764	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244658226	8059	0	0
T1	104291	7	0	0
T4	47086	1	0	0
T5	1820	1	0	0
T6	3618	1	0	0
T16	1014	2	0	0
T21	1784	1	0	0
T22	1513	1	0	0
T23	2772	1	0	0
T24	1040	6	0	0
T25	2463	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244658226	5764	0	0
T1	104291	3	0	0
T2	188115	150	0	0
T3	55972	0	0	0
T9	77182	19	0	0
T10	319825	12	0	0
T11	0	3	0	0
T12	0	123	0	0
T16	1014	1	0	0
T17	3115	0	0	0
T18	941	0	0	0
T24	1040	5	0	0
T25	2463	0	0	0
T39	0	2	0	0
T181	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T39,T40
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	122328416	7932	0	0
CgEnOn_A	122328416	5637	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122328416	7932	0	0
T1	52143	7	0	0
T4	23543	1	0	0
T5	908	1	0	0
T6	1808	1	0	0
T16	507	1	0	0
T21	892	1	0	0
T22	757	1	0	0
T23	1386	1	0	0
T24	520	6	0	0
T25	1231	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122328416	5637	0	0
T1	52143	3	0	0
T2	940565	148	0	0
T3	27986	0	0	0
T9	38589	18	0	0
T10	159909	12	0	0
T11	0	2	0	0
T12	0	119	0	0
T16	507	0	0	0
T17	1558	0	0	0
T18	470	0	0	0
T24	520	5	0	0
T25	1231	0	0	0
T39	0	2	0	0
T181	0	2	0	0
T182	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T39,T40
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	490998608	8017	0	0
CgEnOn_A	490998608	5719	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490998608	8017	0	0
T1	205622	8	0	0
T4	94292	1	0	0
T5	3476	1	0	0
T6	6770	1	0	0
T16	2108	2	0	0
T21	3662	1	0	0
T22	2851	1	0	0
T23	5665	1	0	0
T24	2173	6	0	0
T25	4565	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490998608	5719	0	0
T1	205622	4	0	0
T2	376396	150	0	0
T3	112023	0	0	0
T9	153966	21	0	0
T10	644982	13	0	0
T11	0	3	0	0
T12	0	128	0	0
T16	2108	1	0	0
T17	6058	0	0	0
T18	1889	0	0	0
T24	2173	5	0	0
T25	4565	0	0	0
T39	0	2	0	0
T181	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T39,T40
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	251361123	8026	0	0
CgEnOn_A	251361123	5729	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	251361123	8026	0	0
T1	117216	7	0	0
T4	70189	1	0	0
T5	1737	1	0	0
T6	3385	1	0	0
T16	1054	2	0	0
T21	1830	1	0	0
T22	1425	1	0	0
T23	2832	1	0	0
T24	1176	4	0	0
T25	2282	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	251361123	5729	0	0
T1	117216	3	0	0
T2	198287	144	0	0
T3	56014	0	0	0
T9	76987	22	0	0
T10	319626	10	0	0
T11	0	3	0	0
T12	0	126	0	0
T16	1054	1	0	0
T17	3029	0	0	0
T18	944	0	0	0
T24	1176	3	0	0
T25	2282	0	0	0
T39	0	1	0	0
T181	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T1,T2
1	0	Covered	T23,T1,T16
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	523609009	4310	0	0
CgEnOn_A	523609009	4307	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523609009	4310	0	0
T1	238196	1	0	0
T2	414525	64	0	0
T3	116694	0	0	0
T9	154387	20	0	0
T10	0	19	0	0
T11	0	20	0	0
T12	0	42	0	0
T16	2196	1	0	0
T17	6310	0	0	0
T18	1969	0	0	0
T23	5902	10	0	0
T24	2434	4	0	0
T25	4756	0	0	0
T28	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523609009	4307	0	0
T1	238196	1	0	0
T2	414525	64	0	0
T3	116694	0	0	0
T9	154387	20	0	0
T10	0	19	0	0
T11	0	20	0	0
T12	0	42	0	0
T16	2196	1	0	0
T17	6310	0	0	0
T18	1969	0	0	0
T23	5902	10	0	0
T24	2434	4	0	0
T25	4756	0	0	0
T28	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T1,T2
1	0	Covered	T23,T1,T16
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	523609009	4205	0	0
CgEnOn_A	523609009	4202	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523609009	4205	0	0
T1	238196	1	0	0
T2	414525	57	0	0
T3	116694	0	0	0
T9	154387	23	0	0
T10	0	16	0	0
T11	0	15	0	0
T12	0	48	0	0
T16	2196	1	0	0
T17	6310	0	0	0
T18	1969	0	0	0
T23	5902	6	0	0
T24	2434	4	0	0
T25	4756	0	0	0
T28	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523609009	4202	0	0
T1	238196	1	0	0
T2	414525	57	0	0
T3	116694	0	0	0
T9	154387	23	0	0
T10	0	16	0	0
T11	0	15	0	0
T12	0	48	0	0
T16	2196	1	0	0
T17	6310	0	0	0
T18	1969	0	0	0
T23	5902	6	0	0
T24	2434	4	0	0
T25	4756	0	0	0
T28	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T1,T2
1	0	Covered	T23,T1,T16
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	523609009	4196	0	0
CgEnOn_A	523609009	4193	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523609009	4196	0	0
T1	238196	1	0	0
T2	414525	66	0	0
T3	116694	0	0	0
T9	154387	23	0	0
T10	0	16	0	0
T11	0	20	0	0
T12	0	45	0	0
T16	2196	1	0	0
T17	6310	0	0	0
T18	1969	0	0	0
T23	5902	8	0	0
T24	2434	4	0	0
T25	4756	0	0	0
T28	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523609009	4193	0	0
T1	238196	1	0	0
T2	414525	66	0	0
T3	116694	0	0	0
T9	154387	23	0	0
T10	0	16	0	0
T11	0	20	0	0
T12	0	45	0	0
T16	2196	1	0	0
T17	6310	0	0	0
T18	1969	0	0	0
T23	5902	8	0	0
T24	2434	4	0	0
T25	4756	0	0	0
T28	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T1,T2
1	0	Covered	T23,T1,T16
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	523609009	4380	0	0
CgEnOn_A	523609009	4377	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523609009	4380	0	0
T1	238196	1	0	0
T2	414525	55	0	0
T3	116694	0	0	0
T9	154387	17	0	0
T10	0	17	0	0
T11	0	16	0	0
T12	0	56	0	0
T16	2196	1	0	0
T17	6310	0	0	0
T18	1969	0	0	0
T23	5902	12	0	0
T24	2434	4	0	0
T25	4756	0	0	0
T28	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523609009	4377	0	0
T1	238196	1	0	0
T2	414525	55	0	0
T3	116694	0	0	0
T9	154387	17	0	0
T10	0	17	0	0
T11	0	16	0	0
T12	0	56	0	0
T16	2196	1	0	0
T17	6310	0	0	0
T18	1969	0	0	0
T23	5902	12	0	0
T24	2434	4	0	0
T25	4756	0	0	0
T28	0	2	0	0