Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	624330	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3520682

1

T7

21

T8

4

T9

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1017073	1			T7	40		T8	3		T9	1
values[0x0]	1438020	1			T7	21		T8	5		T9	1
values[0x1]	1689919	1			T7	20		T8	2		T9	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	347183	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3797829

1

T7

27

T8

5

T9

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16145	1			T1	712		T20	3		T3	234
valid_sources[0x01]	14329	1			T4	3		T1	630		T2	5
valid_sources[0x02]	18450	1			T1	677		T5	10		T3	219
valid_sources[0x03]	16392	1			T6	1		T1	652		T22	1
valid_sources[0x04]	15935	1			T1	748		T5	1		T3	232
valid_sources[0x05]	16007	1			T6	1		T1	661		T22	1
valid_sources[0x06]	15280	1			T7	3		T4	1		T1	713
valid_sources[0x07]	17047	1			T6	1		T1	693		T22	2
valid_sources[0x08]	16163	1			T6	1		T4	1		T1	646
valid_sources[0x09]	16459	1			T6	1		T4	3		T26	1
valid_sources[0x0a]	14703	1			T6	2		T1	712		T19	30
valid_sources[0x0b]	17023	1			T4	5		T1	615		T5	3
valid_sources[0x0c]	16722	1			T1	612		T22	4		T5	2
valid_sources[0x0d]	14633	1			T6	2		T1	667		T22	2
valid_sources[0x0e]	17032	1			T6	1		T1	693		T22	2
valid_sources[0x0f]	18103	1			T1	669		T22	3		T23	2
valid_sources[0x10]	17692	1			T4	1		T1	679		T5	4
valid_sources[0x11]	17077	1			T4	2		T1	727		T22	2
valid_sources[0x12]	16208	1			T4	4		T1	678		T23	1
valid_sources[0x13]	18432	1			T1	627		T22	1		T5	5
valid_sources[0x14]	14927	1			T1	653		T22	1		T5	4
valid_sources[0x15]	16356	1			T1	686		T20	1		T5	3
valid_sources[0x16]	16218	1			T7	4		T6	1		T4	1
valid_sources[0x17]	16018	1			T7	11		T6	1		T4	2
valid_sources[0x18]	17179	1			T4	2		T1	721		T22	2
valid_sources[0x19]	16790	1			T4	5		T1	755		T20	1
valid_sources[0x1a]	18524	1			T1	680		T22	1		T5	6
valid_sources[0x1b]	16418	1			T6	2		T1	744		T5	2
valid_sources[0x1c]	16309	1			T4	1		T1	611		T22	2
valid_sources[0x1d]	15152	1			T1	668		T22	2		T5	2
valid_sources[0x1e]	15738	1			T4	1		T1	726		T5	4
valid_sources[0x1f]	16041	1			T1	627		T5	2		T3	235
valid_sources[0x20]	16922	1			T1	617		T5	4		T2	3
valid_sources[0x21]	16323	1			T8	1		T4	2		T1	686
valid_sources[0x22]	16869	1			T4	1		T1	677		T23	1
valid_sources[0x23]	14324	1			T4	1		T1	678		T22	1
valid_sources[0x24]	17344	1			T1	681		T22	1		T5	3
valid_sources[0x25]	16146	1			T6	2		T1	657		T23	2
valid_sources[0x26]	17752	1			T1	614		T20	4		T22	3
valid_sources[0x27]	17332	1			T6	1		T1	644		T5	2
valid_sources[0x28]	16288	1			T9	2		T6	1		T1	607
valid_sources[0x29]	17503	1			T6	1		T1	636		T5	7
valid_sources[0x2a]	14803	1			T6	3		T1	614		T22	2
valid_sources[0x2b]	14805	1			T7	3		T1	535		T20	2
valid_sources[0x2c]	16051	1			T4	1		T1	575		T23	3
valid_sources[0x2d]	15421	1			T7	2		T1	598		T22	1
valid_sources[0x2e]	16817	1			T1	621		T22	2		T5	4
valid_sources[0x2f]	16056	1			T6	1		T1	657		T5	1
valid_sources[0x30]	17017	1			T4	2		T1	726		T2	15
valid_sources[0x31]	15781	1			T1	670		T5	1		T2	7
valid_sources[0x32]	16928	1			T6	3		T4	1		T26	5
valid_sources[0x33]	16148	1			T4	2		T1	648		T22	1
valid_sources[0x34]	17075	1			T1	723		T22	6		T5	3
valid_sources[0x35]	15977	1			T6	1		T1	678		T22	2
valid_sources[0x36]	17327	1			T1	664		T5	1		T2	6
valid_sources[0x37]	15606	1			T7	13		T4	1		T1	727
valid_sources[0x38]	16593	1			T4	4		T1	669		T5	5
valid_sources[0x39]	15944	1			T1	676		T22	1		T5	2
valid_sources[0x3a]	16103	1			T1	648		T5	3		T25	8
valid_sources[0x3b]	18224	1			T1	682		T5	4		T2	6
valid_sources[0x3c]	16071	1			T6	1		T1	697		T3	216
valid_sources[0x3d]	16104	1			T1	709		T22	2		T5	1
valid_sources[0x3e]	14739	1			T6	1		T1	710		T23	2
valid_sources[0x3f]	17440	1			T8	2		T4	5		T1	642
valid_sources[0x40]	15460	1			T6	3		T1	695		T22	3
valid_sources[0x41]	14717	1			T6	1		T1	682		T22	1
valid_sources[0x42]	14486	1			T6	4		T1	656		T22	2
valid_sources[0x43]	17577	1			T6	1		T4	2		T1	649
valid_sources[0x44]	16292	1			T1	681		T22	1		T5	1
valid_sources[0x45]	15264	1			T4	1		T26	1		T1	711
valid_sources[0x46]	16360	1			T1	633		T5	1		T24	7
valid_sources[0x47]	16035	1			T1	690		T20	2		T22	1
valid_sources[0x48]	15913	1			T4	2		T1	644		T5	1
valid_sources[0x49]	15435	1			T1	714		T22	1		T5	4
valid_sources[0x4a]	15503	1			T1	684		T20	2		T5	4
valid_sources[0x4b]	16622	1			T6	2		T4	1		T1	642
valid_sources[0x4c]	15439	1			T6	1		T1	664		T22	1
valid_sources[0x4d]	16028	1			T4	4		T1	643		T5	6
valid_sources[0x4e]	17385	1			T1	700		T23	1		T5	1
valid_sources[0x4f]	16304	1			T4	10		T1	689		T5	4
valid_sources[0x50]	15537	1			T6	1		T1	725		T22	1
valid_sources[0x51]	16824	1			T1	655		T22	1		T5	1
valid_sources[0x52]	18127	1			T6	1		T4	3		T26	4
valid_sources[0x53]	15218	1			T4	1		T1	671		T22	1
valid_sources[0x54]	15906	1			T7	3		T6	1		T1	665
valid_sources[0x55]	16818	1			T6	1		T1	651		T5	3
valid_sources[0x56]	15287	1			T6	3		T4	1		T1	652
valid_sources[0x57]	14693	1			T4	2		T1	632		T22	1
valid_sources[0x58]	15759	1			T6	2		T1	704		T22	1
valid_sources[0x59]	15998	1			T6	2		T1	645		T5	3
valid_sources[0x5a]	16275	1			T6	1		T4	4		T1	669
valid_sources[0x5b]	15450	1			T4	2		T1	659		T22	2
valid_sources[0x5c]	18266	1			T7	1		T6	1		T1	708
valid_sources[0x5d]	15276	1			T4	2		T1	673		T5	1
valid_sources[0x5e]	17490	1			T6	1		T1	648		T5	1
valid_sources[0x5f]	16225	1			T1	700		T22	2		T5	2
valid_sources[0x60]	14696	1			T1	601		T5	1		T2	5
valid_sources[0x61]	16288	1			T7	10		T4	4		T26	3
valid_sources[0x62]	16065	1			T4	5		T1	638		T5	4
valid_sources[0x63]	16362	1			T6	1		T1	661		T5	4
valid_sources[0x64]	15323	1			T1	637		T20	3		T22	1
valid_sources[0x65]	14076	1			T6	1		T1	662		T22	1
valid_sources[0x66]	15382	1			T6	1		T4	3		T1	658
valid_sources[0x67]	16432	1			T6	1		T1	683		T20	2
valid_sources[0x68]	16097	1			T4	5		T1	676		T5	2
valid_sources[0x69]	15679	1			T6	2		T4	1		T1	651
valid_sources[0x6a]	15741	1			T7	1		T1	799		T23	1
valid_sources[0x6b]	19202	1			T6	1		T1	595		T5	2
valid_sources[0x6c]	17229	1			T6	1		T4	3		T1	701
valid_sources[0x6d]	16071	1			T26	1		T1	669		T22	1
valid_sources[0x6e]	17760	1			T26	12		T1	649		T22	2
valid_sources[0x6f]	15895	1			T1	682		T22	1		T5	1
valid_sources[0x70]	15081	1			T6	1		T1	706		T5	6
valid_sources[0x71]	16211	1			T1	699		T22	1		T5	2
valid_sources[0x72]	17193	1			T9	1		T1	705		T5	3
valid_sources[0x73]	14825	1			T4	11		T1	731		T5	5
valid_sources[0x74]	15401	1			T1	583		T22	1		T5	1
valid_sources[0x75]	15993	1			T6	2		T1	624		T22	1
valid_sources[0x76]	17554	1			T1	570		T22	1		T5	4
valid_sources[0x77]	16269	1			T1	705		T22	1		T3	226
valid_sources[0x78]	16400	1			T4	4		T1	717		T20	1
valid_sources[0x79]	15807	1			T6	4		T4	4		T1	670
valid_sources[0x7a]	16569	1			T9	1		T6	1		T4	4
valid_sources[0x7b]	14919	1			T6	3		T4	3		T1	614
valid_sources[0x7c]	17104	1			T6	1		T1	692		T23	2
valid_sources[0x7d]	15690	1			T6	1		T4	6		T1	597
valid_sources[0x7e]	16249	1			T4	2		T1	650		T5	2
valid_sources[0x7f]	16721	1			T6	1		T1	645		T22	3
valid_sources[0x80]	16150	1			T6	2		T4	1		T1	666

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

887736

1

T7

15

T8

2

T9

1

values[0x0]

all_enables

biggest_size

1340311

1

T7

4

T8

2

T9

1

values[0x1]

all_enables

biggest_size

1292635

1

T7

2

T6

21

T4

19