Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T22
0	1	Covered	T1,T22,T25
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T22
1	0	Covered	T35,T36,T37
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1006926584	14579	0	0
GateOpen_A	1006926584	20966	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006926584	14579	0	0
T1	2016503	474	0	0
T2	415238	0	0	0
T3	0	215	0	0
T5	238920	0	0	0
T19	4013	0	0	0
T20	19228	0	0	0
T21	10233	0	0	0
T22	213775	8	0	0
T23	23505	0	0	0
T24	8728	8	0	0
T25	7008	18	0	0
T35	0	10	0	0
T39	0	6	0	0
T41	0	4	0	0
T96	0	4	0	0
T153	0	35	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006926584	20966	0	0
T1	2016503	498	0	0
T4	78720	20	0	0
T5	0	68	0	0
T6	169181	4	0	0
T8	4733	4	0	0
T9	10333	4	0	0
T19	4013	0	0	0
T20	19228	4	0	0
T21	10233	4	0	0
T22	213775	16	0	0
T26	4950	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T22
0	1	Covered	T1,T22,T25
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T22
1	0	Covered	T35,T36,T37
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	111004528	3465	0	0
GateOpen_A	111004528	5060	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111004528	3465	0	0
T1	222772	110	0	0
T2	46126	0	0	0
T3	0	51	0	0
T5	17975	0	0	0
T19	435	0	0	0
T20	2329	0	0	0
T21	1213	0	0	0
T22	23739	2	0	0
T23	2969	0	0	0
T24	950	2	0	0
T25	761	4	0	0
T35	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T96	0	1	0	0
T153	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111004528	5060	0	0
T1	222772	116	0	0
T4	7054	5	0	0
T5	0	17	0	0
T6	18154	1	0	0
T8	544	1	0	0
T9	1158	1	0	0
T19	435	0	0	0
T20	2329	1	0	0
T21	1213	1	0	0
T22	23739	4	0	0
T26	544	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T22
0	1	Covered	T1,T22,T25
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T22
1	0	Covered	T35,T36,T37
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	222009868	3734	0	0
GateOpen_A	222009868	5329	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222009868	3734	0	0
T1	445547	129	0	0
T2	92252	0	0	0
T3	0	53	0	0
T5	35951	0	0	0
T19	870	0	0	0
T20	4661	0	0	0
T21	2429	0	0	0
T22	47479	2	0	0
T23	5944	0	0	0
T24	1900	2	0	0
T25	1522	5	0	0
T35	0	2	0	0
T39	0	2	0	0
T41	0	1	0	0
T96	0	1	0	0
T153	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222009868	5329	0	0
T1	445547	135	0	0
T4	14109	5	0	0
T5	0	17	0	0
T6	36307	1	0	0
T8	1089	1	0	0
T9	2315	1	0	0
T19	870	0	0	0
T20	4661	1	0	0
T21	2429	1	0	0
T22	47479	4	0	0
T26	1087	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T22
0	1	Covered	T1,T22,T25
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T22
1	0	Covered	T35,T36,T37
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	445693628	3695	0	0
GateOpen_A	445693628	5293	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445693628	3695	0	0
T1	892055	116	0	0
T2	184571	0	0	0
T3	0	55	0	0
T5	123327	0	0	0
T19	1805	0	0	0
T20	8158	0	0	0
T21	4394	0	0	0
T22	95036	2	0	0
T23	9728	0	0	0
T24	3919	2	0	0
T25	3150	5	0	0
T35	0	2	0	0
T39	0	2	0	0
T41	0	1	0	0
T96	0	1	0	0
T153	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445693628	5293	0	0
T1	892055	122	0	0
T4	38371	5	0	0
T5	0	17	0	0
T6	72638	1	0	0
T8	2067	1	0	0
T9	4573	1	0	0
T19	1805	0	0	0
T20	8158	1	0	0
T21	4394	1	0	0
T22	95036	4	0	0
T26	2213	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T22
0	1	Covered	T1,T22,T25
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T22
1	0	Covered	T35,T36,T37
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	228218560	3685	0	0
GateOpen_A	228218560	5284	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228218560	3685	0	0
T1	456129	119	0	0
T2	92289	0	0	0
T3	0	56	0	0
T5	61667	0	0	0
T19	903	0	0	0
T20	4080	0	0	0
T21	2197	0	0	0
T22	47521	2	0	0
T23	4864	0	0	0
T24	1959	2	0	0
T25	1575	4	0	0
T35	0	4	0	0
T39	0	1	0	0
T41	0	1	0	0
T96	0	1	0	0
T153	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228218560	5284	0	0
T1	456129	125	0	0
T4	19186	5	0	0
T5	0	17	0	0
T6	42082	1	0	0
T8	1033	1	0	0
T9	2287	1	0	0
T19	903	0	0	0
T20	4080	1	0	0
T21	2197	1	0	0
T22	47521	4	0	0
T26	1106	1	0	0