Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	812840455	80854	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812840455	80854	0	0
T1	2347250	2470	0	0
T2	124975	163	0	0
T3	0	677	0	0
T5	160580	0	0	0
T12	0	122	0	0
T13	0	285	0	0
T14	0	732	0	0
T15	0	203	0	0
T16	0	34	0	0
T17	0	585	0	0
T18	0	1319	0	0
T19	9020	0	0	0
T20	10195	0	0	0
T21	10985	0	0	0
T22	123745	0	0	0
T23	12660	0	0	0
T24	3260	0	0	0
T25	4095	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	162568091	12043	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162568091	12043	0	0
T1	469450	359	0	0
T2	24995	29	0	0
T3	0	125	0	0
T5	32116	0	0	0
T12	0	21	0	0
T13	0	37	0	0
T14	0	105	0	0
T15	0	30	0	0
T16	0	6	0	0
T17	0	87	0	0
T18	0	210	0	0
T19	1804	0	0	0
T20	2039	0	0	0
T21	2197	0	0	0
T22	24749	0	0	0
T23	2532	0	0	0
T24	652	0	0	0
T25	819	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	162568091	16230	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162568091	16230	0	0
T1	469450	494	0	0
T2	24995	32	0	0
T3	0	129	0	0
T5	32116	0	0	0
T12	0	25	0	0
T13	0	57	0	0
T14	0	143	0	0
T15	0	40	0	0
T16	0	7	0	0
T17	0	123	0	0
T18	0	266	0	0
T19	1804	0	0	0
T20	2039	0	0	0
T21	2197	0	0	0
T22	24749	0	0	0
T23	2532	0	0	0
T24	652	0	0	0
T25	819	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	162568091	24320	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162568091	24320	0	0
T1	469450	768	0	0
T2	24995	40	0	0
T3	0	167	0	0
T5	32116	0	0	0
T12	0	31	0	0
T13	0	95	0	0
T14	0	216	0	0
T15	0	67	0	0
T16	0	9	0	0
T17	0	191	0	0
T18	0	370	0	0
T19	1804	0	0	0
T20	2039	0	0	0
T21	2197	0	0	0
T22	24749	0	0	0
T23	2532	0	0	0
T24	652	0	0	0
T25	819	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	162568091	11974	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162568091	11974	0	0
T1	469450	355	0	0
T2	24995	29	0	0
T3	0	125	0	0
T5	32116	0	0	0
T12	0	21	0	0
T13	0	37	0	0
T14	0	103	0	0
T15	0	26	0	0
T16	0	6	0	0
T17	0	71	0	0
T18	0	206	0	0
T19	1804	0	0	0
T20	2039	0	0	0
T21	2197	0	0	0
T22	24749	0	0	0
T23	2532	0	0	0
T24	652	0	0	0
T25	819	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	162568091	16287	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162568091	16287	0	0
T1	469450	494	0	0
T2	24995	33	0	0
T3	0	131	0	0
T5	32116	0	0	0
T12	0	24	0	0
T13	0	59	0	0
T14	0	165	0	0
T15	0	40	0	0
T16	0	6	0	0
T17	0	113	0	0
T18	0	267	0	0
T19	1804	0	0	0
T20	2039	0	0	0
T21	2197	0	0	0
T22	24749	0	0	0
T23	2532	0	0	0
T24	652	0	0	0
T25	819	0	0	0