Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_mubi4_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_io_step_down_req_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_io_div2_div_scanmode_sync 100.00 100.00 100.00
tb.dut.u_io_div4_div_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_main_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_io_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_usb_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_io_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_io_div2_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_io_div4_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_main_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_usb_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_clk_io_div4_peri_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_io_div2_peri_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_io_peri_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_usb_peri_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clk_main_aes_trans.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync 100.00 100.00 100.00


Module Instance : tb.dut.u_io_step_down_req_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_io_div2_div_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_io_div4_div_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_main_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_div2_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_div4_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_usb_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_io_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_div2_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_div4_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_main_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_main_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_usb_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_io_peri_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_usb_peri_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_aes_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_aes_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_hmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_hmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_kmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_kmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_otbn_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_otbn_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_io_step_down_req_sync

SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync

SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync

Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_io_div2_div_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div4_div_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_main_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_io_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_usb_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_io_div4_peri_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_io_div2_peri_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_io_peri_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_usb_peri_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_aes_trans.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_calib_rdy_sync

Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 6 6

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_io_meas.u_calib_rdy_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div2_meas.u_calib_rdy_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div4_meas.u_calib_rdy_sync

SCORELINE
100.00 100.00
tb.dut.u_main_meas.u_calib_rdy_sync

SCORELINE
100.00 100.00
tb.dut.u_usb_meas.u_calib_rdy_sync

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1

Cond Coverage for Module : prim_mubi4_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9
Branch Coverage for Module : prim_mubi4_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9

Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 22540 22540 0 0
OutputsKnown_A 2147483647 2147483647 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 975408546 962113038 0 14490
gen_flops.gen_stable_chks.OutputDelay_A 2147483647 2147483647 0 16905
gen_flops.gen_stable_chks.OutputIfUnstable_A 2147483647 194062 0 0
gen_no_flops.OutputDelay_A 2147483647 2147483647 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22540 22540 0 0
T1 28 28 0 0
T4 28 28 0 0
T6 28 28 0 0
T7 28 28 0 0
T8 28 28 0 0
T9 28 28 0 0
T19 28 28 0 0
T20 28 28 0 0
T21 28 28 0 0
T26 28 28 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 18022335 17954154 0 0
T4 616716 246569 0 0
T6 1217363 1215225 0 0
T7 141299 139002 0 0
T8 41215 39799 0 0
T9 67095 65300 0 0
T19 47981 45297 0 0
T20 132412 129177 0 0
T21 86574 83913 0 0
T26 59521 56558 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 975408546 962113038 0 14490
T1 2816700 2804820 0 18
T4 59952 18384 0 18
T6 126234 125976 0 18
T7 14682 14406 0 18
T8 6450 6186 0 18
T9 3996 3864 0 18
T19 10824 10158 0 18
T20 12234 11868 0 18
T21 13182 12720 0 18
T26 13554 12792 0 18

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 16905
T1 5627167 5603301 0 21
T4 218239 67198 0 21
T6 417383 416444 0 21
T7 48234 47359 0 21
T8 12824 12309 0 21
T9 24957 24203 0 21
T19 12928 12135 0 21
T20 46228 44900 0 21
T21 27095 26158 0 21
T26 15946 15052 0 21

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 194062 0 0
T1 5627167 4254 0 0
T3 0 761 0 0
T4 218239 24 0 0
T6 417383 4 0 0
T7 48234 250 0 0
T8 12824 31 0 0
T9 24957 16 0 0
T19 12928 12 0 0
T20 46228 231 0 0
T21 27095 201 0 0
T23 0 167 0 0
T26 15946 181 0 0
T39 0 37 0 0
T62 0 94 0 0
T94 0 63 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 9578468 9545982 0 0
T4 338525 160713 0 0
T6 673746 672766 0 0
T7 78383 77198 0 0
T8 21941 21265 0 0
T9 38142 37194 0 0
T19 24229 22965 0 0
T20 73950 72370 0 0
T21 46297 44996 0 0
T26 30021 28675 0 0

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9

Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 445693197 441131623 0 0
gen_flops.gen_stable_chks.OutputDelay_A 445693197 441124879 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 445693197 26794 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445693197 441131623 0 0
T1 892055 888296 0 0
T4 38371 11836 0 0
T6 72637 72475 0 0
T7 8388 8240 0 0
T8 2066 1986 0 0
T9 4573 4438 0 0
T19 1804 1696 0 0
T20 8158 7927 0 0
T21 4393 4245 0 0
T26 2212 2091 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445693197 441124879 0 2415
T1 892055 888293 0 3
T4 38371 11818 0 3
T6 72637 72472 0 3
T7 8388 8237 0 3
T8 2066 1983 0 3
T9 4573 4435 0 3
T19 1804 1693 0 3
T20 8158 7924 0 3
T21 4393 4242 0 3
T26 2212 2088 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445693197 26794 0 0
T1 892055 622 0 0
T3 0 315 0 0
T4 38371 0 0 0
T6 72637 0 0 0
T7 8388 60 0 0
T8 2066 10 0 0
T9 4573 5 0 0
T19 1804 0 0 0
T20 8158 65 0 0
T21 4393 65 0 0
T23 0 71 0 0
T26 2212 0 0 0
T62 0 36 0 0
T94 0 32 0 0

Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 162568091 160359227 0 0
gen_no_flops.OutputDelay_A 162568091 160359227 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160359227 0 0
T1 469450 467474 0 0
T4 9992 3087 0 0
T6 21039 20999 0 0
T7 2447 2404 0 0
T8 1075 1034 0 0
T9 666 647 0 0
T19 1804 1696 0 0
T20 2039 1981 0 0
T21 2197 2123 0 0
T26 2259 2135 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160359227 0 0
T1 469450 467474 0 0
T4 9992 3087 0 0
T6 21039 20999 0 0
T7 2447 2404 0 0
T8 1075 1034 0 0
T9 666 647 0 0
T19 1804 1696 0 0
T20 2039 1981 0 0
T21 2197 2123 0 0
T26 2259 2135 0 0

Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 162568091 160359227 0 0
gen_no_flops.OutputDelay_A 162568091 160359227 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160359227 0 0
T1 469450 467474 0 0
T4 9992 3087 0 0
T6 21039 20999 0 0
T7 2447 2404 0 0
T8 1075 1034 0 0
T9 666 647 0 0
T19 1804 1696 0 0
T20 2039 1981 0 0
T21 2197 2123 0 0
T26 2259 2135 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160359227 0 0
T1 469450 467474 0 0
T4 9992 3087 0 0
T6 21039 20999 0 0
T7 2447 2404 0 0
T8 1075 1034 0 0
T9 666 647 0 0
T19 1804 1696 0 0
T20 2039 1981 0 0
T21 2197 2123 0 0
T26 2259 2135 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 162568091 160359227 0 0
gen_flops.gen_stable_chks.OutputDelay_A 162568091 160352173 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 162568091 16689 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160359227 0 0
T1 469450 467474 0 0
T4 9992 3087 0 0
T6 21039 20999 0 0
T7 2447 2404 0 0
T8 1075 1034 0 0
T9 666 647 0 0
T19 1804 1696 0 0
T20 2039 1981 0 0
T21 2197 2123 0 0
T26 2259 2135 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160352173 0 2415
T1 469450 467470 0 3
T4 9992 3064 0 3
T6 21039 20996 0 3
T7 2447 2401 0 3
T8 1075 1031 0 3
T9 666 644 0 3
T19 1804 1693 0 3
T20 2039 1978 0 3
T21 2197 2120 0 3
T26 2259 2132 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 16689 0 0
T1 469450 389 0 0
T3 0 192 0 0
T4 9992 0 0 0
T6 21039 0 0 0
T7 2447 54 0 0
T8 1075 3 0 0
T9 666 3 0 0
T19 1804 0 0 0
T20 2039 54 0 0
T21 2197 45 0 0
T23 0 47 0 0
T26 2259 0 0 0
T39 0 18 0 0
T62 0 21 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T1 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T1 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T1 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T1
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T1
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T1
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T1
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T1
0 Covered T7,T8,T9

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 162568091 160359227 0 0
gen_flops.gen_stable_chks.OutputDelay_A 162568091 160352173 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 162568091 18921 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160359227 0 0
T1 469450 467474 0 0
T4 9992 3087 0 0
T6 21039 20999 0 0
T7 2447 2404 0 0
T8 1075 1034 0 0
T9 666 647 0 0
T19 1804 1696 0 0
T20 2039 1981 0 0
T21 2197 2123 0 0
T26 2259 2135 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160352173 0 2415
T1 469450 467470 0 3
T4 9992 3064 0 3
T6 21039 20996 0 3
T7 2447 2401 0 3
T8 1075 1031 0 3
T9 666 644 0 3
T19 1804 1693 0 3
T20 2039 1978 0 3
T21 2197 2120 0 3
T26 2259 2132 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 18921 0 0
T1 469450 446 0 0
T3 0 254 0 0
T4 9992 0 0 0
T6 21039 0 0 0
T7 2447 65 0 0
T8 1075 7 0 0
T9 666 0 0 0
T19 1804 0 0 0
T20 2039 49 0 0
T21 2197 26 0 0
T23 0 49 0 0
T26 2259 0 0 0
T39 0 19 0 0
T62 0 37 0 0
T94 0 31 0 0

Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 475396197 473019193 0 0
gen_no_flops.OutputDelay_A 475396197 473019193 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 473019193 0 0
T1 949053 947162 0 0
T4 39971 29388 0 0
T6 75667 75641 0 0
T7 8738 8612 0 0
T8 2152 2112 0 0
T9 4763 4651 0 0
T19 1879 1810 0 0
T20 8498 8386 0 0
T21 4577 4479 0 0
T26 2304 2264 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 473019193 0 0
T1 949053 947162 0 0
T4 39971 29388 0 0
T6 75667 75641 0 0
T7 8738 8612 0 0
T8 2152 2112 0 0
T9 4763 4651 0 0
T19 1879 1810 0 0
T20 8498 8386 0 0
T21 4577 4479 0 0
T26 2304 2264 0 0

Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 445693197 443420535 0 0
gen_no_flops.OutputDelay_A 445693197 443420535 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445693197 443420535 0 0
T1 892055 890352 0 0
T4 38371 28211 0 0
T6 72637 72612 0 0
T7 8388 8267 0 0
T8 2066 2027 0 0
T9 4573 4465 0 0
T19 1804 1738 0 0
T20 8158 8051 0 0
T21 4393 4300 0 0
T26 2212 2173 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445693197 443420535 0 0
T1 892055 890352 0 0
T4 38371 28211 0 0
T6 72637 72612 0 0
T7 8388 8267 0 0
T8 2066 2027 0 0
T9 4573 4465 0 0
T19 1804 1738 0 0
T20 8158 8051 0 0
T21 4393 4300 0 0
T26 2212 2173 0 0

Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 222009492 222009492 0 0
gen_no_flops.OutputDelay_A 222009492 222009492 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 222009492 222009492 0 0
T1 445547 445547 0 0
T4 14108 14108 0 0
T6 36306 36306 0 0
T7 4954 4954 0 0
T8 1089 1089 0 0
T9 2315 2315 0 0
T19 869 869 0 0
T20 4661 4661 0 0
T21 2428 2428 0 0
T26 1087 1087 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 222009492 222009492 0 0
T1 445547 445547 0 0
T4 14108 14108 0 0
T6 36306 36306 0 0
T7 4954 4954 0 0
T8 1089 1089 0 0
T9 2315 2315 0 0
T19 869 869 0 0
T20 4661 4661 0 0
T21 2428 2428 0 0
T26 1087 1087 0 0

Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 111004119 111004119 0 0
gen_no_flops.OutputDelay_A 111004119 111004119 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 111004119 111004119 0 0
T1 222772 222772 0 0
T4 7053 7053 0 0
T6 18153 18153 0 0
T7 2475 2475 0 0
T8 543 543 0 0
T9 1157 1157 0 0
T19 435 435 0 0
T20 2328 2328 0 0
T21 1212 1212 0 0
T26 543 543 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 111004119 111004119 0 0
T1 222772 222772 0 0
T4 7053 7053 0 0
T6 18153 18153 0 0
T7 2475 2475 0 0
T8 543 543 0 0
T9 1157 1157 0 0
T19 435 435 0 0
T20 2328 2328 0 0
T21 1212 1212 0 0
T26 543 543 0 0

Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 228218127 227070738 0 0
gen_no_flops.OutputDelay_A 228218127 227070738 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 228218127 227070738 0 0
T1 456129 455221 0 0
T4 19186 14107 0 0
T6 42081 42068 0 0
T7 4194 4134 0 0
T8 1033 1014 0 0
T9 2286 2232 0 0
T19 902 869 0 0
T20 4079 4026 0 0
T21 2197 2151 0 0
T26 1105 1086 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 228218127 227070738 0 0
T1 456129 455221 0 0
T4 19186 14107 0 0
T6 42081 42068 0 0
T7 4194 4134 0 0
T8 1033 1014 0 0
T9 2286 2232 0 0
T19 902 869 0 0
T20 4079 4026 0 0
T21 2197 2151 0 0
T26 1105 1086 0 0

Line Coverage for Instance : tb.dut.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 6 6

Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 162568091 160359227 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 162568091 160352173 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160359227 0 0
T1 469450 467474 0 0
T4 9992 3087 0 0
T6 21039 20999 0 0
T7 2447 2404 0 0
T8 1075 1034 0 0
T9 666 647 0 0
T19 1804 1696 0 0
T20 2039 1981 0 0
T21 2197 2123 0 0
T26 2259 2135 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160352173 0 2415
T1 469450 467470 0 3
T4 9992 3064 0 3
T6 21039 20996 0 3
T7 2447 2401 0 3
T8 1075 1031 0 3
T9 666 644 0 3
T19 1804 1693 0 3
T20 2039 1978 0 3
T21 2197 2120 0 3
T26 2259 2132 0 3

Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 162568091 160359227 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 162568091 160352173 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160359227 0 0
T1 469450 467474 0 0
T4 9992 3087 0 0
T6 21039 20999 0 0
T7 2447 2404 0 0
T8 1075 1034 0 0
T9 666 647 0 0
T19 1804 1696 0 0
T20 2039 1981 0 0
T21 2197 2123 0 0
T26 2259 2135 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160352173 0 2415
T1 469450 467470 0 3
T4 9992 3064 0 3
T6 21039 20996 0 3
T7 2447 2401 0 3
T8 1075 1031 0 3
T9 666 644 0 3
T19 1804 1693 0 3
T20 2039 1978 0 3
T21 2197 2120 0 3
T26 2259 2132 0 3

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 162568091 160359227 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 162568091 160352173 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160359227 0 0
T1 469450 467474 0 0
T4 9992 3087 0 0
T6 21039 20999 0 0
T7 2447 2404 0 0
T8 1075 1034 0 0
T9 666 647 0 0
T19 1804 1696 0 0
T20 2039 1981 0 0
T21 2197 2123 0 0
T26 2259 2135 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160352173 0 2415
T1 469450 467470 0 3
T4 9992 3064 0 3
T6 21039 20996 0 3
T7 2447 2401 0 3
T8 1075 1031 0 3
T9 666 644 0 3
T19 1804 1693 0 3
T20 2039 1978 0 3
T21 2197 2120 0 3
T26 2259 2132 0 3

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 162568091 160359227 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 162568091 160352173 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160359227 0 0
T1 469450 467474 0 0
T4 9992 3087 0 0
T6 21039 20999 0 0
T7 2447 2404 0 0
T8 1075 1034 0 0
T9 666 647 0 0
T19 1804 1696 0 0
T20 2039 1981 0 0
T21 2197 2123 0 0
T26 2259 2135 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160352173 0 2415
T1 469450 467470 0 3
T4 9992 3064 0 3
T6 21039 20996 0 3
T7 2447 2401 0 3
T8 1075 1031 0 3
T9 666 644 0 3
T19 1804 1693 0 3
T20 2039 1978 0 3
T21 2197 2120 0 3
T26 2259 2132 0 3

Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 162568091 160359227 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 162568091 160352173 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160359227 0 0
T1 469450 467474 0 0
T4 9992 3087 0 0
T6 21039 20999 0 0
T7 2447 2404 0 0
T8 1075 1034 0 0
T9 666 647 0 0
T19 1804 1696 0 0
T20 2039 1981 0 0
T21 2197 2123 0 0
T26 2259 2135 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160352173 0 2415
T1 469450 467470 0 3
T4 9992 3064 0 3
T6 21039 20996 0 3
T7 2447 2401 0 3
T8 1075 1031 0 3
T9 666 644 0 3
T19 1804 1693 0 3
T20 2039 1978 0 3
T21 2197 2120 0 3
T26 2259 2132 0 3

Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 162568091 160359227 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 162568091 160352173 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160359227 0 0
T1 469450 467474 0 0
T4 9992 3087 0 0
T6 21039 20999 0 0
T7 2447 2404 0 0
T8 1075 1034 0 0
T9 666 647 0 0
T19 1804 1696 0 0
T20 2039 1981 0 0
T21 2197 2123 0 0
T26 2259 2135 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160352173 0 2415
T1 469450 467470 0 3
T4 9992 3064 0 3
T6 21039 20996 0 3
T7 2447 2401 0 3
T8 1075 1031 0 3
T9 666 644 0 3
T19 1804 1693 0 3
T20 2039 1978 0 3
T21 2197 2120 0 3
T26 2259 2132 0 3

Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 162568091 160359227 0 0
gen_no_flops.OutputDelay_A 162568091 160359227 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160359227 0 0
T1 469450 467474 0 0
T4 9992 3087 0 0
T6 21039 20999 0 0
T7 2447 2404 0 0
T8 1075 1034 0 0
T9 666 647 0 0
T19 1804 1696 0 0
T20 2039 1981 0 0
T21 2197 2123 0 0
T26 2259 2135 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160359227 0 0
T1 469450 467474 0 0
T4 9992 3087 0 0
T6 21039 20999 0 0
T7 2447 2404 0 0
T8 1075 1034 0 0
T9 666 647 0 0
T19 1804 1696 0 0
T20 2039 1981 0 0
T21 2197 2123 0 0
T26 2259 2135 0 0

Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 162568091 160359227 0 0
gen_no_flops.OutputDelay_A 162568091 160359227 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160359227 0 0
T1 469450 467474 0 0
T4 9992 3087 0 0
T6 21039 20999 0 0
T7 2447 2404 0 0
T8 1075 1034 0 0
T9 666 647 0 0
T19 1804 1696 0 0
T20 2039 1981 0 0
T21 2197 2123 0 0
T26 2259 2135 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160359227 0 0
T1 469450 467474 0 0
T4 9992 3087 0 0
T6 21039 20999 0 0
T7 2447 2404 0 0
T8 1075 1034 0 0
T9 666 647 0 0
T19 1804 1696 0 0
T20 2039 1981 0 0
T21 2197 2123 0 0
T26 2259 2135 0 0

Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 162568091 160359227 0 0
gen_no_flops.OutputDelay_A 162568091 160359227 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160359227 0 0
T1 469450 467474 0 0
T4 9992 3087 0 0
T6 21039 20999 0 0
T7 2447 2404 0 0
T8 1075 1034 0 0
T9 666 647 0 0
T19 1804 1696 0 0
T20 2039 1981 0 0
T21 2197 2123 0 0
T26 2259 2135 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160359227 0 0
T1 469450 467474 0 0
T4 9992 3087 0 0
T6 21039 20999 0 0
T7 2447 2404 0 0
T8 1075 1034 0 0
T9 666 647 0 0
T19 1804 1696 0 0
T20 2039 1981 0 0
T21 2197 2123 0 0
T26 2259 2135 0 0

Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 162568091 160359227 0 0
gen_no_flops.OutputDelay_A 162568091 160359227 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160359227 0 0
T1 469450 467474 0 0
T4 9992 3087 0 0
T6 21039 20999 0 0
T7 2447 2404 0 0
T8 1075 1034 0 0
T9 666 647 0 0
T19 1804 1696 0 0
T20 2039 1981 0 0
T21 2197 2123 0 0
T26 2259 2135 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162568091 160359227 0 0
T1 469450 467474 0 0
T4 9992 3087 0 0
T6 21039 20999 0 0
T7 2447 2404 0 0
T8 1075 1034 0 0
T9 666 647 0 0
T19 1804 1696 0 0
T20 2039 1981 0 0
T21 2197 2123 0 0
T26 2259 2135 0 0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 475396197 470630379 0 0
gen_flops.gen_stable_chks.OutputDelay_A 475396197 470623571 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 475396197 32997 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 470630379 0 0
T1 949053 945021 0 0
T4 39971 12331 0 0
T6 75667 75498 0 0
T7 8738 8583 0 0
T8 2152 2069 0 0
T9 4763 4623 0 0
T19 1879 1767 0 0
T20 8498 8258 0 0
T21 4577 4422 0 0
T26 2304 2178 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 470623571 0 2415
T1 949053 945017 0 3
T4 39971 12313 0 3
T6 75667 75495 0 3
T7 8738 8580 0 3
T8 2152 2066 0 3
T9 4763 4620 0 3
T19 1879 1764 0 3
T20 8498 8255 0 3
T21 4577 4419 0 3
T26 2304 2175 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 32997 0 0
T1 949053 682 0 0
T4 39971 6 0 0
T6 75667 1 0 0
T7 8738 18 0 0
T8 2152 4 0 0
T9 4763 1 0 0
T19 1879 3 0 0
T20 8498 18 0 0
T21 4577 14 0 0
T26 2304 43 0 0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 475396197 470630379 0 0
gen_no_flops.OutputDelay_A 475396197 470630379 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 470630379 0 0
T1 949053 945021 0 0
T4 39971 12331 0 0
T6 75667 75498 0 0
T7 8738 8583 0 0
T8 2152 2069 0 0
T9 4763 4623 0 0
T19 1879 1767 0 0
T20 8498 8258 0 0
T21 4577 4422 0 0
T26 2304 2178 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 470630379 0 0
T1 949053 945021 0 0
T4 39971 12331 0 0
T6 75667 75498 0 0
T7 8738 8583 0 0
T8 2152 2069 0 0
T9 4763 4623 0 0
T19 1879 1767 0 0
T20 8498 8258 0 0
T21 4577 4422 0 0
T26 2304 2178 0 0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 475396197 470630379 0 0
gen_flops.gen_stable_chks.OutputDelay_A 475396197 470623571 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 475396197 32922 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 470630379 0 0
T1 949053 945021 0 0
T4 39971 12331 0 0
T6 75667 75498 0 0
T7 8738 8583 0 0
T8 2152 2069 0 0
T9 4763 4623 0 0
T19 1879 1767 0 0
T20 8498 8258 0 0
T21 4577 4422 0 0
T26 2304 2178 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 470623571 0 2415
T1 949053 945017 0 3
T4 39971 12313 0 3
T6 75667 75495 0 3
T7 8738 8580 0 3
T8 2152 2066 0 3
T9 4763 4620 0 3
T19 1879 1764 0 3
T20 8498 8255 0 3
T21 4577 4419 0 3
T26 2304 2175 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 32922 0 0
T1 949053 708 0 0
T4 39971 6 0 0
T6 75667 1 0 0
T7 8738 16 0 0
T8 2152 4 0 0
T9 4763 3 0 0
T19 1879 3 0 0
T20 8498 18 0 0
T21 4577 16 0 0
T26 2304 47 0 0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 475396197 470630379 0 0
gen_no_flops.OutputDelay_A 475396197 470630379 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 470630379 0 0
T1 949053 945021 0 0
T4 39971 12331 0 0
T6 75667 75498 0 0
T7 8738 8583 0 0
T8 2152 2069 0 0
T9 4763 4623 0 0
T19 1879 1767 0 0
T20 8498 8258 0 0
T21 4577 4422 0 0
T26 2304 2178 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 470630379 0 0
T1 949053 945021 0 0
T4 39971 12331 0 0
T6 75667 75498 0 0
T7 8738 8583 0 0
T8 2152 2069 0 0
T9 4763 4623 0 0
T19 1879 1767 0 0
T20 8498 8258 0 0
T21 4577 4422 0 0
T26 2304 2178 0 0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 475396197 470630379 0 0
gen_flops.gen_stable_chks.OutputDelay_A 475396197 470623571 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 475396197 32782 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 470630379 0 0
T1 949053 945021 0 0
T4 39971 12331 0 0
T6 75667 75498 0 0
T7 8738 8583 0 0
T8 2152 2069 0 0
T9 4763 4623 0 0
T19 1879 1767 0 0
T20 8498 8258 0 0
T21 4577 4422 0 0
T26 2304 2178 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 470623571 0 2415
T1 949053 945017 0 3
T4 39971 12313 0 3
T6 75667 75495 0 3
T7 8738 8580 0 3
T8 2152 2066 0 3
T9 4763 4620 0 3
T19 1879 1764 0 3
T20 8498 8255 0 3
T21 4577 4419 0 3
T26 2304 2175 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 32782 0 0
T1 949053 693 0 0
T4 39971 6 0 0
T6 75667 1 0 0
T7 8738 25 0 0
T8 2152 2 0 0
T9 4763 1 0 0
T19 1879 3 0 0
T20 8498 14 0 0
T21 4577 19 0 0
T26 2304 44 0 0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 475396197 470630379 0 0
gen_no_flops.OutputDelay_A 475396197 470630379 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 470630379 0 0
T1 949053 945021 0 0
T4 39971 12331 0 0
T6 75667 75498 0 0
T7 8738 8583 0 0
T8 2152 2069 0 0
T9 4763 4623 0 0
T19 1879 1767 0 0
T20 8498 8258 0 0
T21 4577 4422 0 0
T26 2304 2178 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 470630379 0 0
T1 949053 945021 0 0
T4 39971 12331 0 0
T6 75667 75498 0 0
T7 8738 8583 0 0
T8 2152 2069 0 0
T9 4763 4623 0 0
T19 1879 1767 0 0
T20 8498 8258 0 0
T21 4577 4422 0 0
T26 2304 2178 0 0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT7,T8,T9
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T7,T8,T9

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 475396197 470630379 0 0
gen_flops.gen_stable_chks.OutputDelay_A 475396197 470623571 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 475396197 32957 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 470630379 0 0
T1 949053 945021 0 0
T4 39971 12331 0 0
T6 75667 75498 0 0
T7 8738 8583 0 0
T8 2152 2069 0 0
T9 4763 4623 0 0
T19 1879 1767 0 0
T20 8498 8258 0 0
T21 4577 4422 0 0
T26 2304 2178 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 470623571 0 2415
T1 949053 945017 0 3
T4 39971 12313 0 3
T6 75667 75495 0 3
T7 8738 8580 0 3
T8 2152 2066 0 3
T9 4763 4620 0 3
T19 1879 1764 0 3
T20 8498 8255 0 3
T21 4577 4419 0 3
T26 2304 2175 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 32957 0 0
T1 949053 714 0 0
T4 39971 6 0 0
T6 75667 1 0 0
T7 8738 12 0 0
T8 2152 1 0 0
T9 4763 3 0 0
T19 1879 3 0 0
T20 8498 13 0 0
T21 4577 16 0 0
T26 2304 47 0 0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 475396197 470630379 0 0
gen_no_flops.OutputDelay_A 475396197 470630379 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T26 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 470630379 0 0
T1 949053 945021 0 0
T4 39971 12331 0 0
T6 75667 75498 0 0
T7 8738 8583 0 0
T8 2152 2069 0 0
T9 4763 4623 0 0
T19 1879 1767 0 0
T20 8498 8258 0 0
T21 4577 4422 0 0
T26 2304 2178 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 475396197 470630379 0 0
T1 949053 945021 0 0
T4 39971 12331 0 0
T6 75667 75498 0 0
T7 8738 8583 0 0
T8 2152 2069 0 0
T9 4763 4623 0 0
T19 1879 1767 0 0
T20 8498 8258 0 0
T21 4577 4422 0 0
T26 2304 2178 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%