Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T1,T22

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	162568091	160221687	0	0
AllClkBypReqTrue_A	162568091	135292	0	0
IoClkBypReqFalse_A	162568091	160141632	0	2415
IoClkBypReqTrue_A	162568091	210851	0	0
LcClkBypAckFalse_A	162568091	160232621	0	0
LcClkBypAckTrue_A	162568091	124358	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162568091	160221687	0	0
T1	469450	467229	0	0
T4	9992	3081	0	0
T6	21039	20998	0	0
T7	2447	2009	0	0
T8	1075	952	0	0
T9	666	646	0	0
T19	1804	1695	0	0
T20	2039	1779	0	0
T21	2197	2061	0	0
T26	2259	2134	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162568091	135292	0	0
T1	469450	2435	0	0
T3	0	3126	0	0
T4	9992	0	0	0
T6	21039	0	0	0
T7	2447	394	0	0
T8	1075	81	0	0
T9	666	0	0	0
T19	1804	0	0	0
T20	2039	201	0	0
T21	2197	61	0	0
T23	0	455	0	0
T26	2259	0	0	0
T39	0	106	0	0
T62	0	172	0	0
T94	0	43	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162568091	160141632	0	2415
T1	469450	467068	0	3
T4	9992	3069	0	3
T6	21039	20996	0	3
T7	2447	1906	0	3
T8	1075	986	0	3
T9	666	607	0	3
T19	1804	1693	0	3
T20	2039	1548	0	3
T21	2197	1673	0	3
T26	2259	2132	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162568091	210851	0	0
T1	469450	4027	0	0
T3	0	3808	0	0
T4	9992	0	0	0
T6	21039	0	0	0
T7	2447	495	0	0
T8	1075	45	0	0
T9	666	37	0	0
T19	1804	0	0	0
T20	2039	430	0	0
T21	2197	447	0	0
T23	0	703	0	0
T26	2259	0	0	0
T39	0	187	0	0
T62	0	184	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162568091	160232621	0	0
T1	469450	467222	0	0
T4	9992	3081	0	0
T6	21039	20998	0	0
T7	2447	2145	0	0
T8	1075	991	0	0
T9	666	622	0	0
T19	1804	1695	0	0
T20	2039	1739	0	0
T21	2197	1873	0	0
T26	2259	2134	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162568091	124358	0	0
T1	469450	2504	0	0
T3	0	2388	0	0
T4	9992	0	0	0
T6	21039	0	0	0
T7	2447	258	0	0
T8	1075	42	0	0
T9	666	24	0	0
T19	1804	0	0	0
T20	2039	241	0	0
T21	2197	249	0	0
T23	0	464	0	0
T26	2259	0	0	0
T39	0	127	0	0
T62	0	110	0	0