Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1901586592	15784	0	0
TransStop_A	1901586592	8029	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1901586592	15784	0	0
T1	3796216	291	0	0
T3	0	134	0	0
T5	513876	0	0	0
T19	7520	0	0	0
T20	33996	0	0	0
T21	18312	0	0	0
T22	396000	0	0	0
T23	40532	0	0	0
T24	16328	0	0	0
T25	13124	0	0	0
T26	9220	19	0	0
T39	0	71	0	0
T41	0	4	0	0
T44	0	28	0	0
T61	0	30	0	0
T95	0	27	0	0
T96	0	4	0	0
T97	0	14	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1901586592	8029	0	0
T1	3796216	142	0	0
T3	0	80	0	0
T5	513876	0	0	0
T13	0	34	0	0
T19	7520	0	0	0
T20	33996	0	0	0
T21	18312	0	0	0
T22	396000	0	0	0
T23	40532	0	0	0
T24	16328	0	0	0
T25	13124	0	0	0
T26	9220	7	0	0
T39	0	33	0	0
T41	0	4	0	0
T44	0	17	0	0
T61	0	11	0	0
T95	0	3	0	0
T96	0	4	0	0
T97	0	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	475396648	3936	0	0
TransStop_A	475396648	1995	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475396648	3936	0	0
T1	949054	66	0	0
T3	0	35	0	0
T5	128469	0	0	0
T19	1880	0	0	0
T20	8499	0	0	0
T21	4578	0	0	0
T22	99000	0	0	0
T23	10133	0	0	0
T24	4082	0	0	0
T25	3281	0	0	0
T26	2305	5	0	0
T39	0	21	0	0
T41	0	1	0	0
T44	0	4	0	0
T61	0	7	0	0
T95	0	9	0	0
T96	0	1	0	0
T97	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475396648	1995	0	0
T1	949054	33	0	0
T3	0	21	0	0
T5	128469	0	0	0
T13	0	34	0	0
T19	1880	0	0	0
T20	8499	0	0	0
T21	4578	0	0	0
T22	99000	0	0	0
T23	10133	0	0	0
T24	4082	0	0	0
T25	3281	0	0	0
T26	2305	1	0	0
T39	0	9	0	0
T41	0	1	0	0
T44	0	3	0	0
T61	0	4	0	0
T96	0	1	0	0
T97	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	475396648	3916	0	0
TransStop_A	475396648	2008	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475396648	3916	0	0
T1	949054	73	0	0
T3	0	36	0	0
T5	128469	0	0	0
T19	1880	0	0	0
T20	8499	0	0	0
T21	4578	0	0	0
T22	99000	0	0	0
T23	10133	0	0	0
T24	4082	0	0	0
T25	3281	0	0	0
T26	2305	5	0	0
T39	0	16	0	0
T41	0	1	0	0
T44	0	9	0	0
T61	0	8	0	0
T95	0	6	0	0
T96	0	1	0	0
T97	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475396648	2008	0	0
T1	949054	30	0	0
T3	0	23	0	0
T5	128469	0	0	0
T19	1880	0	0	0
T20	8499	0	0	0
T21	4578	0	0	0
T22	99000	0	0	0
T23	10133	0	0	0
T24	4082	0	0	0
T25	3281	0	0	0
T26	2305	3	0	0
T39	0	10	0	0
T41	0	1	0	0
T44	0	6	0	0
T61	0	2	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	475396648	3893	0	0
TransStop_A	475396648	1972	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475396648	3893	0	0
T1	949054	77	0	0
T3	0	32	0	0
T5	128469	0	0	0
T19	1880	0	0	0
T20	8499	0	0	0
T21	4578	0	0	0
T22	99000	0	0	0
T23	10133	0	0	0
T24	4082	0	0	0
T25	3281	0	0	0
T26	2305	4	0	0
T39	0	18	0	0
T41	0	1	0	0
T44	0	9	0	0
T61	0	7	0	0
T95	0	6	0	0
T96	0	1	0	0
T97	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475396648	1972	0	0
T1	949054	37	0	0
T3	0	18	0	0
T5	128469	0	0	0
T19	1880	0	0	0
T20	8499	0	0	0
T21	4578	0	0	0
T22	99000	0	0	0
T23	10133	0	0	0
T24	4082	0	0	0
T25	3281	0	0	0
T26	2305	1	0	0
T39	0	6	0	0
T41	0	1	0	0
T44	0	5	0	0
T61	0	2	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	475396648	4039	0	0
TransStop_A	475396648	2054	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475396648	4039	0	0
T1	949054	75	0	0
T3	0	31	0	0
T5	128469	0	0	0
T19	1880	0	0	0
T20	8499	0	0	0
T21	4578	0	0	0
T22	99000	0	0	0
T23	10133	0	0	0
T24	4082	0	0	0
T25	3281	0	0	0
T26	2305	5	0	0
T39	0	16	0	0
T41	0	1	0	0
T44	0	6	0	0
T61	0	8	0	0
T95	0	6	0	0
T96	0	1	0	0
T97	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475396648	2054	0	0
T1	949054	42	0	0
T3	0	18	0	0
T5	128469	0	0	0
T19	1880	0	0	0
T20	8499	0	0	0
T21	4578	0	0	0
T22	99000	0	0	0
T23	10133	0	0	0
T24	4082	0	0	0
T25	3281	0	0	0
T26	2305	2	0	0
T39	0	8	0	0
T41	0	1	0	0
T44	0	3	0	0
T61	0	3	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	2	0	0